Merge branch 'next' of git://git.infradead.org/users/vkoul/slave-dma
Pull second set of slave-dmaengine updates from Vinod Koul:
"Arnd's patch moves the dw_dmac to use generic DMA binding. I agreed
to merge this late as it will avoid the conflicts between trees.
The second patch from Matt adding a dma_request_slave_channel_compat
API was supposed to be picked up, but somehow never got picked up.
Some patches dependent on this are already in -next :("
* 'next' of git://git.infradead.org/users/vkoul/slave-dma:
dmaengine: dw_dmac: move to generic DMA binding
dmaengine: add dma_request_slave_channel_compat()
This commit is contained in:
Linus Torvalds
commit
527c680f7c
5 changed files with 128 additions and 117 deletions
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@ -3,59 +3,61 @@
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Required properties:
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- compatible: "snps,dma-spear1340"
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- reg: Address range of the DMAC registers
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- interrupt-parent: Should be the phandle for the interrupt controller
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that services interrupts for this device
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- interrupt: Should contain the DMAC interrupt number
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- nr_channels: Number of channels supported by hardware
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- is_private: The device channels should be marked as private and not for by the
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general purpose DMA channel allocator. False if not passed.
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- dma-channels: Number of channels supported by hardware
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- dma-requests: Number of DMA request lines supported, up to 16
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- dma-masters: Number of AHB masters supported by the controller
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- #dma-cells: must be <3>
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- chan_allocation_order: order of allocation of channel, 0 (default): ascending,
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1: descending
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- chan_priority: priority of channels. 0 (default): increase from chan 0->n, 1:
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increase from chan n->0
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- block_size: Maximum block size supported by the controller
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- nr_masters: Number of AHB masters supported by the controller
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- data_width: Maximum data width supported by hardware per AHB master
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(0 - 8bits, 1 - 16bits, ..., 5 - 256bits)
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- slave_info:
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- bus_id: name of this device channel, not just a device name since
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devices may have more than one channel e.g. "foo_tx". For using the
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dw_generic_filter(), slave drivers must pass exactly this string as
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param to filter function.
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- cfg_hi: Platform-specific initializer for the CFG_HI register
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- cfg_lo: Platform-specific initializer for the CFG_LO register
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- src_master: src master for transfers on allocated channel.
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- dst_master: dest master for transfers on allocated channel.
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Optional properties:
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- interrupt-parent: Should be the phandle for the interrupt controller
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that services interrupts for this device
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- is_private: The device channels should be marked as private and not for by the
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general purpose DMA channel allocator. False if not passed.
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Example:
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dma@fc000000 {
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dmahost: dma@fc000000 {
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compatible = "snps,dma-spear1340";
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reg = <0xfc000000 0x1000>;
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interrupt-parent = <&vic1>;
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interrupts = <12>;
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nr_channels = <8>;
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dma-channels = <8>;
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dma-requests = <16>;
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dma-masters = <2>;
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#dma-cells = <3>;
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chan_allocation_order = <1>;
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chan_priority = <1>;
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block_size = <0xfff>;
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nr_masters = <2>;
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data_width = <3 3 0 0>;
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slave_info {
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uart0-tx {
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bus_id = "uart0-tx";
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cfg_hi = <0x4000>; /* 0x8 << 11 */
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cfg_lo = <0>;
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src_master = <0>;
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dst_master = <1>;
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};
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spi0-tx {
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bus_id = "spi0-tx";
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cfg_hi = <0x2000>; /* 0x4 << 11 */
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cfg_lo = <0>;
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src_master = <0>;
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dst_master = <0>;
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};
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};
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};
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DMA clients connected to the Designware DMA controller must use the format
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described in the dma.txt file, using a four-cell specifier for each channel.
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The four cells in order are:
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1. A phandle pointing to the DMA controller
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2. The DMA request line number
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3. Source master for transfers on allocated channel
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4. Destination master for transfers on allocated channel
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Example:
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serial@e0000000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0xe0000000 0x1000>;
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interrupts = <0 35 0x4>;
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status = "disabled";
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dmas = <&dmahost 12 0 1>,
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<&dmahost 13 0 1 0>;
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dma-names = "rx", "rx";
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};
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@ -20,6 +20,7 @@
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_dma.h>
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#include <linux/mm.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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@ -171,7 +172,13 @@ static void dwc_initialize(struct dw_dma_chan *dwc)
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if (dwc->initialized == true)
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return;
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if (dws) {
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if (dws && dws->cfg_hi == ~0 && dws->cfg_lo == ~0) {
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/* autoconfigure based on request line from DT */
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if (dwc->direction == DMA_MEM_TO_DEV)
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cfghi = DWC_CFGH_DST_PER(dwc->request_line);
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else if (dwc->direction == DMA_DEV_TO_MEM)
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cfghi = DWC_CFGH_SRC_PER(dwc->request_line);
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} else if (dws) {
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/*
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* We need controller-specific data to set up slave
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* transfers.
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@ -1226,49 +1233,64 @@ static void dwc_free_chan_resources(struct dma_chan *chan)
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dev_vdbg(chan2dev(chan), "%s: done\n", __func__);
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}
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bool dw_dma_generic_filter(struct dma_chan *chan, void *param)
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struct dw_dma_filter_args {
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struct dw_dma *dw;
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unsigned int req;
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unsigned int src;
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unsigned int dst;
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};
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static bool dw_dma_generic_filter(struct dma_chan *chan, void *param)
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{
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struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
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struct dw_dma *dw = to_dw_dma(chan->device);
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static struct dw_dma *last_dw;
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static char *last_bus_id;
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int i = -1;
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struct dw_dma_filter_args *fargs = param;
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struct dw_dma_slave *dws = &dwc->slave;
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/*
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* dmaengine framework calls this routine for all channels of all dma
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* controller, until true is returned. If 'param' bus_id is not
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* registered with a dma controller (dw), then there is no need of
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* running below function for all channels of dw.
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*
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* This block of code does this by saving the parameters of last
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* failure. If dw and param are same, i.e. trying on same dw with
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* different channel, return false.
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*/
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if ((last_dw == dw) && (last_bus_id == param))
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return false;
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/*
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* Return true:
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* - If dw_dma's platform data is not filled with slave info, then all
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* dma controllers are fine for transfer.
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* - Or if param is NULL
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*/
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if (!dw->sd || !param)
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return true;
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/* ensure the device matches our channel */
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if (chan->device != &fargs->dw->dma)
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return false;
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while (++i < dw->sd_count) {
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if (!strcmp(dw->sd[i].bus_id, param)) {
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chan->private = &dw->sd[i];
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last_dw = NULL;
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last_bus_id = NULL;
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dws->dma_dev = dw->dma.dev;
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dws->cfg_hi = ~0;
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dws->cfg_lo = ~0;
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dws->src_master = fargs->src;
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dws->dst_master = fargs->dst;
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return true;
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}
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}
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dwc->request_line = fargs->req;
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last_dw = dw;
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last_bus_id = param;
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return false;
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chan->private = dws;
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return true;
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}
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static struct dma_chan *dw_dma_xlate(struct of_phandle_args *dma_spec,
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struct of_dma *ofdma)
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{
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struct dw_dma *dw = ofdma->of_dma_data;
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struct dw_dma_filter_args fargs = {
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.dw = dw,
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};
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dma_cap_mask_t cap;
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if (dma_spec->args_count != 3)
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return NULL;
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fargs.req = be32_to_cpup(dma_spec->args+0);
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fargs.src = be32_to_cpup(dma_spec->args+1);
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fargs.dst = be32_to_cpup(dma_spec->args+2);
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if (WARN_ON(fargs.req >= DW_DMA_MAX_NR_REQUESTS ||
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fargs.src >= dw->nr_masters ||
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fargs.dst >= dw->nr_masters))
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return NULL;
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dma_cap_zero(cap);
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dma_cap_set(DMA_SLAVE, cap);
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/* TODO: there should be a simpler way to do this */
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return dma_request_channel(cap, dw_dma_generic_filter, &fargs);
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}
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EXPORT_SYMBOL(dw_dma_generic_filter);
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/* --------------------- Cyclic DMA API extensions -------------------- */
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@ -1554,9 +1576,8 @@ static void dw_dma_off(struct dw_dma *dw)
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static struct dw_dma_platform_data *
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dw_dma_parse_dt(struct platform_device *pdev)
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{
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struct device_node *sn, *cn, *np = pdev->dev.of_node;
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struct device_node *np = pdev->dev.of_node;
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struct dw_dma_platform_data *pdata;
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struct dw_dma_slave *sd;
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u32 tmp, arr[4];
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if (!np) {
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@ -1568,7 +1589,7 @@ dw_dma_parse_dt(struct platform_device *pdev)
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if (!pdata)
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return NULL;
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if (of_property_read_u32(np, "nr_channels", &pdata->nr_channels))
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if (of_property_read_u32(np, "dma-channels", &pdata->nr_channels))
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return NULL;
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if (of_property_read_bool(np, "is_private"))
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@ -1583,7 +1604,7 @@ dw_dma_parse_dt(struct platform_device *pdev)
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if (!of_property_read_u32(np, "block_size", &tmp))
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pdata->block_size = tmp;
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if (!of_property_read_u32(np, "nr_masters", &tmp)) {
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if (!of_property_read_u32(np, "dma-masters", &tmp)) {
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if (tmp > 4)
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return NULL;
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@ -1595,36 +1616,6 @@ dw_dma_parse_dt(struct platform_device *pdev)
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for (tmp = 0; tmp < pdata->nr_masters; tmp++)
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pdata->data_width[tmp] = arr[tmp];
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/* parse slave data */
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sn = of_find_node_by_name(np, "slave_info");
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if (!sn)
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return pdata;
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/* calculate number of slaves */
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tmp = of_get_child_count(sn);
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if (!tmp)
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return NULL;
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sd = devm_kzalloc(&pdev->dev, sizeof(*sd) * tmp, GFP_KERNEL);
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if (!sd)
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return NULL;
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pdata->sd = sd;
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pdata->sd_count = tmp;
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for_each_child_of_node(sn, cn) {
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sd->dma_dev = &pdev->dev;
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of_property_read_string(cn, "bus_id", &sd->bus_id);
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of_property_read_u32(cn, "cfg_hi", &sd->cfg_hi);
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of_property_read_u32(cn, "cfg_lo", &sd->cfg_lo);
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if (!of_property_read_u32(cn, "src_master", &tmp))
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sd->src_master = tmp;
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if (!of_property_read_u32(cn, "dst_master", &tmp))
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sd->dst_master = tmp;
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sd++;
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}
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return pdata;
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}
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#else
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@ -1705,8 +1696,6 @@ static int dw_probe(struct platform_device *pdev)
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clk_prepare_enable(dw->clk);
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dw->regs = regs;
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dw->sd = pdata->sd;
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dw->sd_count = pdata->sd_count;
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/* get hardware configuration parameters */
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if (autocfg) {
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@ -1837,6 +1826,14 @@ static int dw_probe(struct platform_device *pdev)
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dma_async_device_register(&dw->dma);
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if (pdev->dev.of_node) {
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err = of_dma_controller_register(pdev->dev.of_node,
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dw_dma_xlate, dw);
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if (err && err != -ENODEV)
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dev_err(&pdev->dev,
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"could not register of_dma_controller\n");
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}
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return 0;
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}
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@ -1845,6 +1842,8 @@ static int dw_remove(struct platform_device *pdev)
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struct dw_dma *dw = platform_get_drvdata(pdev);
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struct dw_dma_chan *dwc, *_dwc;
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if (pdev->dev.of_node)
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of_dma_controller_free(pdev->dev.of_node);
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dw_dma_off(dw);
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dma_async_device_unregister(&dw->dma);
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@ -13,6 +13,7 @@
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#include <linux/dw_dmac.h>
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#define DW_DMA_MAX_NR_CHANNELS 8
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#define DW_DMA_MAX_NR_REQUESTS 16
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/* flow controller */
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enum dw_dma_fc {
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@ -211,6 +212,8 @@ struct dw_dma_chan {
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/* hardware configuration */
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unsigned int block_size;
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bool nollp;
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unsigned int request_line;
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struct dw_dma_slave slave;
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/* configuration passed via DMA_SLAVE_CONFIG */
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struct dma_slave_config dma_sconfig;
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@ -239,10 +242,6 @@ struct dw_dma {
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struct tasklet_struct tasklet;
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struct clk *clk;
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/* slave information */
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struct dw_dma_slave *sd;
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unsigned int sd_count;
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u8 all_chan_mask;
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/* hardware configuration */
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@ -1001,6 +1001,22 @@ void dma_run_dependencies(struct dma_async_tx_descriptor *tx);
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struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type);
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struct dma_chan *net_dma_find_channel(void);
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#define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y)
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#define dma_request_slave_channel_compat(mask, x, y, dev, name) \
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__dma_request_slave_channel_compat(&(mask), x, y, dev, name)
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static inline struct dma_chan
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*__dma_request_slave_channel_compat(dma_cap_mask_t *mask, dma_filter_fn fn,
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void *fn_param, struct device *dev,
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char *name)
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{
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struct dma_chan *chan;
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chan = dma_request_slave_channel(dev, name);
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if (chan)
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return chan;
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return __dma_request_channel(mask, fn, fn_param);
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}
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/* --- Helper iov-locking functions --- */
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|
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@ -27,7 +27,6 @@
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*/
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struct dw_dma_slave {
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struct device *dma_dev;
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const char *bus_id;
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u32 cfg_hi;
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u32 cfg_lo;
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u8 src_master;
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@ -60,9 +59,6 @@ struct dw_dma_platform_data {
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unsigned short block_size;
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unsigned char nr_masters;
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unsigned char data_width[4];
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struct dw_dma_slave *sd;
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unsigned int sd_count;
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};
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/* bursts size */
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@ -114,6 +110,5 @@ void dw_dma_cyclic_stop(struct dma_chan *chan);
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dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan);
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dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan);
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bool dw_dma_generic_filter(struct dma_chan *chan, void *param);
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#endif /* DW_DMAC_H */
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