phy: Add support for NS2 SATA3 PHY in Broadcom SATA3 PHY driver
This patch adds support for Broadcom NS2 SATA3 PHY in existing Broadcom SATA3 PHY driver. Signed-off-by: Anup Patel <anup.patel@broadcom.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
This commit is contained in:
Anup Patel
Kishon Vijay Abraham I
parent
037c418945
commit
4faee9a43d
3 changed files with 211 additions and 48 deletions
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@ -403,15 +403,6 @@ config PHY_TUSB1210
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help
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Support for TI TUSB1210 USB ULPI PHY.
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config PHY_CYGNUS_PCIE
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tristate "Broadcom Cygnus PCIe PHY driver"
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depends on OF && (ARCH_BCM_CYGNUS || COMPILE_TEST)
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select GENERIC_PHY
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default ARCH_BCM_CYGNUS
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help
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Enable this to support the Broadcom Cygnus PCIe PHY.
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If unsure, say N.
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config PHY_BRCM_SATA
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tristate "Broadcom SATA PHY driver"
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depends on ARCH_BRCMSTB || ARCH_BCM_IPROC || BMIPS_GENERIC || COMPILE_TEST
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@ -421,4 +412,14 @@ config PHY_BRCM_SATA
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help
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Enable this to support the Broadcom SATA PHY.
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If unsure, say N.
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config PHY_CYGNUS_PCIE
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tristate "Broadcom Cygnus PCIe PHY driver"
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depends on OF && (ARCH_BCM_CYGNUS || COMPILE_TEST)
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select GENERIC_PHY
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default ARCH_BCM_CYGNUS
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help
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Enable this to support the Broadcom Cygnus PCIe PHY.
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If unsure, say N.
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endmenu
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@ -49,6 +49,6 @@ obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs.o
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obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs-qmp-20nm.o
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obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs-qmp-14nm.o
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obj-$(CONFIG_PHY_TUSB1210) += phy-tusb1210.o
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obj-$(CONFIG_PHY_BRCM_SATA) += phy-brcm-sata.o
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obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o
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obj-$(CONFIG_PHY_CYGNUS_PCIE) += phy-bcm-cygnus-pcie.o
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obj-$(CONFIG_PHY_BRCM_SATA) += phy-brcm-sata.o
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@ -14,6 +14,7 @@
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* GNU General Public License for more details.
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*/
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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@ -24,22 +25,26 @@
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#define SATA_MDIO_BANK_OFFSET 0x23c
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#define SATA_MDIO_REG_OFFSET(ofs) ((ofs) * 4)
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#define SATA_PCB_BANK_OFFSET 0x23c
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#define SATA_PCB_REG_OFFSET(ofs) ((ofs) * 4)
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#define MAX_PORTS 2
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/* Register offset between PHYs in PCB space */
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#define SATA_MDIO_REG_28NM_SPACE_SIZE 0x1000
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#define SATA_PCB_REG_28NM_SPACE_SIZE 0x1000
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/* The older SATA PHY registers duplicated per port registers within the map,
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* rather than having a separate map per port.
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*/
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#define SATA_MDIO_REG_40NM_SPACE_SIZE 0x10
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#define SATA_PCB_REG_40NM_SPACE_SIZE 0x10
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/* Register offset between PHYs in PHY control space */
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#define SATA_PHY_CTRL_REG_28NM_SPACE_SIZE 0x8
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enum brcm_sata_phy_version {
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BRCM_SATA_PHY_28NM,
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BRCM_SATA_PHY_40NM,
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BRCM_SATA_PHY_STB_28NM,
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BRCM_SATA_PHY_STB_40NM,
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BRCM_SATA_PHY_IPROC_NS2,
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};
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struct brcm_sata_port {
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@ -52,15 +57,48 @@ struct brcm_sata_port {
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struct brcm_sata_phy {
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struct device *dev;
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void __iomem *phy_base;
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void __iomem *ctrl_base;
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enum brcm_sata_phy_version version;
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struct brcm_sata_port phys[MAX_PORTS];
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};
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enum sata_mdio_phy_regs {
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PLL_REG_BANK_0 = 0x50,
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enum sata_phy_regs {
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BLOCK0_REG_BANK = 0x000,
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BLOCK0_XGXSSTATUS = 0x81,
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BLOCK0_XGXSSTATUS_PLL_LOCK = BIT(12),
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BLOCK0_SPARE = 0x8d,
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BLOCK0_SPARE_OOB_CLK_SEL_MASK = 0x3,
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BLOCK0_SPARE_OOB_CLK_SEL_REFBY2 = 0x1,
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PLL_REG_BANK_0 = 0x050,
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PLL_REG_BANK_0_PLLCONTROL_0 = 0x81,
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PLL1_REG_BANK = 0x060,
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PLL1_ACTRL2 = 0x82,
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PLL1_ACTRL3 = 0x83,
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PLL1_ACTRL4 = 0x84,
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OOB_REG_BANK = 0x150,
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OOB_CTRL1 = 0x80,
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OOB_CTRL1_BURST_MAX_MASK = 0xf,
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OOB_CTRL1_BURST_MAX_SHIFT = 12,
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OOB_CTRL1_BURST_MIN_MASK = 0xf,
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OOB_CTRL1_BURST_MIN_SHIFT = 8,
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OOB_CTRL1_WAKE_IDLE_MAX_MASK = 0xf,
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OOB_CTRL1_WAKE_IDLE_MAX_SHIFT = 4,
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OOB_CTRL1_WAKE_IDLE_MIN_MASK = 0xf,
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OOB_CTRL1_WAKE_IDLE_MIN_SHIFT = 0,
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OOB_CTRL2 = 0x81,
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OOB_CTRL2_SEL_ENA_SHIFT = 15,
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OOB_CTRL2_SEL_ENA_RC_SHIFT = 14,
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OOB_CTRL2_RESET_IDLE_MAX_MASK = 0x3f,
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OOB_CTRL2_RESET_IDLE_MAX_SHIFT = 8,
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OOB_CTRL2_BURST_CNT_MASK = 0x3,
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OOB_CTRL2_BURST_CNT_SHIFT = 6,
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OOB_CTRL2_RESET_IDLE_MIN_MASK = 0x3f,
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OOB_CTRL2_RESET_IDLE_MIN_SHIFT = 0,
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TXPMD_REG_BANK = 0x1a0,
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TXPMD_CONTROL1 = 0x81,
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TXPMD_CONTROL1_TX_SSC_EN_FRC = BIT(0),
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@ -72,69 +110,183 @@ enum sata_mdio_phy_regs {
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TXPMD_TX_FREQ_CTRL_CONTROL3_FMAX_MASK = 0x3ff,
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};
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static inline void __iomem *brcm_sata_phy_base(struct brcm_sata_port *port)
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enum sata_phy_ctrl_regs {
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PHY_CTRL_1 = 0x0,
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PHY_CTRL_1_RESET = BIT(0),
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};
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static inline void __iomem *brcm_sata_pcb_base(struct brcm_sata_port *port)
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{
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struct brcm_sata_phy *priv = port->phy_priv;
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u32 offset = 0;
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u32 size = 0;
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if (priv->version == BRCM_SATA_PHY_28NM)
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offset = SATA_MDIO_REG_28NM_SPACE_SIZE;
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else if (priv->version == BRCM_SATA_PHY_40NM)
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offset = SATA_MDIO_REG_40NM_SPACE_SIZE;
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else
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switch (priv->version) {
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case BRCM_SATA_PHY_STB_28NM:
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case BRCM_SATA_PHY_IPROC_NS2:
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size = SATA_PCB_REG_28NM_SPACE_SIZE;
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break;
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case BRCM_SATA_PHY_STB_40NM:
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size = SATA_PCB_REG_40NM_SPACE_SIZE;
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break;
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default:
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dev_err(priv->dev, "invalid phy version\n");
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break;
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};
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return priv->phy_base + (port->portnum * offset);
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return priv->phy_base + (port->portnum * size);
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}
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static void brcm_sata_mdio_wr(void __iomem *addr, u32 bank, u32 ofs,
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u32 msk, u32 value)
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static inline void __iomem *brcm_sata_ctrl_base(struct brcm_sata_port *port)
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{
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struct brcm_sata_phy *priv = port->phy_priv;
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u32 size = 0;
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switch (priv->version) {
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case BRCM_SATA_PHY_IPROC_NS2:
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size = SATA_PHY_CTRL_REG_28NM_SPACE_SIZE;
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break;
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default:
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dev_err(priv->dev, "invalid phy version\n");
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break;
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};
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return priv->ctrl_base + (port->portnum * size);
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}
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static void brcm_sata_phy_wr(void __iomem *pcb_base, u32 bank,
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u32 ofs, u32 msk, u32 value)
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{
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u32 tmp;
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writel(bank, addr + SATA_MDIO_BANK_OFFSET);
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tmp = readl(addr + SATA_MDIO_REG_OFFSET(ofs));
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writel(bank, pcb_base + SATA_PCB_BANK_OFFSET);
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tmp = readl(pcb_base + SATA_PCB_REG_OFFSET(ofs));
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tmp = (tmp & msk) | value;
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writel(tmp, addr + SATA_MDIO_REG_OFFSET(ofs));
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writel(tmp, pcb_base + SATA_PCB_REG_OFFSET(ofs));
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}
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static u32 brcm_sata_phy_rd(void __iomem *pcb_base, u32 bank, u32 ofs)
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{
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writel(bank, pcb_base + SATA_PCB_BANK_OFFSET);
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return readl(pcb_base + SATA_PCB_REG_OFFSET(ofs));
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}
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/* These defaults were characterized by H/W group */
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#define FMIN_VAL_DEFAULT 0x3df
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#define FMAX_VAL_DEFAULT 0x3df
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#define FMAX_VAL_SSC 0x83
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#define STB_FMIN_VAL_DEFAULT 0x3df
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#define STB_FMAX_VAL_DEFAULT 0x3df
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#define STB_FMAX_VAL_SSC 0x83
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static void brcm_sata_cfg_ssc(struct brcm_sata_port *port)
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static int brcm_stb_sata_init(struct brcm_sata_port *port)
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{
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void __iomem *base = brcm_sata_phy_base(port);
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void __iomem *base = brcm_sata_pcb_base(port);
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struct brcm_sata_phy *priv = port->phy_priv;
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u32 tmp;
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/* override the TX spread spectrum setting */
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tmp = TXPMD_CONTROL1_TX_SSC_EN_FRC_VAL | TXPMD_CONTROL1_TX_SSC_EN_FRC;
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brcm_sata_mdio_wr(base, TXPMD_REG_BANK, TXPMD_CONTROL1, ~tmp, tmp);
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brcm_sata_phy_wr(base, TXPMD_REG_BANK, TXPMD_CONTROL1, ~tmp, tmp);
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/* set fixed min freq */
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brcm_sata_mdio_wr(base, TXPMD_REG_BANK, TXPMD_TX_FREQ_CTRL_CONTROL2,
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~TXPMD_TX_FREQ_CTRL_CONTROL2_FMIN_MASK,
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FMIN_VAL_DEFAULT);
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brcm_sata_phy_wr(base, TXPMD_REG_BANK, TXPMD_TX_FREQ_CTRL_CONTROL2,
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~TXPMD_TX_FREQ_CTRL_CONTROL2_FMIN_MASK,
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STB_FMIN_VAL_DEFAULT);
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/* set fixed max freq depending on SSC config */
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if (port->ssc_en) {
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dev_info(priv->dev, "enabling SSC on port %d\n", port->portnum);
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tmp = FMAX_VAL_SSC;
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dev_info(priv->dev, "enabling SSC on port%d\n", port->portnum);
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tmp = STB_FMAX_VAL_SSC;
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} else {
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tmp = FMAX_VAL_DEFAULT;
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tmp = STB_FMAX_VAL_DEFAULT;
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}
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brcm_sata_mdio_wr(base, TXPMD_REG_BANK, TXPMD_TX_FREQ_CTRL_CONTROL3,
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brcm_sata_phy_wr(base, TXPMD_REG_BANK, TXPMD_TX_FREQ_CTRL_CONTROL3,
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~TXPMD_TX_FREQ_CTRL_CONTROL3_FMAX_MASK, tmp);
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return 0;
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}
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/* NS2 SATA PLL1 defaults were characterized by H/W group */
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#define NS2_PLL1_ACTRL2_MAGIC 0x1df8
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#define NS2_PLL1_ACTRL3_MAGIC 0x2b00
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#define NS2_PLL1_ACTRL4_MAGIC 0x8824
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static int brcm_ns2_sata_init(struct brcm_sata_port *port)
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{
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int try;
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unsigned int val;
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void __iomem *base = brcm_sata_pcb_base(port);
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void __iomem *ctrl_base = brcm_sata_ctrl_base(port);
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struct device *dev = port->phy_priv->dev;
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/* Configure OOB control */
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val = 0x0;
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val |= (0xc << OOB_CTRL1_BURST_MAX_SHIFT);
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val |= (0x4 << OOB_CTRL1_BURST_MIN_SHIFT);
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val |= (0x9 << OOB_CTRL1_WAKE_IDLE_MAX_SHIFT);
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val |= (0x3 << OOB_CTRL1_WAKE_IDLE_MIN_SHIFT);
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brcm_sata_phy_wr(base, OOB_REG_BANK, OOB_CTRL1, 0x0, val);
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val = 0x0;
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val |= (0x1b << OOB_CTRL2_RESET_IDLE_MAX_SHIFT);
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val |= (0x2 << OOB_CTRL2_BURST_CNT_SHIFT);
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val |= (0x9 << OOB_CTRL2_RESET_IDLE_MIN_SHIFT);
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brcm_sata_phy_wr(base, OOB_REG_BANK, OOB_CTRL2, 0x0, val);
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/* Configure PHY PLL register bank 1 */
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val = NS2_PLL1_ACTRL2_MAGIC;
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brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL2, 0x0, val);
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val = NS2_PLL1_ACTRL3_MAGIC;
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brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL3, 0x0, val);
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val = NS2_PLL1_ACTRL4_MAGIC;
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brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL4, 0x0, val);
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/* Configure PHY BLOCK0 register bank */
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/* Set oob_clk_sel to refclk/2 */
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brcm_sata_phy_wr(base, BLOCK0_REG_BANK, BLOCK0_SPARE,
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~BLOCK0_SPARE_OOB_CLK_SEL_MASK,
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BLOCK0_SPARE_OOB_CLK_SEL_REFBY2);
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/* Strobe PHY reset using PHY control register */
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writel(PHY_CTRL_1_RESET, ctrl_base + PHY_CTRL_1);
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mdelay(1);
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writel(0x0, ctrl_base + PHY_CTRL_1);
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mdelay(1);
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/* Wait for PHY PLL lock by polling pll_lock bit */
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try = 50;
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while (try) {
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val = brcm_sata_phy_rd(base, BLOCK0_REG_BANK,
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BLOCK0_XGXSSTATUS);
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if (val & BLOCK0_XGXSSTATUS_PLL_LOCK)
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break;
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msleep(20);
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try--;
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}
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if (!try) {
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/* PLL did not lock; give up */
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dev_err(dev, "port%d PLL did not lock\n", port->portnum);
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return -ETIMEDOUT;
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}
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dev_dbg(dev, "port%d initialized\n", port->portnum);
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return 0;
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}
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static int brcm_sata_phy_init(struct phy *phy)
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{
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int rc;
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struct brcm_sata_port *port = phy_get_drvdata(phy);
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brcm_sata_cfg_ssc(port);
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switch (port->phy_priv->version) {
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case BRCM_SATA_PHY_STB_28NM:
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case BRCM_SATA_PHY_STB_40NM:
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rc = brcm_stb_sata_init(port);
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break;
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case BRCM_SATA_PHY_IPROC_NS2:
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rc = brcm_ns2_sata_init(port);
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break;
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default:
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rc = -ENODEV;
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};
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return 0;
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}
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@ -146,9 +298,11 @@ static const struct phy_ops phy_ops = {
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static const struct of_device_id brcm_sata_phy_of_match[] = {
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{ .compatible = "brcm,bcm7445-sata-phy",
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.data = (void *)BRCM_SATA_PHY_28NM },
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.data = (void *)BRCM_SATA_PHY_STB_28NM },
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{ .compatible = "brcm,bcm7425-sata-phy",
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.data = (void *)BRCM_SATA_PHY_40NM },
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.data = (void *)BRCM_SATA_PHY_STB_40NM },
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{ .compatible = "brcm,iproc-ns2-sata-phy",
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.data = (void *)BRCM_SATA_PHY_IPROC_NS2 },
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{},
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};
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MODULE_DEVICE_TABLE(of, brcm_sata_phy_of_match);
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@ -181,7 +335,15 @@ static int brcm_sata_phy_probe(struct platform_device *pdev)
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if (of_id)
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priv->version = (enum brcm_sata_phy_version)of_id->data;
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else
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priv->version = BRCM_SATA_PHY_28NM;
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priv->version = BRCM_SATA_PHY_STB_28NM;
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if (priv->version == BRCM_SATA_PHY_IPROC_NS2) {
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
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"phy-ctrl");
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priv->ctrl_base = devm_ioremap_resource(dev, res);
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if (IS_ERR(priv->ctrl_base))
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return PTR_ERR(priv->ctrl_base);
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}
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for_each_available_child_of_node(dn, child) {
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unsigned int id;
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