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MIPS: Oprofile: Fix Loongson irq handler

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The interrupt enable bit for the performance counters is in the Control
    Register $24, not in the counter register.
    loongson2_perfcount_handler(), we need to use
    
    Reported-by: Xu Hengyang <hengyang@mail.ustc.edu.cn>
    Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com>
    Cc: linux-mips@linux-mips.org
    Patchwork: http://patchwork.linux-mips.org/patch/1198/
    Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

---
This commit is contained in:
Wu Zhangjin 2010-05-07 00:59:46 +08:00 committed by Ralf Baechle
parent 46afb8296c
commit 4e73238d16
1 changed files with 1 additions and 1 deletions
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arch/mips/oprofile/op_model_loongson2.c
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@ -122,7 +122,7 @@ static irqreturn_t loongson2_perfcount_handler(int irq, void *dev_id)
*/
/* Check whether the irq belongs to me */
enabled = read_c0_perfcnt() & LOONGSON2_PERFCNT_INT_EN;
enabled = read_c0_perfctrl() & LOONGSON2_PERFCNT_INT_EN;
if (!enabled)
return IRQ_NONE;
enabled = reg.cnt1_enabled | reg.cnt2_enabled;