Techwizz/kernel-fxtec-pro1x
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

ARM: plat-mxc: irq_data conversion.

Browse source 
Signed-off-by: Lennert Buytenhek <buytenh@secretlab.ca>
This commit is contained in:
Lennert Buytenhek 2010-11-29 11:16:23 +01:00
parent b9858efad3
commit 4d93579f63
4 changed files with 55 additions and 55 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

28
arch/arm/plat-mxc/3ds_debugboard.c
View file

@ -60,7 +60,6 @@
#define EXPIO_INT_BUTTON_B (MXC_BOARD_IRQ_START + 4)
static void __iomem *brd_io;
static void expio_ack_irq(u32 irq);
static struct resource smsc911x_resources[] = {
{
@ -93,7 +92,8 @@ static void mxc_expio_irq_handler(u32 irq, struct irq_desc *desc)
u32 int_valid;
u32 expio_irq;
desc->chip->mask(irq); /* irq = gpio irq number */
/* irq = gpio irq number */
desc->irq_data.chip->irq_mask(&desc->irq_data);
imr_val = __raw_readw(brd_io + INTR_MASK_REG);
int_valid = __raw_readw(brd_io + INTR_STATUS_REG) & ~imr_val;
@ -110,37 +110,37 @@ static void mxc_expio_irq_handler(u32 irq, struct irq_desc *desc)
d->handle_irq(expio_irq, d);
}
desc->chip->ack(irq);
desc->chip->unmask(irq);
desc->irq_data.chip->irq_ack(&desc->irq_data);
desc->irq_data.chip->irq_unmask(&desc->irq_data);
}
/*
* Disable an expio pin's interrupt by setting the bit in the imr.
* Irq is an expio virtual irq number
*/
static void expio_mask_irq(u32 irq)
static void expio_mask_irq(struct irq_data *d)
{
u16 reg;
u32 expio = MXC_IRQ_TO_EXPIO(irq);
u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
reg = __raw_readw(brd_io + INTR_MASK_REG);
reg |= (1 << expio);
__raw_writew(reg, brd_io + INTR_MASK_REG);
}
static void expio_ack_irq(u32 irq)
static void expio_ack_irq(struct irq_data *d)
{
u32 expio = MXC_IRQ_TO_EXPIO(irq);
u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
__raw_writew(1 << expio, brd_io + INTR_RESET_REG);
__raw_writew(0, brd_io + INTR_RESET_REG);
expio_mask_irq(irq);
expio_mask_irq(d);
}
static void expio_unmask_irq(u32 irq)
static void expio_unmask_irq(struct irq_data *d)
{
u16 reg;
u32 expio = MXC_IRQ_TO_EXPIO(irq);
u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
reg = __raw_readw(brd_io + INTR_MASK_REG);
reg &= ~(1 << expio);
@ -148,9 +148,9 @@ static void expio_unmask_irq(u32 irq)
}
static struct irq_chip expio_irq_chip = {
.ack = expio_ack_irq,
.mask = expio_mask_irq,
.unmask = expio_unmask_irq,
.irq_ack = expio_ack_irq,
.irq_mask = expio_mask_irq,
.irq_unmask = expio_unmask_irq,
};
int __init mxc_expio_init(u32 base, u32 p_irq)

14
arch/arm/plat-mxc/avic.c
View file

@ -89,22 +89,22 @@ static int avic_set_irq_fiq(unsigned int irq, unsigned int type)
#endif /* CONFIG_FIQ */
/* Disable interrupt number "irq" in the AVIC */
static void mxc_mask_irq(unsigned int irq)
static void mxc_mask_irq(struct irq_data *d)
{
__raw_writel(irq, avic_base + AVIC_INTDISNUM);
__raw_writel(d->irq, avic_base + AVIC_INTDISNUM);
}
/* Enable interrupt number "irq" in the AVIC */
static void mxc_unmask_irq(unsigned int irq)
static void mxc_unmask_irq(struct irq_data *d)
{
__raw_writel(irq, avic_base + AVIC_INTENNUM);
__raw_writel(d->irq, avic_base + AVIC_INTENNUM);
}
static struct mxc_irq_chip mxc_avic_chip = {
.base = {
.ack = mxc_mask_irq,
.mask = mxc_mask_irq,
.unmask = mxc_unmask_irq,
.irq_ack = mxc_mask_irq,
.irq_mask = mxc_mask_irq,
.irq_unmask = mxc_unmask_irq,
},
#ifdef CONFIG_MXC_IRQ_PRIOR
.set_priority = avic_irq_set_priority,

30
arch/arm/plat-mxc/gpio.c
View file

@ -63,29 +63,29 @@ static void _set_gpio_irqenable(struct mxc_gpio_port *port, u32 index,
__raw_writel(l, port->base + GPIO_IMR);
}
static void gpio_ack_irq(u32 irq)
static void gpio_ack_irq(struct irq_data *d)
{
u32 gpio = irq_to_gpio(irq);
u32 gpio = irq_to_gpio(d->irq);
_clear_gpio_irqstatus(&mxc_gpio_ports[gpio / 32], gpio & 0x1f);
}
static void gpio_mask_irq(u32 irq)
static void gpio_mask_irq(struct irq_data *d)
{
u32 gpio = irq_to_gpio(irq);
u32 gpio = irq_to_gpio(d->irq);
_set_gpio_irqenable(&mxc_gpio_ports[gpio / 32], gpio & 0x1f, 0);
}
static void gpio_unmask_irq(u32 irq)
static void gpio_unmask_irq(struct irq_data *d)
{
u32 gpio = irq_to_gpio(irq);
u32 gpio = irq_to_gpio(d->irq);
_set_gpio_irqenable(&mxc_gpio_ports[gpio / 32], gpio & 0x1f, 1);
}
static int mxc_gpio_get(struct gpio_chip *chip, unsigned offset);
static int gpio_set_irq_type(u32 irq, u32 type)
static int gpio_set_irq_type(struct irq_data *d, u32 type)
{
u32 gpio = irq_to_gpio(irq);
u32 gpio = irq_to_gpio(d->irq);
struct mxc_gpio_port *port = &mxc_gpio_ports[gpio / 32];
u32 bit, val;
int edge;
@ -211,9 +211,9 @@ static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
* @param enable enable as wake-up if equal to non-zero
* @return This function returns 0 on success.
*/
static int gpio_set_wake_irq(u32 irq, u32 enable)
static int gpio_set_wake_irq(struct irq_data *d, u32 enable)
{
u32 gpio = irq_to_gpio(irq);
u32 gpio = irq_to_gpio(d->irq);
u32 gpio_idx = gpio & 0x1F;
struct mxc_gpio_port *port = &mxc_gpio_ports[gpio / 32];
@ -233,11 +233,11 @@ static int gpio_set_wake_irq(u32 irq, u32 enable)
}
static struct irq_chip gpio_irq_chip = {
.ack = gpio_ack_irq,
.mask = gpio_mask_irq,
.unmask = gpio_unmask_irq,
.set_type = gpio_set_irq_type,
.set_wake = gpio_set_wake_irq,
.irq_ack = gpio_ack_irq,
.irq_mask = gpio_mask_irq,
.irq_unmask = gpio_unmask_irq,
.irq_set_type = gpio_set_irq_type,
.irq_set_wake = gpio_set_wake_irq,
};
static void _set_gpio_direction(struct gpio_chip *chip, unsigned offset,

38
arch/arm/plat-mxc/tzic.c
View file

@ -69,50 +69,50 @@ static int tzic_set_irq_fiq(unsigned int irq, unsigned int type)
#endif
/**
* tzic_mask_irq() - Disable interrupt number "irq" in the TZIC
* tzic_mask_irq() - Disable interrupt source "d" in the TZIC
*
* @param irq interrupt source number
* @param d interrupt source
*/
static void tzic_mask_irq(unsigned int irq)
static void tzic_mask_irq(struct irq_data *d)
{
int index, off;
index = irq >> 5;
off = irq & 0x1F;
index = d->irq >> 5;
off = d->irq & 0x1F;
__raw_writel(1 << off, tzic_base + TZIC_ENCLEAR0(index));
}
/**
* tzic_unmask_irq() - Enable interrupt number "irq" in the TZIC
* tzic_unmask_irq() - Enable interrupt source "d" in the TZIC
*
* @param irq interrupt source number
* @param d interrupt source
*/
static void tzic_unmask_irq(unsigned int irq)
static void tzic_unmask_irq(struct irq_data *d)
{
int index, off;
index = irq >> 5;
off = irq & 0x1F;
index = d->irq >> 5;
off = d->irq & 0x1F;
__raw_writel(1 << off, tzic_base + TZIC_ENSET0(index));
}
static unsigned int wakeup_intr[4];
/**
* tzic_set_wake_irq() - Set interrupt number "irq" in the TZIC as a wake-up source.
* tzic_set_wake_irq() - Set interrupt source "d" in the TZIC as a wake-up source.
*
* @param irq interrupt source number
* @param d interrupt source
* @param enable enable as wake-up if equal to non-zero
* disble as wake-up if equal to zero
*
* @return This function returns 0 on success.
*/
static int tzic_set_wake_irq(unsigned int irq, unsigned int enable)
static int tzic_set_wake_irq(struct irq_data *d, unsigned int enable)
{
unsigned int index, off;
index = irq >> 5;
off = irq & 0x1F;
index = d->irq >> 5;
off = d->irq & 0x1F;
if (index > 3)
return -EINVAL;
@ -128,10 +128,10 @@ static int tzic_set_wake_irq(unsigned int irq, unsigned int enable)
static struct mxc_irq_chip mxc_tzic_chip = {
.base = {
.name = "MXC_TZIC",
.ack = tzic_mask_irq,
.mask = tzic_mask_irq,
.unmask = tzic_unmask_irq,
.set_wake = tzic_set_wake_irq,
.irq_ack = tzic_mask_irq,
.irq_mask = tzic_mask_irq,
.irq_unmask = tzic_unmask_irq,
.irq_set_wake = tzic_set_wake_irq,
},
#ifdef CONFIG_FIQ
.set_irq_fiq = tzic_set_irq_fiq,