intel_scu_ipc: Remove Moorestown support
All the production devices use the PC compatible version of this device so don't use the SCU interfaces or the SCU firmware interfaces. Delete lots of code and conditional paths Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Matthew Garrett <mjg@redhat.com>
This commit is contained in:
Alan Cox
Matthew Garrett
parent
dc2cbb3b44
commit
4d6446628a
2 changed files with 29 additions and 209 deletions
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@ -174,55 +174,34 @@ static int pwr_reg_rdwr(u16 *addr, u8 *data, u32 count, u32 op, u32 id)
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return -ENODEV;
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}
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if (platform != MRST_CPU_CHIP_PENWELL) {
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bytes = 0;
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d = 0;
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for (i = 0; i < count; i++) {
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cbuf[bytes++] = addr[i];
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cbuf[bytes++] = addr[i] >> 8;
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if (id != IPC_CMD_PCNTRL_R)
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cbuf[bytes++] = data[d++];
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if (id == IPC_CMD_PCNTRL_M)
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cbuf[bytes++] = data[d++];
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}
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for (i = 0; i < bytes; i += 4)
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ipc_data_writel(wbuf[i/4], i);
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ipc_command(bytes << 16 | id << 12 | 0 << 8 | op);
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} else {
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for (nc = 0; nc < count; nc++, offset += 2) {
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cbuf[offset] = addr[nc];
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cbuf[offset + 1] = addr[nc] >> 8;
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}
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for (nc = 0; nc < count; nc++, offset += 2) {
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cbuf[offset] = addr[nc];
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cbuf[offset + 1] = addr[nc] >> 8;
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}
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if (id == IPC_CMD_PCNTRL_R) {
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for (nc = 0, offset = 0; nc < count; nc++, offset += 4)
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ipc_data_writel(wbuf[nc], offset);
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ipc_command((count*2) << 16 | id << 12 | 0 << 8 | op);
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} else if (id == IPC_CMD_PCNTRL_W) {
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for (nc = 0; nc < count; nc++, offset += 1)
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cbuf[offset] = data[nc];
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for (nc = 0, offset = 0; nc < count; nc++, offset += 4)
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ipc_data_writel(wbuf[nc], offset);
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ipc_command((count*3) << 16 | id << 12 | 0 << 8 | op);
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} else if (id == IPC_CMD_PCNTRL_M) {
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cbuf[offset] = data[0];
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cbuf[offset + 1] = data[1];
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ipc_data_writel(wbuf[0], 0); /* Write wbuff */
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ipc_command(4 << 16 | id << 12 | 0 << 8 | op);
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}
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if (id == IPC_CMD_PCNTRL_R) {
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for (nc = 0, offset = 0; nc < count; nc++, offset += 4)
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ipc_data_writel(wbuf[nc], offset);
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ipc_command((count*2) << 16 | id << 12 | 0 << 8 | op);
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} else if (id == IPC_CMD_PCNTRL_W) {
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for (nc = 0; nc < count; nc++, offset += 1)
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cbuf[offset] = data[nc];
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for (nc = 0, offset = 0; nc < count; nc++, offset += 4)
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ipc_data_writel(wbuf[nc], offset);
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ipc_command((count*3) << 16 | id << 12 | 0 << 8 | op);
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} else if (id == IPC_CMD_PCNTRL_M) {
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cbuf[offset] = data[0];
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cbuf[offset + 1] = data[1];
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ipc_data_writel(wbuf[0], 0); /* Write wbuff */
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ipc_command(4 << 16 | id << 12 | 0 << 8 | op);
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}
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err = busy_loop();
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if (id == IPC_CMD_PCNTRL_R) { /* Read rbuf */
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/* Workaround: values are read as 0 without memcpy_fromio */
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memcpy_fromio(cbuf, ipcdev.ipc_base + 0x90, 16);
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if (platform != MRST_CPU_CHIP_PENWELL) {
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for (nc = 0, offset = 2; nc < count; nc++, offset += 3)
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data[nc] = ipc_data_readb(offset);
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} else {
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for (nc = 0; nc < count; nc++)
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data[nc] = ipc_data_readb(nc);
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}
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for (nc = 0; nc < count; nc++)
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data[nc] = ipc_data_readb(nc);
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}
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mutex_unlock(&ipclock);
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return err;
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@ -503,148 +482,6 @@ int intel_scu_ipc_i2c_cntrl(u32 addr, u32 *data)
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}
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EXPORT_SYMBOL(intel_scu_ipc_i2c_cntrl);
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#define IPC_FW_LOAD_ADDR 0xFFFC0000 /* Storage location for FW image */
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#define IPC_FW_UPDATE_MBOX_ADDR 0xFFFFDFF4 /* Mailbox between ipc and scu */
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#define IPC_MAX_FW_SIZE 262144 /* 256K storage size for loading the FW image */
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#define IPC_FW_MIP_HEADER_SIZE 2048 /* Firmware MIP header size */
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/* IPC inform SCU to get ready for update process */
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#define IPC_CMD_FW_UPDATE_READY 0x10FE
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/* IPC inform SCU to go for update process */
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#define IPC_CMD_FW_UPDATE_GO 0x20FE
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/* Status code for fw update */
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#define IPC_FW_UPDATE_SUCCESS 0x444f4e45 /* Status code 'DONE' */
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#define IPC_FW_UPDATE_BADN 0x4241444E /* Status code 'BADN' */
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#define IPC_FW_TXHIGH 0x54784849 /* Status code 'IPC_FW_TXHIGH' */
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#define IPC_FW_TXLOW 0x54784c4f /* Status code 'IPC_FW_TXLOW' */
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struct fw_update_mailbox {
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u32 status;
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u32 scu_flag;
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u32 driver_flag;
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};
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/**
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* intel_scu_ipc_fw_update - Firmware update utility
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* @buffer: firmware buffer
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* @length: size of firmware buffer
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*
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* This function provides an interface to load the firmware into
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* the SCU. Returns 0 on success or -1 on failure
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*/
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int intel_scu_ipc_fw_update(u8 *buffer, u32 length)
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{
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void __iomem *fw_update_base;
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struct fw_update_mailbox __iomem *mailbox = NULL;
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int retry_cnt = 0;
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u32 status;
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mutex_lock(&ipclock);
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fw_update_base = ioremap_nocache(IPC_FW_LOAD_ADDR, (128*1024));
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if (fw_update_base == NULL) {
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mutex_unlock(&ipclock);
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return -ENOMEM;
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}
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mailbox = ioremap_nocache(IPC_FW_UPDATE_MBOX_ADDR,
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sizeof(struct fw_update_mailbox));
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if (mailbox == NULL) {
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iounmap(fw_update_base);
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mutex_unlock(&ipclock);
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return -ENOMEM;
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}
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ipc_command(IPC_CMD_FW_UPDATE_READY);
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/* Intitialize mailbox */
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writel(0, &mailbox->status);
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writel(0, &mailbox->scu_flag);
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writel(0, &mailbox->driver_flag);
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/* Driver copies the 2KB MIP header to SRAM at 0xFFFC0000*/
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memcpy_toio(fw_update_base, buffer, 0x800);
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/* Driver sends "FW Update" IPC command (CMD_ID 0xFE; MSG_ID 0x02).
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* Upon receiving this command, SCU will write the 2K MIP header
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* from 0xFFFC0000 into NAND.
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* SCU will write a status code into the Mailbox, and then set scu_flag.
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*/
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ipc_command(IPC_CMD_FW_UPDATE_GO);
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/*Driver stalls until scu_flag is set */
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while (readl(&mailbox->scu_flag) != 1) {
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rmb();
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mdelay(1);
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}
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/* Driver checks Mailbox status.
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* If the status is 'BADN', then abort (bad NAND).
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* If the status is 'IPC_FW_TXLOW', then continue.
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*/
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while (readl(&mailbox->status) != IPC_FW_TXLOW) {
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rmb();
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mdelay(10);
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}
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mdelay(10);
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update_retry:
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if (retry_cnt > 5)
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goto update_end;
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if (readl(&mailbox->status) != IPC_FW_TXLOW)
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goto update_end;
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buffer = buffer + 0x800;
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memcpy_toio(fw_update_base, buffer, 0x20000);
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writel(1, &mailbox->driver_flag);
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while (readl(&mailbox->scu_flag) == 1) {
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rmb();
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mdelay(1);
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}
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/* check for 'BADN' */
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if (readl(&mailbox->status) == IPC_FW_UPDATE_BADN)
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goto update_end;
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while (readl(&mailbox->status) != IPC_FW_TXHIGH) {
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rmb();
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mdelay(10);
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}
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mdelay(10);
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if (readl(&mailbox->status) != IPC_FW_TXHIGH)
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goto update_end;
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buffer = buffer + 0x20000;
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memcpy_toio(fw_update_base, buffer, 0x20000);
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writel(0, &mailbox->driver_flag);
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while (mailbox->scu_flag == 0) {
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rmb();
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mdelay(1);
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}
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/* check for 'BADN' */
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if (readl(&mailbox->status) == IPC_FW_UPDATE_BADN)
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goto update_end;
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if (readl(&mailbox->status) == IPC_FW_TXLOW) {
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++retry_cnt;
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goto update_retry;
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}
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update_end:
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status = readl(&mailbox->status);
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iounmap(fw_update_base);
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iounmap(mailbox);
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mutex_unlock(&ipclock);
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if (status == IPC_FW_UPDATE_SUCCESS)
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return 0;
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return -EIO;
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}
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EXPORT_SYMBOL(intel_scu_ipc_fw_update);
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/*
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* Interrupt handler gets called when ioc bit of IPC_COMMAND_REG set to 1
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* When ioc bit is set to 1, caller api must wait for interrupt handler called
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@ -727,7 +564,6 @@ static void ipc_remove(struct pci_dev *pdev)
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}
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static DEFINE_PCI_DEVICE_TABLE(pci_ids) = {
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{PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080e)},
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{PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x082a)},
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{ 0,}
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};
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@ -26,13 +26,10 @@
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static int major;
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#define MAX_FW_SIZE 264192
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/* ioctl commnds */
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#define INTE_SCU_IPC_REGISTER_READ 0
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#define INTE_SCU_IPC_REGISTER_WRITE 1
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#define INTE_SCU_IPC_REGISTER_UPDATE 2
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#define INTE_SCU_IPC_FW_UPDATE 0xA2
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struct scu_ipc_data {
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u32 count; /* No. of registers */
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@ -88,27 +85,14 @@ static long scu_ipc_ioctl(struct file *fp, unsigned int cmd,
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if (!capable(CAP_SYS_RAWIO))
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return -EPERM;
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if (cmd == INTE_SCU_IPC_FW_UPDATE) {
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u8 *fwbuf = kmalloc(MAX_FW_SIZE, GFP_KERNEL);
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if (fwbuf == NULL)
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return -ENOMEM;
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if (copy_from_user(fwbuf, (u8 *)arg, MAX_FW_SIZE)) {
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kfree(fwbuf);
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return -EFAULT;
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}
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ret = intel_scu_ipc_fw_update(fwbuf, MAX_FW_SIZE);
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kfree(fwbuf);
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return ret;
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} else {
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if (copy_from_user(&data, argp, sizeof(struct scu_ipc_data)))
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return -EFAULT;
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ret = scu_reg_access(cmd, &data);
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if (ret < 0)
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return ret;
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if (copy_to_user(argp, &data, sizeof(struct scu_ipc_data)))
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return -EFAULT;
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return 0;
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}
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if (copy_from_user(&data, argp, sizeof(struct scu_ipc_data)))
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return -EFAULT;
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ret = scu_reg_access(cmd, &data);
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if (ret < 0)
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return ret;
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if (copy_to_user(argp, &data, sizeof(struct scu_ipc_data)))
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return -EFAULT;
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return 0;
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}
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static const struct file_operations scu_ipc_fops = {
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