[POWERPC] Fix interrupts on 8540 ADS board
* Fixed 8540 ADS support for the new irq layer * Fixed 8540 ADS support for mapping PCI interrupts * Updated 8540 ADS to use device tree for interrupt assignment and sense values Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Andy Fleming
Paul Mackerras
parent
9e8a9bc2d2
commit
4c86cd9c59
1 changed files with 51 additions and 103 deletions
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@ -37,79 +37,7 @@ unsigned long isa_io_base = 0;
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unsigned long isa_mem_base = 0;
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#endif
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/*
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* Internal interrupts are all Level Sensitive, and Positive Polarity
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*
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* Note: Likely, this table and the following function should be
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* obtained and derived from the OF Device Tree.
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*/
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static u_char mpc85xx_ads_openpic_initsenses[] __initdata = {
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MPC85XX_INTERNAL_IRQ_SENSES,
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0x0, /* External 0: */
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#if defined(CONFIG_PCI)
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext 1: PCI slot 0 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext 2: PCI slot 1 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext 3: PCI slot 2 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext 4: PCI slot 3 */
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#else
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0x0, /* External 1: */
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0x0, /* External 2: */
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0x0, /* External 3: */
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0x0, /* External 4: */
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#endif
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 5: PHY */
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0x0, /* External 6: */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 7: PHY */
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0x0, /* External 8: */
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0x0, /* External 9: */
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0x0, /* External 10: */
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0x0, /* External 11: */
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};
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#ifdef CONFIG_PCI
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/*
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* interrupt routing
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*/
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int
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mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
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{
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static char pci_irq_table[][4] =
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/*
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* This is little evil, but works around the fact
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* that revA boards have IDSEL starting at 18
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* and others boards (older) start at 12
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*
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* PCI IDSEL/INTPIN->INTLINE
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* A B C D
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*/
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{
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{PIRQA, PIRQB, PIRQC, PIRQD}, /* IDSEL 2 */
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{PIRQD, PIRQA, PIRQB, PIRQC},
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{PIRQC, PIRQD, PIRQA, PIRQB},
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{PIRQB, PIRQC, PIRQD, PIRQA}, /* IDSEL 5 */
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{0, 0, 0, 0}, /* -- */
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{0, 0, 0, 0}, /* -- */
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{0, 0, 0, 0}, /* -- */
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{0, 0, 0, 0}, /* -- */
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{0, 0, 0, 0}, /* -- */
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{0, 0, 0, 0}, /* -- */
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{PIRQA, PIRQB, PIRQC, PIRQD}, /* IDSEL 12 */
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{PIRQD, PIRQA, PIRQB, PIRQC},
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{PIRQC, PIRQD, PIRQA, PIRQB},
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{PIRQB, PIRQC, PIRQD, PIRQA}, /* IDSEL 15 */
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{0, 0, 0, 0}, /* -- */
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{0, 0, 0, 0}, /* -- */
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{PIRQA, PIRQB, PIRQC, PIRQD}, /* IDSEL 18 */
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{PIRQD, PIRQA, PIRQB, PIRQC},
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{PIRQC, PIRQD, PIRQA, PIRQB},
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{PIRQB, PIRQC, PIRQD, PIRQA}, /* IDSEL 21 */
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};
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const long min_idsel = 2, max_idsel = 21, irqs_per_slot = 4;
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return PCI_IRQ_TABLE_LOOKUP;
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}
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int
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mpc85xx_exclude_device(u_char bus, u_char devfn)
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{
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@ -119,44 +47,63 @@ mpc85xx_exclude_device(u_char bus, u_char devfn)
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return PCIBIOS_SUCCESSFUL;
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}
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void __init
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mpc85xx_pcibios_fixup(void)
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{
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struct pci_dev *dev = NULL;
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for_each_pci_dev(dev)
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pci_read_irq_line(dev);
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}
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#endif /* CONFIG_PCI */
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void __init mpc85xx_ads_pic_init(void)
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{
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struct mpic *mpic1;
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phys_addr_t OpenPIC_PAddr;
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struct mpic *mpic;
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struct resource r;
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struct device_node *np = NULL;
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/* Determine the Physical Address of the OpenPIC regs */
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OpenPIC_PAddr = get_immrbase() + MPC85xx_OPENPIC_OFFSET;
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np = of_find_node_by_type(np, "open-pic");
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mpic1 = mpic_alloc(OpenPIC_PAddr,
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MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
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4, MPC85xx_OPENPIC_IRQ_OFFSET, 0, 250,
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mpc85xx_ads_openpic_initsenses,
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sizeof(mpc85xx_ads_openpic_initsenses),
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" OpenPIC ");
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BUG_ON(mpic1 == NULL);
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mpic_assign_isu(mpic1, 0, OpenPIC_PAddr + 0x10200);
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mpic_assign_isu(mpic1, 1, OpenPIC_PAddr + 0x10280);
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mpic_assign_isu(mpic1, 2, OpenPIC_PAddr + 0x10300);
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mpic_assign_isu(mpic1, 3, OpenPIC_PAddr + 0x10380);
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mpic_assign_isu(mpic1, 4, OpenPIC_PAddr + 0x10400);
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mpic_assign_isu(mpic1, 5, OpenPIC_PAddr + 0x10480);
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mpic_assign_isu(mpic1, 6, OpenPIC_PAddr + 0x10500);
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mpic_assign_isu(mpic1, 7, OpenPIC_PAddr + 0x10580);
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if (np == NULL) {
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printk(KERN_ERR "Could not find open-pic node\n");
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return;
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}
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/* dummy mappings to get to 48 */
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mpic_assign_isu(mpic1, 8, OpenPIC_PAddr + 0x10600);
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mpic_assign_isu(mpic1, 9, OpenPIC_PAddr + 0x10680);
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mpic_assign_isu(mpic1, 10, OpenPIC_PAddr + 0x10700);
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mpic_assign_isu(mpic1, 11, OpenPIC_PAddr + 0x10780);
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if(of_address_to_resource(np, 0, &r)) {
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printk(KERN_ERR "Could not map mpic register space\n");
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of_node_put(np);
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return;
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}
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/* External ints */
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mpic_assign_isu(mpic1, 12, OpenPIC_PAddr + 0x10000);
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mpic_assign_isu(mpic1, 13, OpenPIC_PAddr + 0x10080);
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mpic_assign_isu(mpic1, 14, OpenPIC_PAddr + 0x10100);
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mpic_init(mpic1);
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mpic = mpic_alloc(np, r.start,
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MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
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4, 0, " OpenPIC ");
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BUG_ON(mpic == NULL);
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of_node_put(np);
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mpic_assign_isu(mpic, 0, r.start + 0x10200);
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mpic_assign_isu(mpic, 1, r.start + 0x10280);
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mpic_assign_isu(mpic, 2, r.start + 0x10300);
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mpic_assign_isu(mpic, 3, r.start + 0x10380);
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mpic_assign_isu(mpic, 4, r.start + 0x10400);
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mpic_assign_isu(mpic, 5, r.start + 0x10480);
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mpic_assign_isu(mpic, 6, r.start + 0x10500);
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mpic_assign_isu(mpic, 7, r.start + 0x10580);
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/* Unused on this platform (leave room for 8548) */
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mpic_assign_isu(mpic, 8, r.start + 0x10600);
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mpic_assign_isu(mpic, 9, r.start + 0x10680);
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mpic_assign_isu(mpic, 10, r.start + 0x10700);
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mpic_assign_isu(mpic, 11, r.start + 0x10780);
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/* External Interrupts */
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mpic_assign_isu(mpic, 12, r.start + 0x10000);
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mpic_assign_isu(mpic, 13, r.start + 0x10080);
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mpic_assign_isu(mpic, 14, r.start + 0x10100);
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mpic_init(mpic);
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}
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/*
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@ -165,7 +112,9 @@ void __init mpc85xx_ads_pic_init(void)
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static void __init mpc85xx_ads_setup_arch(void)
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{
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struct device_node *cpu;
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#ifdef CONFIG_PCI
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struct device_node *np;
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#endif
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if (ppc_md.progress)
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ppc_md.progress("mpc85xx_ads_setup_arch()", 0);
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@ -186,8 +135,7 @@ static void __init mpc85xx_ads_setup_arch(void)
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for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
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add_bridge(np);
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ppc_md.pci_swizzle = common_swizzle;
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ppc_md.pci_map_irq = mpc85xx_map_irq;
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ppc_md.pcibios_fixup = mpc85xx_pcibios_fixup;
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ppc_md.pci_exclude_device = mpc85xx_exclude_device;
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#endif
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