r8169: use correct barrier between cacheable and non-cacheable memory
r8169 needs certain writes to be visible to other CPUs or the NIC before touching the hardware, but was using smp_wmb() which is only required to order cacheable memory access. Switch to wmb() which is required to order both cacheable and non-cacheable memory. Noticed by Catalin Marinas and Paul Mackerras. Signed-off-by: David Dillow <dave@thedillows.org> Signed-off-by: David S. Miller <davem@davemloft.net>
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1 changed files with 2 additions and 2 deletions
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@ -4270,7 +4270,7 @@ static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
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tp->cur_tx += frags + 1;
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smp_wmb();
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wmb();
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RTL_W8(TxPoll, NPQ); /* set polling bit */
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@ -4621,7 +4621,7 @@ static int rtl8169_poll(struct napi_struct *napi, int budget)
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* until it does.
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*/
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tp->intr_mask = 0xffff;
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smp_wmb();
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wmb();
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RTL_W16(IntrMask, tp->intr_event);
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}
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