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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu

Browse source 
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu: (21 commits)
  m68knommu: convert to using tracehook_report_syscall_*
  m68knommu: some boards use fixed phy for FEC ethernet
  m68knommu: support the external GPIO based interrupts of the 5272
  m68knommu: mask of vector bits in exception word properly
  m68knommu: change to new flag variables
  m68knommu: Fix MCFUART_TXFIFOSIZE for m548x.
  m68knommu: add basic mmu-less m548x support
  m68knommu: .gitignore vmlinux.lds
  m68knommu: stop using __do_IRQ
  m68knommu: rename PT_OFF_VECTOR to PT_OFF_FORMATVEC.
  m68knommu: add support for Coldfire 547x/548x interrupt controller
  m68k{nommu}: Remove unused DEFINE's from asm-offsets.c
  m68knommu: whitespace cleanup in 68328/entry.S
  m68knommu: Document supported chips in intc-2.c and intc-simr.c.
  m68knommu: fix strace support for 68328/68360
  m68knommu: fix default starting date
  arch/m68knommu: Removing dead 68328_SERIAL_UART2 config option
  arch/m68knommu: Removing dead RAM_{16,32}_MB config option
  arch/m68knommu: Removing dead M68KFPU_EMU config option
  arch/m68knommu: Removing dead RELOCATE config option
  ...
This commit is contained in:
Linus Torvalds 2010-10-25 07:44:27 -07:00
commit 4b37ba90f4
47 changed files with 708 additions and 216 deletions
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2
arch/m68k/include/asm/cacheflush_no.h
View file

@ -29,7 +29,7 @@
static inline void __flush_cache_all(void)
{
#ifdef CONFIG_M5407
#if defined(CONFIG_M5407) || defined(CONFIG_M548x)
/*
* Use cpushl to push and invalidate all cache lines.
* Gas doesn't seem to know how to generate the ColdFire

4
arch/m68k/include/asm/coldfire.h
View file

@ -32,7 +32,9 @@
*/
#define MCF_MBAR 0x10000000
#define MCF_MBAR2 0x80000000
#if defined(CONFIG_M520x)
#if defined(CONFIG_M548x)
#define MCF_IPSBAR MCF_MBAR
#elif defined(CONFIG_M520x)
#define MCF_IPSBAR 0xFC000000
#else
#define MCF_IPSBAR 0x40000000

7
arch/m68k/include/asm/gpio.h
View file

@ -36,7 +36,8 @@
*/
#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x)
defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
defined(CONFIG_M532x) || defined(CONFIG_M548x)
/* These parts have GPIO organized by 8 bit ports */
@ -136,6 +137,8 @@ static inline u32 __mcf_gpio_ppdr(unsigned gpio)
#endif
else
return MCFGPIO_PPDR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
#else
return 0;
#endif
}
@ -173,6 +176,8 @@ static inline u32 __mcf_gpio_podr(unsigned gpio)
#endif
else
return MCFGPIO_PODR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
#else
return 0;
#endif
}

88
arch/m68k/include/asm/m548xgpt.h Normal file
View file

@ -0,0 +1,88 @@
/*
* File: m548xgpt.h
* Purpose: Register and bit definitions for the MCF548X
*
* Notes:
*
*/
#ifndef m548xgpt_h
#define m548xgpt_h
/*********************************************************************
*
* General Purpose Timers (GPT)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_GPT_GMS0 0x000800
#define MCF_GPT_GCIR0 0x000804
#define MCF_GPT_GPWM0 0x000808
#define MCF_GPT_GSR0 0x00080C
#define MCF_GPT_GMS1 0x000810
#define MCF_GPT_GCIR1 0x000814
#define MCF_GPT_GPWM1 0x000818
#define MCF_GPT_GSR1 0x00081C
#define MCF_GPT_GMS2 0x000820
#define MCF_GPT_GCIR2 0x000824
#define MCF_GPT_GPWM2 0x000828
#define MCF_GPT_GSR2 0x00082C
#define MCF_GPT_GMS3 0x000830
#define MCF_GPT_GCIR3 0x000834
#define MCF_GPT_GPWM3 0x000838
#define MCF_GPT_GSR3 0x00083C
#define MCF_GPT_GMS(x) (0x000800+((x)*0x010))
#define MCF_GPT_GCIR(x) (0x000804+((x)*0x010))
#define MCF_GPT_GPWM(x) (0x000808+((x)*0x010))
#define MCF_GPT_GSR(x) (0x00080C+((x)*0x010))
/* Bit definitions and macros for MCF_GPT_GMS */
#define MCF_GPT_GMS_TMS(x) (((x)&0x00000007)<<0)
#define MCF_GPT_GMS_GPIO(x) (((x)&0x00000003)<<4)
#define MCF_GPT_GMS_IEN (0x00000100)
#define MCF_GPT_GMS_OD (0x00000200)
#define MCF_GPT_GMS_SC (0x00000400)
#define MCF_GPT_GMS_CE (0x00001000)
#define MCF_GPT_GMS_WDEN (0x00008000)
#define MCF_GPT_GMS_ICT(x) (((x)&0x00000003)<<16)
#define MCF_GPT_GMS_OCT(x) (((x)&0x00000003)<<20)
#define MCF_GPT_GMS_OCPW(x) (((x)&0x000000FF)<<24)
#define MCF_GPT_GMS_OCT_FRCLOW (0x00000000)
#define MCF_GPT_GMS_OCT_PULSEHI (0x00100000)
#define MCF_GPT_GMS_OCT_PULSELO (0x00200000)
#define MCF_GPT_GMS_OCT_TOGGLE (0x00300000)
#define MCF_GPT_GMS_ICT_ANY (0x00000000)
#define MCF_GPT_GMS_ICT_RISE (0x00010000)
#define MCF_GPT_GMS_ICT_FALL (0x00020000)
#define MCF_GPT_GMS_ICT_PULSE (0x00030000)
#define MCF_GPT_GMS_GPIO_INPUT (0x00000000)
#define MCF_GPT_GMS_GPIO_OUTLO (0x00000020)
#define MCF_GPT_GMS_GPIO_OUTHI (0x00000030)
#define MCF_GPT_GMS_TMS_DISABLE (0x00000000)
#define MCF_GPT_GMS_TMS_INCAPT (0x00000001)
#define MCF_GPT_GMS_TMS_OUTCAPT (0x00000002)
#define MCF_GPT_GMS_TMS_PWM (0x00000003)
#define MCF_GPT_GMS_TMS_GPIO (0x00000004)
/* Bit definitions and macros for MCF_GPT_GCIR */
#define MCF_GPT_GCIR_CNT(x) (((x)&0x0000FFFF)<<0)
#define MCF_GPT_GCIR_PRE(x) (((x)&0x0000FFFF)<<16)
/* Bit definitions and macros for MCF_GPT_GPWM */
#define MCF_GPT_GPWM_LOAD (0x00000001)
#define MCF_GPT_GPWM_PWMOP (0x00000100)
#define MCF_GPT_GPWM_WIDTH(x) (((x)&0x0000FFFF)<<16)
/* Bit definitions and macros for MCF_GPT_GSR */
#define MCF_GPT_GSR_CAPT (0x00000001)
#define MCF_GPT_GSR_COMP (0x00000002)
#define MCF_GPT_GSR_PWMP (0x00000004)
#define MCF_GPT_GSR_TEXP (0x00000008)
#define MCF_GPT_GSR_PIN (0x00000100)
#define MCF_GPT_GSR_OVF(x) (((x)&0x00000007)<<12)
#define MCF_GPT_GSR_CAPTURE(x) (((x)&0x0000FFFF)<<16)
/********************************************************************/
#endif /* m548xgpt_h */

55
arch/m68k/include/asm/m548xsim.h Normal file
View file

@ -0,0 +1,55 @@
/*
* m548xsim.h -- ColdFire 547x/548x System Integration Unit support.
*/
#ifndef m548xsim_h
#define m548xsim_h
#define MCFINT_VECBASE 64
/*
* Interrupt Controller Registers
*/
#define MCFICM_INTC0 0x0700 /* Base for Interrupt Ctrl 0 */
#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
#define MCFINTC_IRLR 0x18 /* */
#define MCFINTC_IACKL 0x19 /* */
#define MCFINTC_ICR0 0x40 /* Base ICR register */
/*
* Define system peripheral IRQ usage.
*/
#define MCF_IRQ_TIMER (64 + 54) /* Slice Timer 0 */
#define MCF_IRQ_PROFILER (64 + 53) /* Slice Timer 1 */
/*
* Generic GPIO support
*/
#define MCFGPIO_PIN_MAX 0 /* I am too lazy to count */
#define MCFGPIO_IRQ_MAX -1
#define MCFGPIO_IRQ_VECBASE -1
/*
* Some PSC related definitions
*/
#define MCF_PAR_PSC(x) (0x000A4F-((x)&0x3))
#define MCF_PAR_SDA (0x0008)
#define MCF_PAR_SCL (0x0004)
#define MCF_PAR_PSC_TXD (0x04)
#define MCF_PAR_PSC_RXD (0x08)
#define MCF_PAR_PSC_RTS(x) (((x)&0x03)<<4)
#define MCF_PAR_PSC_CTS(x) (((x)&0x03)<<6)
#define MCF_PAR_PSC_CTS_GPIO (0x00)
#define MCF_PAR_PSC_CTS_BCLK (0x80)
#define MCF_PAR_PSC_CTS_CTS (0xC0)
#define MCF_PAR_PSC_RTS_GPIO (0x00)
#define MCF_PAR_PSC_RTS_FSYNC (0x20)
#define MCF_PAR_PSC_RTS_RTS (0x30)
#define MCF_PAR_PSC_CANRX (0x40)
#endif /* m548xsim_h */

2
arch/m68k/include/asm/mcfcache.h
View file

@ -107,7 +107,7 @@
.endm
#endif /* CONFIG_M532x */
#if defined(CONFIG_M5407)
#if defined(CONFIG_M5407) || defined(CONFIG_M548x)
/*
* Version 4 cores have a true harvard style separate instruction
* and data cache. Invalidate and enable cache, also enable write

2
arch/m68k/include/asm/mcfsim.h
View file

@ -41,6 +41,8 @@
#elif defined(CONFIG_M5407)
#include <asm/m5407sim.h>
#include <asm/mcfintc.h>
#elif defined(CONFIG_M548x)
#include <asm/m548xsim.h>
#endif
/****************************************************************************/

44
arch/m68k/include/asm/mcfslt.h Normal file
View file

@ -0,0 +1,44 @@
/****************************************************************************/
/*
* mcfslt.h -- ColdFire internal Slice (SLT) timer support defines.
*
* (C) Copyright 2004, Greg Ungerer (gerg@snapgear.com)
* (C) Copyright 2009, Philippe De Muyter (phdm@macqel.be)
*/
/****************************************************************************/
#ifndef mcfslt_h
#define mcfslt_h
/****************************************************************************/
/*
* Get address specific defines for the 547x.
*/
#define MCFSLT_TIMER0 0x900 /* Base address of TIMER0 */
#define MCFSLT_TIMER1 0x910 /* Base address of TIMER1 */
/*
* Define the SLT timer register set addresses.
*/
#define MCFSLT_STCNT 0x00 /* Terminal count */
#define MCFSLT_SCR 0x04 /* Control */
#define MCFSLT_SCNT 0x08 /* Current count */
#define MCFSLT_SSR 0x0C /* Status */
/*
* Bit definitions for the SCR control register.
*/
#define MCFSLT_SCR_RUN 0x04000000 /* Run mode (continuous) */
#define MCFSLT_SCR_IEN 0x02000000 /* Interrupt enable */
#define MCFSLT_SCR_TEN 0x01000000 /* Timer enable */
/*
* Bit definitions for the SSR status register.
*/
#define MCFSLT_SSR_BE 0x02000000 /* Bus error condition */
#define MCFSLT_SSR_TE 0x01000000 /* Timeout condition */
/****************************************************************************/
#endif /* mcfslt_h */

9
arch/m68k/include/asm/mcfuart.h
View file

@ -47,6 +47,11 @@
#define MCFUART_BASE1 0xfc060000 /* Base address of UART1 */
#define MCFUART_BASE2 0xfc064000 /* Base address of UART2 */
#define MCFUART_BASE3 0xfc068000 /* Base address of UART3 */
#elif defined(CONFIG_M548x)
#define MCFUART_BASE1 0x8600 /* on M548x */
#define MCFUART_BASE2 0x8700 /* on M548x */
#define MCFUART_BASE3 0x8800 /* on M548x */
#define MCFUART_BASE4 0x8900 /* on M548x */
#endif
@ -212,7 +217,9 @@ struct mcf_platform_uart {
#define MCFUART_URF_RXS 0xc0 /* Receiver status */
#endif
#if defined(CONFIG_M5272)
#if defined(CONFIG_M548x)
#define MCFUART_TXFIFOSIZE 512
#elif defined(CONFIG_M5272)
#define MCFUART_TXFIFOSIZE 25
#else
#define MCFUART_TXFIFOSIZE 1

12
arch/m68k/kernel/asm-offsets.c
View file

@ -22,13 +22,9 @@
int main(void)
{
/* offsets into the task struct */
DEFINE(TASK_STATE, offsetof(struct task_struct, state));
DEFINE(TASK_FLAGS, offsetof(struct task_struct, flags));
DEFINE(TASK_PTRACE, offsetof(struct task_struct, ptrace));
DEFINE(TASK_THREAD, offsetof(struct task_struct, thread));
DEFINE(TASK_INFO, offsetof(struct task_struct, thread.info));
DEFINE(TASK_MM, offsetof(struct task_struct, mm));
DEFINE(TASK_ACTIVE_MM, offsetof(struct task_struct, active_mm));
#ifdef CONFIG_MMU
DEFINE(TASK_TINFO, offsetof(struct task_struct, thread.info));
#endif
@ -64,14 +60,6 @@ int main(void)
/* bitfields are a bit difficult */
DEFINE(PT_OFF_FORMATVEC, offsetof(struct pt_regs, pc) + 4);
/* offsets into the irq_handler struct */
DEFINE(IRQ_HANDLER, offsetof(struct irq_node, handler));
DEFINE(IRQ_DEVID, offsetof(struct irq_node, dev_id));
DEFINE(IRQ_NEXT, offsetof(struct irq_node, next));
/* offsets into the kernel_stat struct */
DEFINE(STAT_IRQ, offsetof(struct kernel_stat, irqs));
/* offsets into the irq_cpustat_t struct */
DEFINE(CPUSTAT_SOFTIRQ_PENDING, offsetof(irq_cpustat_t, __softirq_pending));

11
arch/m68knommu/Kconfig
View file

@ -59,6 +59,10 @@ config GENERIC_HARDIRQS
bool
default y
config GENERIC_HARDIRQS_NO__DO_IRQ
bool
default y
config GENERIC_CALIBRATE_DELAY
bool
default y
@ -171,6 +175,11 @@ config M5407
help
Motorola ColdFire 5407 processor support.
config M548x
bool "MCF548x"
help
Freescale ColdFire 5480/5481/5482/5483/5484/5485 processor support.
endchoice
config M527x
@ -181,7 +190,7 @@ config M527x
config COLDFIRE
bool
depends on (M5206 || M5206e || M520x || M523x || M5249 || M527x || M5272 || M528x || M5307 || M532x || M5407)
depends on (M5206 || M5206e || M520x || M523x || M5249 || M527x || M5272 || M528x || M5307 || M532x || M5407 || M548x)
select GENERIC_GPIO
select ARCH_REQUIRE_GPIOLIB
default y

3
arch/m68knommu/Makefile
View file

@ -25,6 +25,7 @@ platform-$(CONFIG_M528x) := 528x
platform-$(CONFIG_M5307) := 5307
platform-$(CONFIG_M532x) := 532x
platform-$(CONFIG_M5407) := 5407
platform-$(CONFIG_M548x) := 548x
PLATFORM := $(platform-y)
board-$(CONFIG_PILOT) := pilot
@ -73,6 +74,7 @@ cpuclass-$(CONFIG_M528x) := coldfire
cpuclass-$(CONFIG_M5307) := coldfire
cpuclass-$(CONFIG_M532x) := coldfire
cpuclass-$(CONFIG_M5407) := coldfire
cpuclass-$(CONFIG_M548x) := coldfire
cpuclass-$(CONFIG_M68328) := 68328
cpuclass-$(CONFIG_M68EZ328) := 68328
cpuclass-$(CONFIG_M68VZ328) := 68328
@ -100,6 +102,7 @@ cflags-$(CONFIG_M528x) := $(call cc-option,-m528x,-m5307)
cflags-$(CONFIG_M5307) := $(call cc-option,-m5307,-m5200)
cflags-$(CONFIG_M532x) := $(call cc-option,-mcpu=532x,-m5307)
cflags-$(CONFIG_M5407) := $(call cc-option,-m5407,-m5200)
cflags-$(CONFIG_M548x) := $(call cc-option,-m5407,-m5200)
cflags-$(CONFIG_M68328) := -m68000
cflags-$(CONFIG_M68EZ328) := -m68000
cflags-$(CONFIG_M68VZ328) := -m68000

1
arch/m68knommu/kernel/.gitignore vendored Normal file
View file

@ -0,0 +1 @@
vmlinux.lds

11
arch/m68knommu/kernel/asm-offsets.c
View file

@ -21,14 +21,8 @@
int main(void)
{
/* offsets into the task struct */
DEFINE(TASK_STATE, offsetof(struct task_struct, state));
DEFINE(TASK_FLAGS, offsetof(struct task_struct, flags));
DEFINE(TASK_PTRACE, offsetof(struct task_struct, ptrace));
DEFINE(TASK_BLOCKED, offsetof(struct task_struct, blocked));
DEFINE(TASK_THREAD, offsetof(struct task_struct, thread));
DEFINE(TASK_THREAD_INFO, offsetof(struct task_struct, stack));
DEFINE(TASK_MM, offsetof(struct task_struct, mm));
DEFINE(TASK_ACTIVE_MM, offsetof(struct task_struct, active_mm));
/* offsets into the irq_cpustat_t struct */
DEFINE(CPUSTAT_SOFTIRQ_PENDING, offsetof(irq_cpustat_t, __softirq_pending));
@ -63,7 +57,7 @@ int main(void)
DEFINE(PT_OFF_FORMATVEC, offsetof(struct pt_regs, sr) - 2);
#else
/* bitfields are a bit difficult */
DEFINE(PT_OFF_VECTOR, offsetof(struct pt_regs, pc) + 4);
DEFINE(PT_OFF_FORMATVEC, offsetof(struct pt_regs, pc) + 4);
#endif
/* signal defines */
@ -75,11 +69,8 @@ int main(void)
DEFINE(PT_PTRACED, PT_PTRACED);
/* Offsets in thread_info structure */
DEFINE(TI_TASK, offsetof(struct thread_info, task));
DEFINE(TI_EXECDOMAIN, offsetof(struct thread_info, exec_domain));
DEFINE(TI_FLAGS, offsetof(struct thread_info, flags));
DEFINE(TI_PREEMPTCOUNT, offsetof(struct thread_info, preempt_count));
DEFINE(TI_CPU, offsetof(struct thread_info, cpu));
return 0;
}

47
arch/m68knommu/kernel/ptrace.c
View file

@ -18,6 +18,7 @@
#include <linux/ptrace.h>
#include <linux/user.h>
#include <linux/signal.h>
#include <linux/tracehook.h>
#include <asm/uaccess.h>
#include <asm/page.h>
@ -134,14 +135,6 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
tmp >>= 16;
} else if (addr >= 21 && addr < 49) {
tmp = child->thread.fp[addr - 21];
#ifdef CONFIG_M68KFPU_EMU
/* Convert internal fpu reg representation
* into long double format
*/
if (FPU_IS_EMU && (addr < 45) && !(addr % 3))
tmp = ((tmp & 0xffff0000) << 15) |
((tmp & 0x0000ffff) << 16);
#endif
} else if (addr == 49) {
tmp = child->mm->start_code;
} else if (addr == 50) {
@ -175,16 +168,6 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
}
if (addr >= 21 && addr < 48)
{
#ifdef CONFIG_M68KFPU_EMU
/* Convert long double format
* into internal fpu reg representation
*/
if (FPU_IS_EMU && (addr < 45) && !(addr % 3)) {
data = (unsigned long)data << 15;
data = (data & 0xffff0000) |
((data & 0x0000ffff) >> 1);
}
#endif
child->thread.fp[addr - 21] = data;
ret = 0;
}
@ -259,21 +242,17 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
return ret;
}
asmlinkage void syscall_trace(void)
asmlinkage int syscall_trace_enter(void)
{
if (!test_thread_flag(TIF_SYSCALL_TRACE))
return;
if (!(current->ptrace & PT_PTRACED))
return;
ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD)
? 0x80 : 0));
/*
* this isn't the same as continuing with a signal, but it will do
* for normal use. strace only continues with a signal if the
* stopping signal is not SIGTRAP. -brl
*/
if (current->exit_code) {
send_sig(current->exit_code, current, 1);
current->exit_code = 0;
}
int ret = 0;
if (test_thread_flag(TIF_SYSCALL_TRACE))
ret = tracehook_report_syscall_entry(task_pt_regs(current));
return ret;
}
asmlinkage void syscall_trace_leave(void)
{
if (test_thread_flag(TIF_SYSCALL_TRACE))
tracehook_report_syscall_exit(task_pt_regs(current), 0);
}

3
arch/m68knommu/kernel/setup.c
View file

@ -54,9 +54,6 @@ void (*mach_reset)(void);
void (*mach_halt)(void);
void (*mach_power_off)(void);
#ifdef CONFIG_M68000
#define CPU "MC68000"
#endif
#ifdef CONFIG_M68328
#define CPU "MC68328"
#endif

11
arch/m68knommu/kernel/time.c
View file

@ -60,13 +60,16 @@ static unsigned long read_rtc_mmss(void)
{
unsigned int year, mon, day, hour, min, sec;
if (mach_gettod)
if (mach_gettod) {
mach_gettod(&year, &mon, &day, &hour, &min, &sec);
else
year = mon = day = hour = min = sec = 0;
if ((year += 1900) < 1970)
year += 100;
} else {
year = 1970;
mon = day = 1;
hour = min = sec = 0;
}
return mktime(year, mon, day, hour, min, sec);
}

26
arch/m68knommu/kernel/traps.c
View file

@ -179,14 +179,16 @@ static void __show_stack(struct task_struct *task, unsigned long *stack)
void bad_super_trap(struct frame *fp)
{
int vector = (fp->ptregs.vector >> 2) & 0xff;
console_verbose();
if (fp->ptregs.vector < 4 * ARRAY_SIZE(vec_names))
if (vector < ARRAY_SIZE(vec_names))
printk (KERN_WARNING "*** %s *** FORMAT=%X\n",
vec_names[(fp->ptregs.vector) >> 2],
vec_names[vector],
fp->ptregs.format);
else
printk (KERN_WARNING "*** Exception %d *** FORMAT=%X\n",
(fp->ptregs.vector) >> 2,
vector,
fp->ptregs.format);
printk (KERN_WARNING "Current process id is %d\n", current->pid);
die_if_kernel("BAD KERNEL TRAP", &fp->ptregs, 0);
@ -195,10 +197,11 @@ void bad_super_trap(struct frame *fp)
asmlinkage void trap_c(struct frame *fp)
{
int sig;
int vector = (fp->ptregs.vector >> 2) & 0xff;
siginfo_t info;
if (fp->ptregs.sr & PS_S) {
if ((fp->ptregs.vector >> 2) == VEC_TRACE) {
if (vector == VEC_TRACE) {
/* traced a trapping instruction */
} else
bad_super_trap(fp);
@ -206,7 +209,7 @@ asmlinkage void trap_c(struct frame *fp)
}
/* send the appropriate signal to the user program */
switch ((fp->ptregs.vector) >> 2) {
switch (vector) {
case VEC_ADDRERR:
info.si_code = BUS_ADRALN;
sig = SIGBUS;
@ -360,16 +363,3 @@ void show_stack(struct task_struct *task, unsigned long *stack)
else
__show_stack(task, stack);
}
#ifdef CONFIG_M68KFPU_EMU
asmlinkage void fpemu_signal(int signal, int code, void *addr)
{
siginfo_t info;
info.si_signo = signal;
info.si_errno = 0;
info.si_code = code;
info.si_addr = addr;
force_sig_info(signal, &info, current);
}
#endif

4
arch/m68knommu/platform/5206/Makefile
View file

@ -8,8 +8,8 @@
# on the console port whenever a DBG interrupt occurs. You have to
# set up you HW breakpoints to trigger a DBG interrupt:
#
# EXTRA_CFLAGS += -DTRAP_DBG_INTERRUPT
# EXTRA_AFLAGS += -DTRAP_DBG_INTERRUPT
# ccflags-y := -DTRAP_DBG_INTERRUPT
# asflags-y := -DTRAP_DBG_INTERRUPT
#
asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1

4
arch/m68knommu/platform/5206e/Makefile
View file

@ -8,8 +8,8 @@
# on the console port whenever a DBG interrupt occurs. You have to
# set up you HW breakpoints to trigger a DBG interrupt:
#
# EXTRA_CFLAGS += -DTRAP_DBG_INTERRUPT
# EXTRA_AFLAGS += -DTRAP_DBG_INTERRUPT
# ccflags-y := -DTRAP_DBG_INTERRUPT
# asflags-y := -DTRAP_DBG_INTERRUPT
#
asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1

4
arch/m68knommu/platform/520x/Makefile
View file

@ -8,8 +8,8 @@
# on the console port whenever a DBG interrupt occurs. You have to
# set up you HW breakpoints to trigger a DBG interrupt:
#
# EXTRA_CFLAGS += -DTRAP_DBG_INTERRUPT
# EXTRA_AFLAGS += -DTRAP_DBG_INTERRUPT
# ccflags-y := -DTRAP_DBG_INTERRUPT
# asflags-y := -DTRAP_DBG_INTERRUPT
#
asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1

4
arch/m68knommu/platform/523x/Makefile
View file

@ -8,8 +8,8 @@
# on the console port whenever a DBG interrupt occurs. You have to
# set up you HW breakpoints to trigger a DBG interrupt:
#
# EXTRA_CFLAGS += -DTRAP_DBG_INTERRUPT
# EXTRA_AFLAGS += -DTRAP_DBG_INTERRUPT
# ccflags-y := -DTRAP_DBG_INTERRUPT
# asflags-y := -DTRAP_DBG_INTERRUPT
#
asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1

4
arch/m68knommu/platform/5249/Makefile
View file

@ -8,8 +8,8 @@
# on the console port whenever a DBG interrupt occurs. You have to
# set up you HW breakpoints to trigger a DBG interrupt:
#
# EXTRA_CFLAGS += -DTRAP_DBG_INTERRUPT
# EXTRA_AFLAGS += -DTRAP_DBG_INTERRUPT
# ccflags-y := -DTRAP_DBG_INTERRUPT
# asflags-y := -DTRAP_DBG_INTERRUPT
#
asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1

4
arch/m68knommu/platform/5272/Makefile
View file

@ -8,8 +8,8 @@
# on the console port whenever a DBG interrupt occurs. You have to
# set up you HW breakpoints to trigger a DBG interrupt:
#
# EXTRA_CFLAGS += -DTRAP_DBG_INTERRUPT
# EXTRA_AFLAGS += -DTRAP_DBG_INTERRUPT
# ccflags-y := -DTRAP_DBG_INTERRUPT
# asflags-y := -DTRAP_DBG_INTERRUPT
#
asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1

16
arch/m68knommu/platform/5272/config.c
View file

@ -13,6 +13,8 @@
#include <linux/param.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/phy.h>
#include <linux/phy_fixed.h>
#include <asm/machdep.h>
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
@ -148,9 +150,23 @@ void __init config_BSP(char *commandp, int size)
/***************************************************************************/
/*
* Some 5272 based boards have the FEC ethernet diectly connected to
* an ethernet switch. In this case we need to use the fixed phy type,
* and we need to declare it early in boot.
*/
static struct fixed_phy_status nettel_fixed_phy_status __initdata = {
.link = 1,
.speed = 100,
.duplex = 0,
};
/***************************************************************************/
static int __init init_BSP(void)
{
m5272_uarts_init();
fixed_phy_add(PHY_POLL, 0, &nettel_fixed_phy_status);
platform_add_devices(m5272_devices, ARRAY_SIZE(m5272_devices));
return 0;
}

60
arch/m68knommu/platform/5272/intc.c
View file

@ -12,6 +12,7 @@
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/kernel_stat.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <asm/coldfire.h>
@ -29,6 +30,10 @@
* via a set of 4 "Interrupt Controller Registers" (ICR). There is a
* loose mapping of vector number to register and internal bits, but
* a table is the easiest and quickest way to map them.
*
* Note that the external interrupts are edge triggered (unlike the
* internal interrupt sources which are level triggered). Which means
* they also need acknowledgeing via acknowledge bits.
*/
struct irqmap {
unsigned char icr;
@ -68,6 +73,11 @@ static struct irqmap intc_irqmap[MCFINT_VECMAX - MCFINT_VECBASE] = {
/*MCF_IRQ_SWTO*/ { .icr = MCFSIM_ICR4, .index = 16, .ack = 0, },
};
/*
* The act of masking the interrupt also has a side effect of 'ack'ing
* an interrupt on this irq (for the external irqs). So this mask function
* is also an ack_mask function.
*/
static void intc_irq_mask(unsigned int irq)
{
if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) {
@ -95,7 +105,9 @@ static void intc_irq_ack(unsigned int irq)
irq -= MCFINT_VECBASE;
if (intc_irqmap[irq].ack) {
u32 v;
v = 0xd << intc_irqmap[irq].index;
v = readl(MCF_MBAR + intc_irqmap[irq].icr);
v &= (0x7 << intc_irqmap[irq].index);
v |= (0x8 << intc_irqmap[irq].index);
writel(v, MCF_MBAR + intc_irqmap[irq].icr);
}
}
@ -103,21 +115,47 @@ static void intc_irq_ack(unsigned int irq)
static int intc_irq_set_type(unsigned int irq, unsigned int type)
{
/* We can set the edge type here for external interrupts */
if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) {
irq -= MCFINT_VECBASE;
if (intc_irqmap[irq].ack) {
u32 v;
v = readl(MCF_MBAR + MCFSIM_PITR);
if (type == IRQ_TYPE_EDGE_FALLING)
v &= ~(0x1 << (32 - irq));
else
v |= (0x1 << (32 - irq));
writel(v, MCF_MBAR + MCFSIM_PITR);
}
}
return 0;
}
/*
* Simple flow handler to deal with the external edge triggered interrupts.
* We need to be careful with the masking/acking due to the side effects
* of masking an interrupt.
*/
static void intc_external_irq(unsigned int irq, struct irq_desc *desc)
{
kstat_incr_irqs_this_cpu(irq, desc);
desc->status |= IRQ_INPROGRESS;
desc->chip->ack(irq);
handle_IRQ_event(irq, desc->action);
desc->status &= ~IRQ_INPROGRESS;
}
static struct irq_chip intc_irq_chip = {
.name = "CF-INTC",
.mask = intc_irq_mask,
.unmask = intc_irq_unmask,
.mask_ack = intc_irq_mask,
.ack = intc_irq_ack,
.set_type = intc_irq_set_type,
};
void __init init_IRQ(void)
{
int irq;
int irq, edge;
init_vectors();
@ -128,11 +166,17 @@ void __init init_IRQ(void)
writel(0x88888888, MCF_MBAR + MCFSIM_ICR4);
for (irq = 0; (irq < NR_IRQS); irq++) {
irq_desc[irq].status = IRQ_DISABLED;
irq_desc[irq].action = NULL;
irq_desc[irq].depth = 1;
irq_desc[irq].chip = &intc_irq_chip;
intc_irq_set_type(irq, 0);
set_irq_chip(irq, &intc_irq_chip);
edge = 0;
if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX))
edge = intc_irqmap[irq - MCFINT_VECBASE].ack;
if (edge) {
set_irq_type(irq, IRQ_TYPE_EDGE_RISING);
set_irq_handler(irq, intc_external_irq);
} else {
set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
set_irq_handler(irq, handle_level_irq);
}
}
}

4
arch/m68knommu/platform/527x/Makefile
View file

@ -8,8 +8,8 @@
# on the console port whenever a DBG interrupt occurs. You have to
# set up you HW breakpoints to trigger a DBG interrupt:
#
# EXTRA_CFLAGS += -DTRAP_DBG_INTERRUPT
# EXTRA_AFLAGS += -DTRAP_DBG_INTERRUPT
# ccflags-y := -DTRAP_DBG_INTERRUPT
# asflags-y := -DTRAP_DBG_INTERRUPT
#
asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1

4
arch/m68knommu/platform/528x/Makefile
View file

@ -8,8 +8,8 @@
# on the console port whenever a DBG interrupt occurs. You have to
# set up you HW breakpoints to trigger a DBG interrupt:
#
# EXTRA_CFLAGS += -DTRAP_DBG_INTERRUPT
# EXTRA_AFLAGS += -DTRAP_DBG_INTERRUPT
# ccflags-y := -DTRAP_DBG_INTERRUPT
# asflags-y := -DTRAP_DBG_INTERRUPT
#
asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1

4
arch/m68knommu/platform/5307/Makefile
View file

@ -8,8 +8,8 @@
# on the console port whenever a DBG interrupt occurs. You have to
# set up you HW breakpoints to trigger a DBG interrupt:
#
# EXTRA_CFLAGS += -DTRAP_DBG_INTERRUPT
# EXTRA_AFLAGS += -DTRAP_DBG_INTERRUPT
# ccflags-y := -DTRAP_DBG_INTERRUPT
# asflags-y := -DTRAP_DBG_INTERRUPT
#
asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1

4
arch/m68knommu/platform/532x/Makefile
View file

@ -8,8 +8,8 @@
# on the console port whenever a DBG interrupt occurs. You have to
# set up you HW breakpoints to trigger a DBG interrupt:
#
# EXTRA_CFLAGS += -DTRAP_DBG_INTERRUPT
# EXTRA_AFLAGS += -DTRAP_DBG_INTERRUPT
# ccflags-y := -DTRAP_DBG_INTERRUPT
# asflags-y := -DTRAP_DBG_INTERRUPT
#
asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1

4
arch/m68knommu/platform/5407/Makefile
View file

@ -8,8 +8,8 @@
# on the console port whenever a DBG interrupt occurs. You have to
# set up you HW breakpoints to trigger a DBG interrupt:
#
# EXTRA_CFLAGS += -DTRAP_DBG_INTERRUPT
# EXTRA_AFLAGS += -DTRAP_DBG_INTERRUPT
# ccflags-y := -DTRAP_DBG_INTERRUPT
# asflags-y := -DTRAP_DBG_INTERRUPT
#
asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1

18
arch/m68knommu/platform/548x/Makefile Normal file
View file

@ -0,0 +1,18 @@
#
# Makefile for the m68knommu linux kernel.
#
#
# If you want to play with the HW breakpoints then you will
# need to add define this, which will give you a stack backtrace
# on the console port whenever a DBG interrupt occurs. You have to
# set up you HW breakpoints to trigger a DBG interrupt:
#
# EXTRA_CFLAGS += -DTRAP_DBG_INTERRUPT
# EXTRA_AFLAGS += -DTRAP_DBG_INTERRUPT
#
asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
obj-y := config.o

115
arch/m68knommu/platform/548x/config.c Normal file
View file

@ -0,0 +1,115 @@
/***************************************************************************/
/*
* linux/arch/m68knommu/platform/548x/config.c
*
* Copyright (C) 2010, Philippe De Muyter <phdm@macqel.be>
*/
/***************************************************************************/
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <asm/machdep.h>
#include <asm/coldfire.h>
#include <asm/m548xsim.h>
#include <asm/mcfuart.h>
#include <asm/m548xgpt.h>
/***************************************************************************/
static struct mcf_platform_uart m548x_uart_platform[] = {
{
.mapbase = MCF_MBAR + MCFUART_BASE1,
.irq = 64 + 35,
},
{
.mapbase = MCF_MBAR + MCFUART_BASE2,
.irq = 64 + 34,
},
{
.mapbase = MCF_MBAR + MCFUART_BASE3,
.irq = 64 + 33,
},
{
.mapbase = MCF_MBAR + MCFUART_BASE4,
.irq = 64 + 32,
},
};
static struct platform_device m548x_uart = {
.name = "mcfuart",
.id = 0,
.dev.platform_data = m548x_uart_platform,
};
static struct platform_device *m548x_devices[] __initdata = {
&m548x_uart,
};
/***************************************************************************/
static void __init m548x_uart_init_line(int line, int irq)
{
int rts_cts;
/* enable io pins */
switch (line) {
case 0:
rts_cts = 0; break;
case 1:
rts_cts = MCF_PAR_PSC_RTS_RTS; break;
case 2:
rts_cts = MCF_PAR_PSC_RTS_RTS | MCF_PAR_PSC_CTS_CTS; break;
case 3:
rts_cts = 0; break;
}
__raw_writeb(MCF_PAR_PSC_TXD | rts_cts | MCF_PAR_PSC_RXD,
MCF_MBAR + MCF_PAR_PSC(line));
}
static void __init m548x_uarts_init(void)
{
const int nrlines = ARRAY_SIZE(m548x_uart_platform);
int line;
for (line = 0; (line < nrlines); line++)
m548x_uart_init_line(line, m548x_uart_platform[line].irq);
}
/***************************************************************************/
static void mcf548x_reset(void)
{
/* disable interrupts and enable the watchdog */
asm("movew #0x2700, %sr\n");
__raw_writel(0, MCF_MBAR + MCF_GPT_GMS0);
__raw_writel(MCF_GPT_GCIR_CNT(1), MCF_MBAR + MCF_GPT_GCIR0);
__raw_writel(MCF_GPT_GMS_WDEN | MCF_GPT_GMS_CE | MCF_GPT_GMS_TMS(4),
MCF_MBAR + MCF_GPT_GMS0);
}
/***************************************************************************/
void __init config_BSP(char *commandp, int size)
{
mach_reset = mcf548x_reset;
m548x_uarts_init();
}
/***************************************************************************/
static int __init init_BSP(void)
{
platform_add_devices(m548x_devices, ARRAY_SIZE(m548x_devices));
return 0;
}
arch_initcall(init_BSP);
/***************************************************************************/

22
arch/m68knommu/platform/68328/entry.S
View file

@ -46,7 +46,7 @@ do_trace:
movel #-ENOSYS,%sp@(PT_OFF_D0) /* needed for strace*/
subql #4,%sp
SAVE_SWITCH_STACK
jbsr syscall_trace
jbsr syscall_trace_enter
RESTORE_SWITCH_STACK
addql #4,%sp
movel %sp@(PT_OFF_ORIG_D0),%d1
@ -60,7 +60,7 @@ do_trace:
1: movel %d0,%sp@(PT_OFF_D0) /* save the return value */
subql #4,%sp /* dummy return address */
SAVE_SWITCH_STACK
jbsr syscall_trace
jbsr syscall_trace_leave
ret_from_signal:
RESTORE_SWITCH_STACK
@ -80,7 +80,7 @@ ENTRY(system_call)
movel %sp,%d1 /* get thread_info pointer */
andl #-THREAD_SIZE,%d1
movel %d1,%a2
btst #TIF_SYSCALL_TRACE,%a2@(TI_FLAGS)
btst #(TIF_SYSCALL_TRACE%8),%a2@(TI_FLAGS+(31-TIF_SYSCALL_TRACE)/8)
jne do_trace
cmpl #NR_syscalls,%d0
jcc badsys
@ -133,7 +133,7 @@ Lreturn:
*/
inthandler1:
SAVE_ALL
movew %sp@(PT_OFF_VECTOR), %d0
movew %sp@(PT_OFF_FORMATVEC), %d0
and #0x3ff, %d0
movel %sp,%sp@-
@ -144,7 +144,7 @@ inthandler1:
inthandler2:
SAVE_ALL
movew %sp@(PT_OFF_VECTOR), %d0
movew %sp@(PT_OFF_FORMATVEC), %d0
and #0x3ff, %d0
movel %sp,%sp@-
@ -155,7 +155,7 @@ inthandler2:
inthandler3:
SAVE_ALL
movew %sp@(PT_OFF_VECTOR), %d0
movew %sp@(PT_OFF_FORMATVEC), %d0
and #0x3ff, %d0
movel %sp,%sp@-
@ -166,7 +166,7 @@ inthandler3:
inthandler4:
SAVE_ALL
movew %sp@(PT_OFF_VECTOR), %d0
movew %sp@(PT_OFF_FORMATVEC), %d0
and #0x3ff, %d0
movel %sp,%sp@-
@ -177,7 +177,7 @@ inthandler4:
inthandler5:
SAVE_ALL
movew %sp@(PT_OFF_VECTOR), %d0
movew %sp@(PT_OFF_FORMATVEC), %d0
and #0x3ff, %d0
movel %sp,%sp@-
@ -188,7 +188,7 @@ inthandler5:
inthandler6:
SAVE_ALL
movew %sp@(PT_OFF_VECTOR), %d0
movew %sp@(PT_OFF_FORMATVEC), %d0
and #0x3ff, %d0
movel %sp,%sp@-
@ -199,7 +199,7 @@ inthandler6:
inthandler7:
SAVE_ALL
movew %sp@(PT_OFF_VECTOR), %d0
movew %sp@(PT_OFF_FORMATVEC), %d0
and #0x3ff, %d0
movel %sp,%sp@-
@ -210,7 +210,7 @@ inthandler7:
inthandler:
SAVE_ALL
movew %sp@(PT_OFF_VECTOR), %d0
movew %sp@(PT_OFF_FORMATVEC), %d0
and #0x3ff, %d0
movel %sp,%sp@-

6
arch/m68knommu/platform/68328/head-de2.S
View file

@ -1,11 +1,5 @@
#if defined(CONFIG_RAM32MB)
#define MEM_END 0x02000000 /* Memory size 32Mb */
#elif defined(CONFIG_RAM16MB)
#define MEM_END 0x01000000 /* Memory size 16Mb */
#else
#define MEM_END 0x00800000 /* Memory size 8Mb */
#endif
#undef CRT_DEBUG

27
arch/m68knommu/platform/68328/head-ram.S
View file

@ -67,33 +67,6 @@ pclp1:
beq pclp1
#endif /* DEBUG */
#ifdef CONFIG_RELOCATE
/* Copy me to RAM */
moveal #__rom_start, %a0
moveal #_stext, %a1
moveal #_edata, %a2
/* Copy %a0 to %a1 until %a1 == %a2 */
LD1:
movel %a0@+, %d0
movel %d0, %a1@+
cmpal %a1, %a2
bhi LD1
#ifdef DEBUG
moveq #74, %d7 /* 'J' */
moveb %d7,0xfffff907 /* No absolute addresses */
pclp2:
movew 0xfffff906, %d7
andw #0x2000, %d7
beq pclp2
#endif /* DEBUG */
/* jump into the RAM copy */
jmp ram_jump
ram_jump:
#endif /* CONFIG_RELOCATE */
#ifdef DEBUG
moveq #82, %d7 /* 'R' */
moveb %d7,0xfffff907 /* No absolute addresses */

6
arch/m68knommu/platform/68328/ints.c
View file

@ -179,10 +179,8 @@ void __init init_IRQ(void)
IMR = ~0;
for (i = 0; (i < NR_IRQS); i++) {
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = NULL;
irq_desc[i].depth = 1;
irq_desc[i].chip = &intc_irq_chip;
set_irq_chip(irq, &intc_irq_chip);
set_irq_handler(irq, handle_level_irq);
}
}

13
arch/m68knommu/platform/68360/entry.S
View file

@ -42,7 +42,7 @@ do_trace:
movel #-ENOSYS,%sp@(PT_OFF_D0) /* needed for strace*/
subql #4,%sp
SAVE_SWITCH_STACK
jbsr syscall_trace
jbsr syscall_trace_enter
RESTORE_SWITCH_STACK
addql #4,%sp
movel %sp@(PT_OFF_ORIG_D0),%d1
@ -56,7 +56,7 @@ do_trace:
1: movel %d0,%sp@(PT_OFF_D0) /* save the return value */
subql #4,%sp /* dummy return address */
SAVE_SWITCH_STACK
jbsr syscall_trace
jbsr syscall_trace_leave
ret_from_signal:
RESTORE_SWITCH_STACK
@ -71,7 +71,12 @@ ENTRY(system_call)
jbsr set_esp0
addql #4,%sp
btst #PF_TRACESYS_BIT,%a2@(TASK_FLAGS+PF_TRACESYS_OFF)
movel %sp@(PT_OFF_ORIG_D0),%d0
movel %sp,%d1 /* get thread_info pointer */
andl #-THREAD_SIZE,%d1
movel %d1,%a2
btst #(TIF_SYSCALL_TRACE%8),%a2@(TI_FLAGS+(31-TIF_SYSCALL_TRACE)/8)
jne do_trace
cmpl #NR_syscalls,%d0
jcc badsys
@ -124,7 +129,7 @@ Lreturn:
*/
inthandler:
SAVE_ALL
movew %sp@(PT_OFF_VECTOR), %d0
movew %sp@(PT_OFF_FORMATVEC), %d0
and.l #0x3ff, %d0
lsr.l #0x02, %d0

6
arch/m68knommu/platform/68360/ints.c
View file

@ -132,10 +132,8 @@ void init_IRQ(void)
pquicc->intr_cimr = 0x00000000;
for (i = 0; (i < NR_IRQS); i++) {
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = NULL;
irq_desc[i].depth = 1;
irq_desc[i].chip = &intc_irq_chip;
set_irq_chip(irq, &intc_irq_chip);
set_irq_handler(irq, handle_level_irq);
}
}

5
arch/m68knommu/platform/68VZ328/config.c
View file

@ -90,11 +90,6 @@ static void init_hardware(char *command, int size)
PDIQEG &= ~PD(1);
PDIRQEN |= PD(1); /* IRQ enabled */
#ifdef CONFIG_68328_SERIAL_UART2
/* Enable RXD TXD port bits to enable UART2 */
PJSEL &= ~(PJ(5) | PJ(4));
#endif
#ifdef CONFIG_INIT_LCD
/* initialize LCD controller */
LSSA = (long) screen_bits;

5
arch/m68knommu/platform/coldfire/Makefile
View file

@ -8,8 +8,8 @@
# on the console port whenever a DBG interrupt occurs. You have to
# set up you HW breakpoints to trigger a DBG interrupt:
#
# EXTRA_CFLAGS += -DTRAP_DBG_INTERRUPT
# EXTRA_AFLAGS += -DTRAP_DBG_INTERRUPT
# ccflags-y := -DTRAP_DBG_INTERRUPT
# asflags-y := -DTRAP_DBG_INTERRUPT
#
asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
@ -26,6 +26,7 @@ obj-$(CONFIG_M528x) += pit.o intc-2.o
obj-$(CONFIG_M5307) += timers.o intc.o
obj-$(CONFIG_M532x) += timers.o intc-simr.o
obj-$(CONFIG_M5407) += timers.o intc.o
obj-$(CONFIG_M548x) += sltimers.o intc-2.o
obj-y += pinmux.o gpio.o
extra-y := head.o

4
arch/m68knommu/platform/coldfire/entry.S
View file

@ -88,7 +88,7 @@ ENTRY(system_call)
movel %d2,PT_OFF_D0(%sp) /* on syscall entry */
subql #4,%sp
SAVE_SWITCH_STACK
jbsr syscall_trace
jbsr syscall_trace_enter
RESTORE_SWITCH_STACK
addql #4,%sp
movel %d3,%a0
@ -96,7 +96,7 @@ ENTRY(system_call)
movel %d0,%sp@(PT_OFF_D0) /* save the return value */
subql #4,%sp /* dummy return address */
SAVE_SWITCH_STACK
jbsr syscall_trace
jbsr syscall_trace_leave
ret_from_signal:
RESTORE_SWITCH_STACK

55
arch/m68knommu/platform/coldfire/intc-2.c
View file

@ -1,5 +1,11 @@
/*
* intc-1.c
* intc-2.c
*
* General interrupt controller code for the many ColdFire cores that use
* interrupt controllers with 63 interrupt sources, organized as 56 fully-
* programmable + 7 fixed-level interrupt sources. This includes the 523x
* family, the 5270, 5271, 5274, 5275, and the 528x family which have two such
* controllers, and the 547x and 548x families which have only one of them.
*
* (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com>
*
@ -19,21 +25,37 @@
#include <asm/traps.h>
/*
* Each vector needs a unique priority and level asscoiated with it.
* We don't really care so much what they are, we don't rely on the
* tranditional priority interrupt scheme of the m68k/ColdFire.
* Bit definitions for the ICR family of registers.
*/
static u8 intc_intpri = 0x36;
#define MCFSIM_ICR_LEVEL(l) ((l)<<3) /* Level l intr */
#define MCFSIM_ICR_PRI(p) (p) /* Priority p intr */
/*
* Each vector needs a unique priority and level associated with it.
* We don't really care so much what they are, we don't rely on the
* traditional priority interrupt scheme of the m68k/ColdFire.
*/
static u8 intc_intpri = MCFSIM_ICR_LEVEL(6) | MCFSIM_ICR_PRI(6);
#ifdef MCFICM_INTC1
#define NR_VECS 128
#else
#define NR_VECS 64
#endif
static void intc_irq_mask(unsigned int irq)
{
if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + 128)) {
if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + NR_VECS)) {
unsigned long imraddr;
u32 val, imrbit;
irq -= MCFINT_VECBASE;
imraddr = MCF_IPSBAR;
#ifdef MCFICM_INTC1
imraddr += (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0;
#else
imraddr += MCFICM_INTC0;
#endif
imraddr += (irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL;
imrbit = 0x1 << (irq & 0x1f);
@ -44,13 +66,17 @@ static void intc_irq_mask(unsigned int irq)
static void intc_irq_unmask(unsigned int irq)
{
if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + 128)) {
if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + NR_VECS)) {
unsigned long intaddr, imraddr, icraddr;
u32 val, imrbit;
irq -= MCFINT_VECBASE;
intaddr = MCF_IPSBAR;
#ifdef MCFICM_INTC1
intaddr += (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0;
#else
intaddr += MCFICM_INTC0;
#endif
imraddr = intaddr + ((irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL);
icraddr = intaddr + MCFINTC_ICR0 + (irq & 0x3f);
imrbit = 0x1 << (irq & 0x1f);
@ -67,10 +93,16 @@ static void intc_irq_unmask(unsigned int irq)
}
}
static int intc_irq_set_type(unsigned int irq, unsigned int type)
{
return 0;
}
static struct irq_chip intc_irq_chip = {
.name = "CF-INTC",
.mask = intc_irq_mask,
.unmask = intc_irq_unmask,
.set_type = intc_irq_set_type,
};
void __init init_IRQ(void)
@ -81,13 +113,14 @@ void __init init_IRQ(void)
/* Mask all interrupt sources */
__raw_writel(0x1, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRL);
#ifdef MCFICM_INTC1
__raw_writel(0x1, MCF_IPSBAR + MCFICM_INTC1 + MCFINTC_IMRL);
#endif
for (irq = 0; (irq < NR_IRQS); irq++) {
irq_desc[irq].status = IRQ_DISABLED;
irq_desc[irq].action = NULL;
irq_desc[irq].depth = 1;
irq_desc[irq].chip = &intc_irq_chip;
set_irq_chip(irq, &intc_irq_chip);
set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
set_irq_handler(irq, handle_level_irq);
}
}

10
arch/m68knommu/platform/coldfire/intc-simr.c
View file

@ -1,6 +1,8 @@
/*
* intc-simr.c
*
* Interrupt controller code for the ColdFire 5208, 5207 & 532x parts.
*
* (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com>
*
* This file is subject to the terms and conditions of the GNU General Public
@ -68,11 +70,9 @@ void __init init_IRQ(void)
__raw_writeb(0xff, MCFINTC1_SIMR);
for (irq = 0; (irq < NR_IRQS); irq++) {
irq_desc[irq].status = IRQ_DISABLED;
irq_desc[irq].action = NULL;
irq_desc[irq].depth = 1;
irq_desc[irq].chip = &intc_irq_chip;
intc_irq_set_type(irq, 0);
set_irq_chip(irq, &intc_irq_chip);
set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
set_irq_handler(irq, handle_level_irq);
}
}

8
arch/m68knommu/platform/coldfire/intc.c
View file

@ -143,11 +143,9 @@ void __init init_IRQ(void)
mcf_maskimr(0xffffffff);
for (irq = 0; (irq < NR_IRQS); irq++) {
irq_desc[irq].status = IRQ_DISABLED;
irq_desc[irq].action = NULL;
irq_desc[irq].depth = 1;
irq_desc[irq].chip = &intc_irq_chip;
intc_irq_set_type(irq, 0);
set_irq_chip(irq, &intc_irq_chip);
set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
set_irq_handler(irq, handle_level_irq);
}
}

145
arch/m68knommu/platform/coldfire/sltimers.c Normal file
View file

@ -0,0 +1,145 @@
/***************************************************************************/
/*
* sltimers.c -- generic ColdFire slice timer support.
*
* Copyright (C) 2009-2010, Philippe De Muyter <phdm@macqel.be>
* based on
* timers.c -- generic ColdFire hardware timer support.
* Copyright (C) 1999-2008, Greg Ungerer <gerg@snapgear.com>
*/
/***************************************************************************/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/profile.h>
#include <linux/clocksource.h>
#include <asm/io.h>
#include <asm/traps.h>
#include <asm/machdep.h>
#include <asm/coldfire.h>
#include <asm/mcfslt.h>
#include <asm/mcfsim.h>
/***************************************************************************/
#ifdef CONFIG_HIGHPROFILE
/*
* By default use Slice Timer 1 as the profiler clock timer.
*/
#define PA(a) (MCF_MBAR + MCFSLT_TIMER1 + (a))
/*
* Choose a reasonably fast profile timer. Make it an odd value to
* try and get good coverage of kernel operations.
*/
#define PROFILEHZ 1013
irqreturn_t mcfslt_profile_tick(int irq, void *dummy)
{
/* Reset Slice Timer 1 */
__raw_writel(MCFSLT_SSR_BE | MCFSLT_SSR_TE, PA(MCFSLT_SSR));
if (current->pid)
profile_tick(CPU_PROFILING);
return IRQ_HANDLED;
}
static struct irqaction mcfslt_profile_irq = {
.name = "profile timer",
.flags = IRQF_DISABLED | IRQF_TIMER,
.handler = mcfslt_profile_tick,
};
void mcfslt_profile_init(void)
{
printk(KERN_INFO "PROFILE: lodging TIMER 1 @ %dHz as profile timer\n",
PROFILEHZ);
setup_irq(MCF_IRQ_PROFILER, &mcfslt_profile_irq);
/* Set up TIMER 2 as high speed profile clock */
__raw_writel(MCF_BUSCLK / PROFILEHZ - 1, PA(MCFSLT_STCNT));
__raw_writel(MCFSLT_SCR_RUN | MCFSLT_SCR_IEN | MCFSLT_SCR_TEN,
PA(MCFSLT_SCR));
}
#endif /* CONFIG_HIGHPROFILE */
/***************************************************************************/
/*
* By default use Slice Timer 0 as the system clock timer.
*/
#define TA(a) (MCF_MBAR + MCFSLT_TIMER0 + (a))
static u32 mcfslt_cycles_per_jiffy;
static u32 mcfslt_cnt;
static irqreturn_t mcfslt_tick(int irq, void *dummy)
{
/* Reset Slice Timer 0 */
__raw_writel(MCFSLT_SSR_BE | MCFSLT_SSR_TE, TA(MCFSLT_SSR));
mcfslt_cnt += mcfslt_cycles_per_jiffy;
return arch_timer_interrupt(irq, dummy);
}
static struct irqaction mcfslt_timer_irq = {
.name = "timer",
.flags = IRQF_DISABLED | IRQF_TIMER,
.handler = mcfslt_tick,
};
static cycle_t mcfslt_read_clk(struct clocksource *cs)
{
unsigned long flags;
u32 cycles;
u16 scnt;
local_irq_save(flags);
scnt = __raw_readl(TA(MCFSLT_SCNT));
cycles = mcfslt_cnt;
local_irq_restore(flags);
/* substract because slice timers count down */
return cycles - scnt;
}
static struct clocksource mcfslt_clk = {
.name = "slt",
.rating = 250,
.read = mcfslt_read_clk,
.shift = 20,
.mask = CLOCKSOURCE_MASK(32),
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
};
void hw_timer_init(void)
{
mcfslt_cycles_per_jiffy = MCF_BUSCLK / HZ;
/*
* The coldfire slice timer (SLT) runs from STCNT to 0 included,
* then STCNT again and so on. It counts thus actually
* STCNT + 1 steps for 1 tick, not STCNT. So if you want
* n cycles, initialize STCNT with n - 1.
*/
__raw_writel(mcfslt_cycles_per_jiffy - 1, TA(MCFSLT_STCNT));
__raw_writel(MCFSLT_SCR_RUN | MCFSLT_SCR_IEN | MCFSLT_SCR_TEN,
TA(MCFSLT_SCR));
/* initialize mcfslt_cnt knowing that slice timers count down */
mcfslt_cnt = mcfslt_cycles_per_jiffy;
setup_irq(MCF_IRQ_TIMER, &mcfslt_timer_irq);
mcfslt_clk.mult = clocksource_hz2mult(MCF_BUSCLK, mcfslt_clk.shift);
clocksource_register(&mcfslt_clk);
#ifdef CONFIG_HIGHPROFILE
mcfslt_profile_init();
#endif
}

5
drivers/serial/68328serial.h
View file

@ -181,13 +181,8 @@ struct m68k_serial {
/*
* Define the number of ports supported and their irqs.
*/
#ifndef CONFIG_68328_SERIAL_UART2
#define NR_PORTS 1
#define UART_IRQ_DEFNS {UART_IRQ_NUM}
#else
#define NR_PORTS 2
#define UART_IRQ_DEFNS {UART1_IRQ_NUM, UART2_IRQ_NUM}
#endif
#endif /* __KERNEL__ */
#endif /* !(_MC683XX_SERIAL_H) */