RDMA/cxgb3: Fixes for zero STag
Handling the zero STag in receive work request requires some extra
logic in the driver:
- Only set the QP_PRIV bit for kernel mode QPs.
- Add a zero STag build function for recv wrs. The uP needs a PBL
allocated and passed down in the recv WR so it can construct a HW
PBL for the zero STag S/G entries. Note: we need to place a few
restrictions on zero STag usage because of this:
1) all SGEs in a recv WR must either be zero STag or not. No mixing.
2) an individual SGE length cannot exceed 128MB for a zero-stag SGE.
This should be OK since it's not really practical to allocate
such a large chunk of pinned contiguous DMA mapped memory.
- Add an optimized non-zero-STag recv wr format for kernel users.
This is needed to optimize both zero and non-zero STag cracking in
the recv path for kernel users.
- Remove the iwch_ prefix from the static build functions.
- Bump required FW version.
Signed-off-by: Steve Wise <swise@opengridcomputing.com>
This commit is contained in:
Steve Wise
Roland Dreier
parent
96f15c0353
commit
4ab928f692
5 changed files with 132 additions and 28 deletions
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@ -278,7 +278,7 @@ int cxio_create_qp(struct cxio_rdev *rdev_p, u32 kernel_domain,
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if (!wq->qpid)
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return -ENOMEM;
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wq->rq = kzalloc(depth * sizeof(u64), GFP_KERNEL);
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wq->rq = kzalloc(depth * sizeof(struct t3_swrq), GFP_KERNEL);
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if (!wq->rq)
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goto err1;
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@ -302,6 +302,7 @@ int cxio_create_qp(struct cxio_rdev *rdev_p, u32 kernel_domain,
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if (!kernel_domain)
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wq->udb = (u64)rdev_p->rnic_info.udbell_physbase +
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(wq->qpid << rdev_p->qpshift);
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wq->rdev = rdev_p;
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PDBG("%s qpid 0x%x doorbell 0x%p udb 0x%llx\n", __func__,
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wq->qpid, wq->doorbell, (unsigned long long) wq->udb);
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return 0;
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@ -1266,13 +1267,16 @@ int cxio_poll_cq(struct t3_wq *wq, struct t3_cq *cq, struct t3_cqe *cqe,
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wq->sq_rptr = CQE_WRID_SQ_WPTR(*hw_cqe);
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PDBG("%s completing sq idx %ld\n", __func__,
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Q_PTR2IDX(wq->sq_rptr, wq->sq_size_log2));
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*cookie = (wq->sq +
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Q_PTR2IDX(wq->sq_rptr, wq->sq_size_log2))->wr_id;
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*cookie = wq->sq[Q_PTR2IDX(wq->sq_rptr, wq->sq_size_log2)].wr_id;
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wq->sq_rptr++;
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} else {
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PDBG("%s completing rq idx %ld\n", __func__,
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Q_PTR2IDX(wq->rq_rptr, wq->rq_size_log2));
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*cookie = *(wq->rq + Q_PTR2IDX(wq->rq_rptr, wq->rq_size_log2));
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*cookie = wq->rq[Q_PTR2IDX(wq->rq_rptr, wq->rq_size_log2)].wr_id;
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if (wq->rq[Q_PTR2IDX(wq->rq_rptr, wq->rq_size_log2)].pbl_addr)
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cxio_hal_pblpool_free(wq->rdev,
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wq->rq[Q_PTR2IDX(wq->rq_rptr,
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wq->rq_size_log2)].pbl_addr, T3_STAG0_PBL_SIZE);
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wq->rq_rptr++;
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}
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@ -39,6 +39,9 @@
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#define T3_MAX_SGE 4
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#define T3_MAX_INLINE 64
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#define T3_STAG0_PBL_SIZE (2 * T3_MAX_SGE << 3)
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#define T3_STAG0_MAX_PBE_LEN (128 * 1024 * 1024)
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#define T3_STAG0_PAGE_SHIFT 15
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#define Q_EMPTY(rptr,wptr) ((rptr)==(wptr))
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#define Q_FULL(rptr,wptr,size_log2) ( (((wptr)-(rptr))>>(size_log2)) && \
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@ -665,6 +668,11 @@ struct t3_swsq {
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int signaled;
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};
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struct t3_swrq {
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__u64 wr_id;
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__u32 pbl_addr;
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};
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/*
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* A T3 WQ implements both the SQ and RQ.
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*/
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@ -681,14 +689,15 @@ struct t3_wq {
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u32 sq_wptr; /* sq_wptr - sq_rptr == count of */
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u32 sq_rptr; /* pending wrs */
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u32 sq_size_log2; /* sq size */
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u64 *rq; /* SW RQ (holds consumer wr_ids */
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struct t3_swrq *rq; /* SW RQ (holds consumer wr_ids */
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u32 rq_wptr; /* rq_wptr - rq_rptr == count of */
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u32 rq_rptr; /* pending wrs */
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u64 *rq_oldest_wr; /* oldest wr on the SW RQ */
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struct t3_swrq *rq_oldest_wr; /* oldest wr on the SW RQ */
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u32 rq_size_log2; /* rq size */
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u32 rq_addr; /* rq adapter address */
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void __iomem *doorbell; /* kernel db */
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u64 udb; /* user db if any */
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struct cxio_rdev *rdev;
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};
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struct t3_cq {
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@ -1007,10 +1007,10 @@ static struct ib_qp *iwch_create_qp(struct ib_pd *pd,
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qhp->ibqp.qp_num = qhp->wq.qpid;
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init_timer(&(qhp->timer));
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PDBG("%s sq_num_entries %d, rq_num_entries %d "
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"qpid 0x%0x qhp %p dma_addr 0x%llx size %d\n",
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"qpid 0x%0x qhp %p dma_addr 0x%llx size %d rq_addr 0x%x\n",
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__func__, qhp->attr.sq_num_entries, qhp->attr.rq_num_entries,
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qhp->wq.qpid, qhp, (unsigned long long) qhp->wq.dma_addr,
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1 << qhp->wq.size_log2);
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1 << qhp->wq.size_log2, qhp->wq.rq_addr);
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return &qhp->ibqp;
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}
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@ -33,10 +33,11 @@
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#include "iwch.h"
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#include "iwch_cm.h"
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#include "cxio_hal.h"
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#include "cxio_resource.h"
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#define NO_SUPPORT -1
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static int iwch_build_rdma_send(union t3_wr *wqe, struct ib_send_wr *wr,
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static int build_rdma_send(union t3_wr *wqe, struct ib_send_wr *wr,
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u8 * flit_cnt)
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{
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int i;
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@ -81,7 +82,7 @@ static int iwch_build_rdma_send(union t3_wr *wqe, struct ib_send_wr *wr,
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return 0;
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}
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static int iwch_build_rdma_write(union t3_wr *wqe, struct ib_send_wr *wr,
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static int build_rdma_write(union t3_wr *wqe, struct ib_send_wr *wr,
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u8 *flit_cnt)
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{
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int i;
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@ -122,7 +123,7 @@ static int iwch_build_rdma_write(union t3_wr *wqe, struct ib_send_wr *wr,
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return 0;
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}
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static int iwch_build_rdma_read(union t3_wr *wqe, struct ib_send_wr *wr,
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static int build_rdma_read(union t3_wr *wqe, struct ib_send_wr *wr,
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u8 *flit_cnt)
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{
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if (wr->num_sge > 1)
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@ -143,7 +144,7 @@ static int iwch_build_rdma_read(union t3_wr *wqe, struct ib_send_wr *wr,
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return 0;
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}
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static int iwch_build_fastreg(union t3_wr *wqe, struct ib_send_wr *wr,
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static int build_fastreg(union t3_wr *wqe, struct ib_send_wr *wr,
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u8 *flit_cnt, int *wr_cnt, struct t3_wq *wq)
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{
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int i;
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@ -185,7 +186,7 @@ static int iwch_build_fastreg(union t3_wr *wqe, struct ib_send_wr *wr,
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return 0;
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}
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static int iwch_build_inv_stag(union t3_wr *wqe, struct ib_send_wr *wr,
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static int build_inv_stag(union t3_wr *wqe, struct ib_send_wr *wr,
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u8 *flit_cnt)
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{
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wqe->local_inv.stag = cpu_to_be32(wr->ex.invalidate_rkey);
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@ -244,23 +245,106 @@ static int iwch_sgl2pbl_map(struct iwch_dev *rhp, struct ib_sge *sg_list,
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return 0;
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}
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static int iwch_build_rdma_recv(struct iwch_dev *rhp, union t3_wr *wqe,
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static int build_rdma_recv(struct iwch_qp *qhp, union t3_wr *wqe,
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struct ib_recv_wr *wr)
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{
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int i;
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if (wr->num_sge > T3_MAX_SGE)
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return -EINVAL;
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int i, err = 0;
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u32 pbl_addr[T3_MAX_SGE];
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u8 page_size[T3_MAX_SGE];
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err = iwch_sgl2pbl_map(qhp->rhp, wr->sg_list, wr->num_sge, pbl_addr,
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page_size);
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if (err)
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return err;
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wqe->recv.pagesz[0] = page_size[0];
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wqe->recv.pagesz[1] = page_size[1];
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wqe->recv.pagesz[2] = page_size[2];
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wqe->recv.pagesz[3] = page_size[3];
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wqe->recv.num_sgle = cpu_to_be32(wr->num_sge);
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for (i = 0; i < wr->num_sge; i++) {
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wqe->recv.sgl[i].stag = cpu_to_be32(wr->sg_list[i].lkey);
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wqe->recv.sgl[i].len = cpu_to_be32(wr->sg_list[i].length);
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wqe->recv.sgl[i].to = cpu_to_be64(wr->sg_list[i].addr);
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/* to in the WQE == the offset into the page */
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wqe->recv.sgl[i].to = cpu_to_be64(((u32) wr->sg_list[i].addr) %
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(1UL << (12 + page_size[i])));
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/* pbl_addr is the adapters address in the PBL */
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wqe->recv.pbl_addr[i] = cpu_to_be32(pbl_addr[i]);
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}
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for (; i < T3_MAX_SGE; i++) {
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wqe->recv.sgl[i].stag = 0;
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wqe->recv.sgl[i].len = 0;
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wqe->recv.sgl[i].to = 0;
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wqe->recv.pbl_addr[i] = 0;
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}
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qhp->wq.rq[Q_PTR2IDX(qhp->wq.rq_wptr,
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qhp->wq.rq_size_log2)].wr_id = wr->wr_id;
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qhp->wq.rq[Q_PTR2IDX(qhp->wq.rq_wptr,
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qhp->wq.rq_size_log2)].pbl_addr = 0;
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return 0;
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}
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static int build_zero_stag_recv(struct iwch_qp *qhp, union t3_wr *wqe,
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struct ib_recv_wr *wr)
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{
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int i;
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u32 pbl_addr;
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u32 pbl_offset;
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/*
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* The T3 HW requires the PBL in the HW recv descriptor to reference
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* a PBL entry. So we allocate the max needed PBL memory here and pass
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* it to the uP in the recv WR. The uP will build the PBL and setup
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* the HW recv descriptor.
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*/
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pbl_addr = cxio_hal_pblpool_alloc(&qhp->rhp->rdev, T3_STAG0_PBL_SIZE);
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if (!pbl_addr)
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return -ENOMEM;
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/*
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* Compute the 8B aligned offset.
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*/
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pbl_offset = (pbl_addr - qhp->rhp->rdev.rnic_info.pbl_base) >> 3;
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wqe->recv.num_sgle = cpu_to_be32(wr->num_sge);
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for (i = 0; i < wr->num_sge; i++) {
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/*
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* Use a 128MB page size. This and an imposed 128MB
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* sge length limit allows us to require only a 2-entry HW
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* PBL for each SGE. This restriction is acceptable since
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* since it is not possible to allocate 128MB of contiguous
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* DMA coherent memory!
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*/
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if (wr->sg_list[i].length > T3_STAG0_MAX_PBE_LEN)
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return -EINVAL;
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wqe->recv.pagesz[i] = T3_STAG0_PAGE_SHIFT;
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/*
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* T3 restricts a recv to all zero-stag or all non-zero-stag.
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*/
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if (wr->sg_list[i].lkey != 0)
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return -EINVAL;
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wqe->recv.sgl[i].stag = 0;
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wqe->recv.sgl[i].len = cpu_to_be32(wr->sg_list[i].length);
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wqe->recv.sgl[i].to = cpu_to_be64(wr->sg_list[i].addr);
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wqe->recv.pbl_addr[i] = cpu_to_be32(pbl_offset);
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pbl_offset += 2;
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}
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for (; i < T3_MAX_SGE; i++) {
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wqe->recv.pagesz[i] = 0;
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wqe->recv.sgl[i].stag = 0;
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wqe->recv.sgl[i].len = 0;
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wqe->recv.sgl[i].to = 0;
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wqe->recv.pbl_addr[i] = 0;
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}
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qhp->wq.rq[Q_PTR2IDX(qhp->wq.rq_wptr,
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qhp->wq.rq_size_log2)].wr_id = wr->wr_id;
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qhp->wq.rq[Q_PTR2IDX(qhp->wq.rq_wptr,
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qhp->wq.rq_size_log2)].pbl_addr = pbl_addr;
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return 0;
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}
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@ -312,18 +396,18 @@ int iwch_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
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if (wr->send_flags & IB_SEND_FENCE)
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t3_wr_flags |= T3_READ_FENCE_FLAG;
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t3_wr_opcode = T3_WR_SEND;
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err = iwch_build_rdma_send(wqe, wr, &t3_wr_flit_cnt);
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err = build_rdma_send(wqe, wr, &t3_wr_flit_cnt);
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break;
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case IB_WR_RDMA_WRITE:
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case IB_WR_RDMA_WRITE_WITH_IMM:
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t3_wr_opcode = T3_WR_WRITE;
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err = iwch_build_rdma_write(wqe, wr, &t3_wr_flit_cnt);
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err = build_rdma_write(wqe, wr, &t3_wr_flit_cnt);
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break;
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case IB_WR_RDMA_READ:
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case IB_WR_RDMA_READ_WITH_INV:
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t3_wr_opcode = T3_WR_READ;
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t3_wr_flags = 0; /* T3 reads are always signaled */
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err = iwch_build_rdma_read(wqe, wr, &t3_wr_flit_cnt);
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err = build_rdma_read(wqe, wr, &t3_wr_flit_cnt);
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if (err)
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break;
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sqp->read_len = wqe->read.local_len;
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@ -332,14 +416,14 @@ int iwch_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
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break;
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case IB_WR_FAST_REG_MR:
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t3_wr_opcode = T3_WR_FASTREG;
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err = iwch_build_fastreg(wqe, wr, &t3_wr_flit_cnt,
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err = build_fastreg(wqe, wr, &t3_wr_flit_cnt,
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&wr_cnt, &qhp->wq);
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break;
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case IB_WR_LOCAL_INV:
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if (wr->send_flags & IB_SEND_FENCE)
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t3_wr_flags |= T3_LOCAL_FENCE_FLAG;
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t3_wr_opcode = T3_WR_INV_STAG;
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err = iwch_build_inv_stag(wqe, wr, &t3_wr_flit_cnt);
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err = build_inv_stag(wqe, wr, &t3_wr_flit_cnt);
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break;
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default:
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PDBG("%s post of type=%d TBD!\n", __func__,
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@ -398,18 +482,24 @@ int iwch_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
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return -EINVAL;
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}
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while (wr) {
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if (wr->num_sge > T3_MAX_SGE) {
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err = -EINVAL;
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*bad_wr = wr;
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break;
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}
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idx = Q_PTR2IDX(qhp->wq.wptr, qhp->wq.size_log2);
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wqe = (union t3_wr *) (qhp->wq.queue + idx);
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if (num_wrs)
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err = iwch_build_rdma_recv(qhp->rhp, wqe, wr);
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if (wr->sg_list[0].lkey)
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err = build_rdma_recv(qhp, wqe, wr);
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else
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err = build_zero_stag_recv(qhp, wqe, wr);
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else
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err = -ENOMEM;
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if (err) {
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*bad_wr = wr;
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break;
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}
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qhp->wq.rq[Q_PTR2IDX(qhp->wq.rq_wptr, qhp->wq.rq_size_log2)] =
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wr->wr_id;
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build_fw_riwrh((void *) wqe, T3_WR_RCV, T3_COMPLETION_FLAG,
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Q_GENBIT(qhp->wq.wptr, qhp->wq.size_log2),
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0, sizeof(struct t3_receive_wr) >> 3, T3_SOPEOP);
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@ -810,7 +900,8 @@ static int rdma_init(struct iwch_dev *rhp, struct iwch_qp *qhp,
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init_attr.qp_dma_size = (1UL << qhp->wq.size_log2);
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init_attr.rqe_count = iwch_rqes_posted(qhp);
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init_attr.flags = qhp->attr.mpa_attr.initiator ? MPA_INITIATOR : 0;
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init_attr.flags |= capable(CAP_NET_BIND_SERVICE) ? PRIV_QP : 0;
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if (!qhp->ibqp.uobject)
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init_attr.flags |= PRIV_QP;
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if (peer2peer) {
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init_attr.rtr_type = RTR_READ;
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if (init_attr.ord == 0 && qhp->attr.mpa_attr.initiator)
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@ -38,7 +38,7 @@
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#define DRV_VERSION "1.0-ko"
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/* Firmware version */
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#define FW_VERSION_MAJOR 6
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#define FW_VERSION_MAJOR 7
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#define FW_VERSION_MINOR 0
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||||
#define FW_VERSION_MICRO 0
|
||||
#endif /* __CHELSIO_VERSION_H */
|
||||
|
|
|
|||
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Reference in a new issue