nvc0/ppp: initial implementation of engine
Will allow use of the engine if firmware (nvXX_fuc086) provided. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
parent
7d8bd91bf4
commit
4a7950140b
4 changed files with 120 additions and 8 deletions
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@ -180,6 +180,7 @@ nouveau-y += core/engine/mpeg/nv40.o
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nouveau-y += core/engine/mpeg/nv50.o
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nouveau-y += core/engine/mpeg/nv84.o
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nouveau-y += core/engine/ppp/nv98.o
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nouveau-y += core/engine/ppp/nvc0.o
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nouveau-y += core/engine/software/nv04.o
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nouveau-y += core/engine/software/nv10.o
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nouveau-y += core/engine/software/nv50.o
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110
drivers/gpu/drm/nouveau/core/engine/ppp/nvc0.c
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110
drivers/gpu/drm/nouveau/core/engine/ppp/nvc0.c
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@ -0,0 +1,110 @@
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/*
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* Copyright 2012 Maarten Lankhorst
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Maarten Lankhorst
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*/
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#include <core/falcon.h>
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#include <engine/ppp.h>
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struct nvc0_ppp_priv {
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struct nouveau_falcon base;
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};
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/*******************************************************************************
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* PPP object classes
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******************************************************************************/
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static struct nouveau_oclass
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nvc0_ppp_sclass[] = {
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{ 0x90b3, &nouveau_object_ofuncs },
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{},
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};
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/*******************************************************************************
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* PPPP context
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******************************************************************************/
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static struct nouveau_oclass
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nvc0_ppp_cclass = {
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.handle = NV_ENGCTX(PPP, 0xc0),
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.ofuncs = &(struct nouveau_ofuncs) {
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.ctor = _nouveau_falcon_context_ctor,
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.dtor = _nouveau_falcon_context_dtor,
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.init = _nouveau_falcon_context_init,
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.fini = _nouveau_falcon_context_fini,
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.rd32 = _nouveau_falcon_context_rd32,
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.wr32 = _nouveau_falcon_context_wr32,
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},
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};
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/*******************************************************************************
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* PPPP engine/subdev functions
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******************************************************************************/
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static int
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nvc0_ppp_init(struct nouveau_object *object)
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{
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struct nvc0_ppp_priv *priv = (void *)object;
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int ret;
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ret = nouveau_falcon_init(&priv->base);
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if (ret)
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return ret;
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nv_wr32(priv, 0x086010, 0x0000fff2);
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nv_wr32(priv, 0x08601c, 0x0000fff2);
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return 0;
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}
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static int
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nvc0_ppp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
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struct nouveau_oclass *oclass, void *data, u32 size,
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struct nouveau_object **pobject)
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{
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struct nvc0_ppp_priv *priv;
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int ret;
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ret = nouveau_falcon_create(parent, engine, oclass, 0x086000, true,
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"PPPP", "ppp", &priv);
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*pobject = nv_object(priv);
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if (ret)
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return ret;
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nv_subdev(priv)->unit = 0x00000002;
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nv_engine(priv)->cclass = &nvc0_ppp_cclass;
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nv_engine(priv)->sclass = nvc0_ppp_sclass;
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return 0;
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}
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struct nouveau_oclass
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nvc0_ppp_oclass = {
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.handle = NV_ENGINE(PPP, 0xc0),
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.ofuncs = &(struct nouveau_ofuncs) {
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.ctor = nvc0_ppp_ctor,
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.dtor = _nouveau_falcon_dtor,
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.init = nvc0_ppp_init,
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.fini = _nouveau_falcon_fini,
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.rd32 = _nouveau_falcon_rd32,
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.wr32 = _nouveau_falcon_wr32,
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},
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};
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@ -41,5 +41,6 @@ struct nouveau_ppp {
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#define _nouveau_ppp_fini _nouveau_engine_fini
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extern struct nouveau_oclass nv98_ppp_oclass;
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extern struct nouveau_oclass nvc0_ppp_oclass;
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#endif
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@ -76,7 +76,7 @@ nvc0_identify(struct nouveau_device *device)
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device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass;
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device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
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device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
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device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
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device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
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device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
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device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
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device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass;
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@ -104,7 +104,7 @@ nvc0_identify(struct nouveau_device *device)
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device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass;
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device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
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device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
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device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
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device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
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device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
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device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
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device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass;
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@ -132,7 +132,7 @@ nvc0_identify(struct nouveau_device *device)
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device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass;
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device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
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device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
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device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
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device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
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device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
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device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
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device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass;
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@ -160,7 +160,7 @@ nvc0_identify(struct nouveau_device *device)
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device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass;
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device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
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device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
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device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
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device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
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device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
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device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
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device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass;
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@ -188,7 +188,7 @@ nvc0_identify(struct nouveau_device *device)
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device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass;
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device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
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device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
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device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
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device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
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device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
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device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
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device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass;
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@ -216,7 +216,7 @@ nvc0_identify(struct nouveau_device *device)
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device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass;
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device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
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device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
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device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
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device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
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device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
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device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
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device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass;
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device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass;
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device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
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device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
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device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
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device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
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device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
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device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
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device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass;
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@ -272,7 +272,7 @@ nvc0_identify(struct nouveau_device *device)
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device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass;
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device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
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device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
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device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
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device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
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device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
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device->oclass[NVDEV_ENGINE_DISP ] = &nvd0_disp_oclass;
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break;
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