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Blackfin arch: enable reprogram cclk and sclk for bf518f-ezbrd

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Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
This commit is contained in:
Sonic Zhang 2009-01-07 23:14:38 +08:00 • committed by Bryan Wu
parent 501674a593
commit 4934540d9f
2 changed files with 9 additions and 2 deletions
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5
arch/blackfin/Kconfig
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@ -330,6 +330,11 @@ config MEM_MT48LC32M16A2TG_75
depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD) depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD)
default y default y
config MEM_MT48LC32M8A2_75
bool
depends on (BFIN518F_EZBRD)
default y
source "arch/blackfin/mach-bf518/Kconfig" source "arch/blackfin/mach-bf518/Kconfig"
source "arch/blackfin/mach-bf527/Kconfig" source "arch/blackfin/mach-bf527/Kconfig"
source "arch/blackfin/mach-bf533/Kconfig" source "arch/blackfin/mach-bf533/Kconfig"

6
arch/blackfin/include/asm/mem_init.h
View file

@ -13,7 +13,8 @@
defined(CONFIG_MEM_GENERIC_BOARD) || \ defined(CONFIG_MEM_GENERIC_BOARD) || \
defined(CONFIG_MEM_MT48LC32M8A2_75) || \ defined(CONFIG_MEM_MT48LC32M8A2_75) || \
defined(CONFIG_MEM_MT48LC8M32B2B5_7) || \ defined(CONFIG_MEM_MT48LC8M32B2B5_7) || \
defined(CONFIG_MEM_MT48LC32M16A2TG_75) defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \
defined(CONFIG_MEM_MT48LC32M8A2_75)
#if (CONFIG_SCLK_HZ > 119402985) #if (CONFIG_SCLK_HZ > 119402985)
#define SDRAM_tRP TRP_2 #define SDRAM_tRP TRP_2
#define SDRAM_tRP_num 2 #define SDRAM_tRP_num 2
@ -100,7 +101,8 @@
defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \ defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \
defined(CONFIG_MEM_GENERIC_BOARD) || \ defined(CONFIG_MEM_GENERIC_BOARD) || \
defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \ defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \
defined(CONFIG_MEM_MT48LC16M16A2TG_75) defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \
defined(CONFIG_MEM_MT48LC32M8A2_75)
/*SDRAM INFORMATION: */ /*SDRAM INFORMATION: */
#define SDRAM_Tref 64 /* Refresh period in milliseconds */ #define SDRAM_Tref 64 /* Refresh period in milliseconds */
#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */