Techwizz/kernel-fxtec-pro1x
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

blackfin updates for Linux 3.11

Browse source 
-----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.11 (GNU/Linux)
 
 iQIcBAABAgAGBQJR28L1AAoJEJommM3PjknHzPYP/1G5Fxixm8PqCUCO9vGv4xEL
 t1epDnkBZqfNSYnbElQe6Ba6d+NaGGBAj3Qfv/MdPnypTG4op4YQP6V9QsxFN/eW
 g+jI7Nu+xXf4i7QKakC88ek2JxBUW5ysTZovwxQuXA0q1hPoVLMgGJyaUnIWaL8H
 jucHy5THeB8hSpbOAlLUG18vEXpaSi/eeMn6XX99i5anmyeT4Sw2hwFuKXJgGQd/
 +taquzQSwbga9MDwGuZlaui7ZgP33FKQP5p9kn7v2zt+BV5/w0T+MeoloY8EO9uE
 wEJqeZdPHnjKNy5ilX3l5CBDEpYSVyrZFPF1Z3x/OiouQHOppvoM1R/L/1pbczIQ
 MbomugiHQVqkw9wVw8Bfzh6rx8VAapsvPegnV9oseAHKS/0HObsfAFxNeCzahr7l
 OTPIPeTwSkJRS06pDItK/nPUucCLR7meAgWJ7Ts/FJEWZOrlEjJqfOK8JxB6rSL4
 uectlHC6irRjuAFyqT5eTRx0av8DevRiz15YTFHxXwqrQmaDFyns8IiRASDbi+sz
 FXP0caw9tD2eKwoJ9kIaqvHq15yxkfSA7UagqZbVa5uGZQtZ1leQQy0rHR9z807y
 5C9w5YoMH/UpbnPOtJNnBVx+u/XFD+o6bJx0tWRop9zhUnqY35vt+mcL2AbHr4/v
 TT0z8stoOAfTuBbMrIXY
 =hGeR
 -----END PGP SIGNATURE-----

Merge tag 'blackfin-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/realmz6/blackfin-linux

Pull blackfin updates from Steven Miao:
 "blackfin updates for Linux 3.11"

* tag 'blackfin-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/realmz6/blackfin-linux:
  smp: refine bf561 smpboot code
  bf609: stmmac: fix build after stmmac_mdio_bus_data changed
  bf609: add cpu revision 0.1
  bf609: rename bfin6xx_spi to bfin_spi3
  kgdb: blackfin: include irq_regs.h in kgdb.c
This commit is contained in:
Linus Torvalds 2013-07-10 10:12:58 -07:00
commit 49283f6020
6 changed files with 24 additions and 27 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
arch/blackfin/Kconfig
View file

@ -283,7 +283,7 @@ config BF_REV_0_0
config BF_REV_0_1
bool "0.1"
depends on (BF51x || BF52x || (BF54x && !BF54xM))
depends on (BF51x || BF52x || (BF54x && !BF54xM) || BF60x)
config BF_REV_0_2
bool "0.2"

4
arch/blackfin/include/asm/bfin6xx_spi.h → arch/blackfin/include/asm/bfin_spi3.h
View file

@ -240,7 +240,7 @@ struct bfin_spi_regs {
#define MAX_CTRL_CS 8 /* cs in spi controller */
/* device.platform_data for SSP controller devices */
struct bfin6xx_spi_master {
struct bfin_spi3_master {
u16 num_chipselect;
u16 pin_req[7];
};
@ -248,7 +248,7 @@ struct bfin6xx_spi_master {
/* spi_board_info.controller_data for SPI slave devices,
* copied to spi_device.platform_data ... mostly for dma tuning
*/
struct bfin6xx_spi_chip {
struct bfin_spi3_chip {
u32 control;
u16 cs_chg_udelay; /* Some devices require 16-bit delays */
u32 tx_dummy_val; /* tx value for rx only transfer */

1
arch/blackfin/kernel/kgdb.c
View file

@ -9,6 +9,7 @@
#include <linux/ptrace.h> /* for linux pt_regs struct */
#include <linux/kgdb.h>
#include <linux/uaccess.h>
#include <asm/irq_regs.h>
void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs)
{

7
arch/blackfin/mach-bf561/smp.c
View file

@ -69,7 +69,6 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
SSYNC();
/* We are done with local CPU inits, unblock the boot CPU. */
set_cpu_online(cpu, true);
spin_lock(&boot_lock);
spin_unlock(&boot_lock);
}
@ -91,7 +90,9 @@ int __cpuinit platform_boot_secondary(unsigned int cpu, struct task_struct *idle
SSYNC();
}
timeout = jiffies + 1 * HZ;
timeout = jiffies + HZ;
/* release the lock and let coreb run */
spin_unlock(&boot_lock);
while (time_before(jiffies, timeout)) {
if (cpu_online(cpu))
break;
@ -100,8 +101,6 @@ int __cpuinit platform_boot_secondary(unsigned int cpu, struct task_struct *idle
}
if (cpu_online(cpu)) {
/* release the lock and let coreb run */
spin_unlock(&boot_lock);
return 0;
} else
panic("CPU%u: processor failed to boot\n", cpu);

19
arch/blackfin/mach-bf609/boards/ezkit.c
View file

@ -17,7 +17,7 @@
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/usb/musb.h>
#include <asm/bfin6xx_spi.h>
#include <asm/bfin_spi3.h>
#include <asm/dma.h>
#include <asm/gpio.h>
#include <asm/nand.h>
@ -108,7 +108,6 @@ static struct platform_device bfin_rotary_device = {
static unsigned short pins[] = P_RMII0;
static struct stmmac_mdio_bus_data phy_private_data = {
.bus_id = 0,
.phy_mask = 1,
};
@ -745,13 +744,13 @@ static struct flash_platform_data bfin_spi_flash_data = {
.type = "w25q32",
};
static struct bfin6xx_spi_chip spi_flash_chip_info = {
static struct bfin_spi3_chip spi_flash_chip_info = {
.enable_dma = true, /* use dma transfer with this chip*/
};
#endif
#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
static struct bfin6xx_spi_chip spidev_chip_info = {
static struct bfin_spi3_chip spidev_chip_info = {
.enable_dma = true,
};
#endif
@ -1296,7 +1295,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
},
#endif
};
#if defined(CONFIG_SPI_BFIN6XX) || defined(CONFIG_SPI_BFIN6XX_MODULE)
#if IS_ENABLED(CONFIG_SPI_BFIN_V3)
/* SPI (0) */
static struct resource bfin_spi0_resource[] = {
{
@ -1337,13 +1336,13 @@ static struct resource bfin_spi1_resource[] = {
};
/* SPI controller data */
static struct bfin6xx_spi_master bf60x_spi_master_info0 = {
static struct bfin_spi3_master bf60x_spi_master_info0 = {
.num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
.pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
};
static struct platform_device bf60x_spi_master0 = {
.name = "bfin-spi",
.name = "bfin-spi3",
.id = 0, /* Bus number */
.num_resources = ARRAY_SIZE(bfin_spi0_resource),
.resource = bfin_spi0_resource,
@ -1352,13 +1351,13 @@ static struct platform_device bf60x_spi_master0 = {
},
};
static struct bfin6xx_spi_master bf60x_spi_master_info1 = {
static struct bfin_spi3_master bf60x_spi_master_info1 = {
.num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
.pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
};
static struct platform_device bf60x_spi_master1 = {
.name = "bfin-spi",
.name = "bfin-spi3",
.id = 1, /* Bus number */
.num_resources = ARRAY_SIZE(bfin_spi1_resource),
.resource = bfin_spi1_resource,
@ -1534,7 +1533,7 @@ static struct platform_device *ezkit_devices[] __initdata = {
&bfin_sdh_device,
#endif
#if defined(CONFIG_SPI_BFIN6XX) || defined(CONFIG_SPI_BFIN6XX_MODULE)
#if IS_ENABLED(CONFIG_SPI_BFIN_V3)
&bf60x_spi_master0,
&bf60x_spi_master1,
#endif

18
arch/blackfin/mach-common/smp.c
View file

@ -49,6 +49,7 @@ unsigned long blackfin_iflush_l1_entry[NR_CPUS];
struct blackfin_initial_pda __cpuinitdata initial_pda_coreb;
enum ipi_message_type {
BFIN_IPI_NONE,
BFIN_IPI_TIMER,
BFIN_IPI_RESCHEDULE,
BFIN_IPI_CALL_FUNC,
@ -72,8 +73,8 @@ static DEFINE_SPINLOCK(stop_lock);
/* Simple FIFO buffer, overflow leads to panic */
struct ipi_data {
unsigned long count;
unsigned long bits;
atomic_t count;
atomic_t bits;
};
static DEFINE_PER_CPU(struct ipi_data, bfin_ipi);
@ -146,7 +147,6 @@ static irqreturn_t ipi_handler_int1(int irq, void *dev_instance)
platform_clear_ipi(cpu, IRQ_SUPPLE_1);
bfin_ipi_data = &__get_cpu_var(bfin_ipi);
smp_mb();
while ((pending = xchg(&bfin_ipi_data->bits, 0)) != 0) {
msg = 0;
do {
@ -170,9 +170,8 @@ static irqreturn_t ipi_handler_int1(int irq, void *dev_instance)
ipi_cpu_stop(cpu);
break;
}
atomic_dec(&bfin_ipi_data->count);
} while (msg < BITS_PER_LONG);
smp_mb();
}
return IRQ_HANDLED;
}
@ -195,12 +194,10 @@ void send_ipi(const struct cpumask *cpumask, enum ipi_message_type msg)
unsigned long flags;
local_irq_save(flags);
smp_mb();
for_each_cpu(cpu, cpumask) {
bfin_ipi_data = &per_cpu(bfin_ipi, cpu);
smp_mb();
set_bit(msg, &bfin_ipi_data->bits);
bfin_ipi_data->count++;
atomic_set_mask((1 << msg), &bfin_ipi_data->bits);
atomic_inc(&bfin_ipi_data->count);
platform_send_ipi_cpu(cpu, IRQ_SUPPLE_1);
}
@ -319,7 +316,6 @@ void __cpuinit secondary_start_kernel(void)
setup_secondary(cpu);
platform_secondary_init(cpu);
/* setup local core timer */
bfin_local_timer_setup();
@ -335,6 +331,8 @@ void __cpuinit secondary_start_kernel(void)
*/
calibrate_delay();
/* We are done with local CPU inits, unblock the boot CPU. */
set_cpu_online(cpu, true);
cpu_startup_entry(CPUHP_ONLINE);
}