arm/tegra: pinmux: ioremap registers
Use ioremap to obtain access to registers instead of using static
mappings. This reduces the number of users of the static mappings, which
will eventually allow them to be removed.
Note that on Tegra30, the number of register "banks" will decrease to 2,
and the packing of specific bits into registers will change significantly.
That's why this change adds the "*_bank" fields to the pingroup tables,
rather than implementing some more hard-coded scheme.
Also, completely remove the implementation of suspend/resume; Tegra doesn't
yet support suspend/resume, and the implementation is complex for the
general pinmux driver:
* Not all registers are used within each bank, so we probably shouldn't
just iterate over every register in the bank, and save/restore it,
since that would mean touching undefined registers.
* Registers are shared between pingroups, so we can't simply iterate over
each pingroup, and save/restore the registers it uses.
It'd probably be best have probe() calculate a bitmask of actually-used
registers for each bank, and have suspend/resume iterate over those
bitmaps.
Oh, and Real Soon Now, I should be looking into converting this driver to
the new pinmux/pinctrl subsystem, so I didn't want to put too much work
into the current incarnation.
v2: s/space/bank/ to match comments on reg_* fields in pinmux.h.
Re-order bank/reg parameters to pg_readl/pg_writel.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Stephen Warren
Olof Johansson
parent
88d8951e58
commit
48f2eceefb
3 changed files with 123 additions and 94 deletions
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@ -199,6 +199,7 @@ struct tegra_drive_pingroup_config {
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struct tegra_drive_pingroup_desc {
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const char *name;
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s16 reg_bank;
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s16 reg;
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};
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@ -207,6 +208,9 @@ struct tegra_pingroup_desc {
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int funcs[4];
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int func_safe;
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int vddio;
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s16 tri_bank; /* Register bank the tri_reg exists within */
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s16 mux_bank; /* Register bank the mux_reg exists within */
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s16 pupd_bank; /* Register bank the pupd_reg exists within */
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s16 tri_reg; /* offset into the TRISTATE_REG_* register bank */
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s16 mux_reg; /* offset into the PIN_MUX_CTL_* register bank */
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s16 pupd_reg; /* offset into the PULL_UPDOWN_REG_* register bank */
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@ -31,10 +31,16 @@
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#include <mach/pinmux.h>
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#include <mach/suspend.h>
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#define TRISTATE_REG_A 0x14
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#define PIN_MUX_CTL_REG_A 0x80
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#define PULLUPDOWN_REG_A 0xa0
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#define PINGROUP_REG_A 0x868
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#define DRIVE_PINGROUP(pg_name, r) \
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[TEGRA_DRIVE_PINGROUP_ ## pg_name] = { \
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.name = #pg_name, \
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.reg = r \
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.reg_bank = 3, \
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.reg = ((r) - PINGROUP_REG_A) \
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}
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const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE_PINGROUP] = {
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@ -90,11 +96,14 @@ const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE
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TEGRA_MUX_ ## f3, \
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}, \
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.func_safe = TEGRA_MUX_ ## f_safe, \
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.tri_reg = tri_r, \
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.tri_bank = 0, \
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.tri_reg = ((tri_r) - TRISTATE_REG_A), \
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.tri_bit = tri_b, \
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.mux_reg = mux_r, \
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.mux_bank = 1, \
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.mux_reg = ((mux_r) - PIN_MUX_CTL_REG_A), \
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.mux_bit = mux_b, \
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.pupd_reg = pupd_r, \
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.pupd_bank = 2, \
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.pupd_reg = ((pupd_r) - PULLUPDOWN_REG_A), \
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.pupd_bit = pupd_b, \
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}
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@ -217,62 +226,3 @@ const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = {
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PINGROUP(XM2C, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xA8, 30),
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PINGROUP(XM2D, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xA8, 28),
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};
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#ifdef CONFIG_PM
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#define TRISTATE_REG_A 0x14
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#define TRISTATE_REG_NUM 4
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#define PIN_MUX_CTL_REG_A 0x80
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#define PIN_MUX_CTL_REG_NUM 8
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#define PULLUPDOWN_REG_A 0xa0
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#define PULLUPDOWN_REG_NUM 5
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static u32 pinmux_reg[TRISTATE_REG_NUM + PIN_MUX_CTL_REG_NUM +
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PULLUPDOWN_REG_NUM +
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ARRAY_SIZE(tegra_soc_drive_pingroups)];
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static inline unsigned long pg_readl(unsigned long offset)
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{
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return readl(IO_TO_VIRT(TEGRA_APB_MISC_BASE + offset));
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}
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static inline void pg_writel(unsigned long value, unsigned long offset)
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{
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writel(value, IO_TO_VIRT(TEGRA_APB_MISC_BASE + offset));
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}
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void tegra_pinmux_suspend(void)
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{
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unsigned int i;
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u32 *ctx = pinmux_reg;
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for (i = 0; i < PIN_MUX_CTL_REG_NUM; i++)
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*ctx++ = pg_readl(PIN_MUX_CTL_REG_A + i*4);
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for (i = 0; i < PULLUPDOWN_REG_NUM; i++)
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*ctx++ = pg_readl(PULLUPDOWN_REG_A + i*4);
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for (i = 0; i < TRISTATE_REG_NUM; i++)
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*ctx++ = pg_readl(TRISTATE_REG_A + i*4);
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for (i = 0; i < ARRAY_SIZE(tegra_soc_drive_pingroups); i++)
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*ctx++ = pg_readl(tegra_soc_drive_pingroups[i].reg);
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}
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void tegra_pinmux_resume(void)
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{
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unsigned int i;
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u32 *ctx = pinmux_reg;
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for (i = 0; i < PIN_MUX_CTL_REG_NUM; i++)
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pg_writel(*ctx++, PIN_MUX_CTL_REG_A + i*4);
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for (i = 0; i < PULLUPDOWN_REG_NUM; i++)
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pg_writel(*ctx++, PULLUPDOWN_REG_A + i*4);
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for (i = 0; i < TRISTATE_REG_NUM; i++)
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pg_writel(*ctx++, TRISTATE_REG_A + i*4);
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for (i = 0; i < ARRAY_SIZE(tegra_soc_drive_pingroups); i++)
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pg_writel(*ctx++, tegra_soc_drive_pingroups[i].reg);
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}
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#endif
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@ -170,15 +170,17 @@ static const char *pupd_name(unsigned long val)
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}
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}
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static int nbanks;
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static void __iomem **regs;
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static inline unsigned long pg_readl(unsigned long offset)
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static inline u32 pg_readl(u32 bank, u32 reg)
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{
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return readl(IO_TO_VIRT(TEGRA_APB_MISC_BASE + offset));
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return readl(regs[bank] + reg);
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}
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static inline void pg_writel(unsigned long value, unsigned long offset)
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static inline void pg_writel(u32 val, u32 bank, u32 reg)
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{
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writel(value, IO_TO_VIRT(TEGRA_APB_MISC_BASE + offset));
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writel(val, regs[bank] + reg);
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}
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static int tegra_pinmux_set_func(const struct tegra_pingroup_config *config)
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@ -218,10 +220,10 @@ static int tegra_pinmux_set_func(const struct tegra_pingroup_config *config)
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spin_lock_irqsave(&mux_lock, flags);
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reg = pg_readl(pingroups[pg].mux_reg);
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reg = pg_readl(pingroups[pg].mux_bank, pingroups[pg].mux_reg);
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reg &= ~(0x3 << pingroups[pg].mux_bit);
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reg |= mux << pingroups[pg].mux_bit;
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pg_writel(reg, pingroups[pg].mux_reg);
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pg_writel(reg, pingroups[pg].mux_bank, pingroups[pg].mux_reg);
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spin_unlock_irqrestore(&mux_lock, flags);
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@ -242,11 +244,11 @@ int tegra_pinmux_set_tristate(enum tegra_pingroup pg,
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spin_lock_irqsave(&mux_lock, flags);
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reg = pg_readl(pingroups[pg].tri_reg);
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reg = pg_readl(pingroups[pg].tri_bank, pingroups[pg].tri_reg);
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reg &= ~(0x1 << pingroups[pg].tri_bit);
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if (tristate)
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reg |= 1 << pingroups[pg].tri_bit;
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pg_writel(reg, pingroups[pg].tri_reg);
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pg_writel(reg, pingroups[pg].tri_bank, pingroups[pg].tri_reg);
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spin_unlock_irqrestore(&mux_lock, flags);
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@ -273,10 +275,10 @@ int tegra_pinmux_set_pullupdown(enum tegra_pingroup pg,
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spin_lock_irqsave(&mux_lock, flags);
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reg = pg_readl(pingroups[pg].pupd_reg);
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reg = pg_readl(pingroups[pg].pupd_bank, pingroups[pg].pupd_reg);
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reg &= ~(0x3 << pingroups[pg].pupd_bit);
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reg |= pupd << pingroups[pg].pupd_bit;
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pg_writel(reg, pingroups[pg].pupd_reg);
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pg_writel(reg, pingroups[pg].pupd_bank, pingroups[pg].pupd_reg);
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spin_unlock_irqrestore(&mux_lock, flags);
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@ -363,12 +365,12 @@ static int tegra_drive_pinmux_set_hsm(enum tegra_drive_pingroup pg,
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spin_lock_irqsave(&mux_lock, flags);
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reg = pg_readl(drive_pingroups[pg].reg);
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reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
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if (hsm == TEGRA_HSM_ENABLE)
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reg |= (1 << 2);
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else
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reg &= ~(1 << 2);
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pg_writel(reg, drive_pingroups[pg].reg);
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pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
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spin_unlock_irqrestore(&mux_lock, flags);
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@ -388,12 +390,12 @@ static int tegra_drive_pinmux_set_schmitt(enum tegra_drive_pingroup pg,
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spin_lock_irqsave(&mux_lock, flags);
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reg = pg_readl(drive_pingroups[pg].reg);
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reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
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if (schmitt == TEGRA_SCHMITT_ENABLE)
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reg |= (1 << 3);
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else
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reg &= ~(1 << 3);
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pg_writel(reg, drive_pingroups[pg].reg);
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pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
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spin_unlock_irqrestore(&mux_lock, flags);
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@ -413,10 +415,10 @@ static int tegra_drive_pinmux_set_drive(enum tegra_drive_pingroup pg,
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spin_lock_irqsave(&mux_lock, flags);
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reg = pg_readl(drive_pingroups[pg].reg);
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reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
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reg &= ~(0x3 << 4);
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reg |= drive << 4;
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pg_writel(reg, drive_pingroups[pg].reg);
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pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
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spin_unlock_irqrestore(&mux_lock, flags);
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@ -436,10 +438,10 @@ static int tegra_drive_pinmux_set_pull_down(enum tegra_drive_pingroup pg,
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spin_lock_irqsave(&mux_lock, flags);
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reg = pg_readl(drive_pingroups[pg].reg);
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reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
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reg &= ~(0x1f << 12);
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reg |= pull_down << 12;
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pg_writel(reg, drive_pingroups[pg].reg);
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pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
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spin_unlock_irqrestore(&mux_lock, flags);
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@ -459,10 +461,10 @@ static int tegra_drive_pinmux_set_pull_up(enum tegra_drive_pingroup pg,
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spin_lock_irqsave(&mux_lock, flags);
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reg = pg_readl(drive_pingroups[pg].reg);
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reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
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reg &= ~(0x1f << 12);
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reg |= pull_up << 12;
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pg_writel(reg, drive_pingroups[pg].reg);
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pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
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spin_unlock_irqrestore(&mux_lock, flags);
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@ -482,10 +484,10 @@ static int tegra_drive_pinmux_set_slew_rising(enum tegra_drive_pingroup pg,
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spin_lock_irqsave(&mux_lock, flags);
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reg = pg_readl(drive_pingroups[pg].reg);
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reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
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reg &= ~(0x3 << 28);
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reg |= slew_rising << 28;
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pg_writel(reg, drive_pingroups[pg].reg);
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pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
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spin_unlock_irqrestore(&mux_lock, flags);
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@ -505,10 +507,10 @@ static int tegra_drive_pinmux_set_slew_falling(enum tegra_drive_pingroup pg,
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spin_lock_irqsave(&mux_lock, flags);
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reg = pg_readl(drive_pingroups[pg].reg);
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reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
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reg &= ~(0x3 << 30);
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reg |= slew_falling << 30;
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pg_writel(reg, drive_pingroups[pg].reg);
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pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
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spin_unlock_irqrestore(&mux_lock, flags);
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@ -668,6 +670,74 @@ void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *co
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static int __devinit tegra_pinmux_probe(struct platform_device *pdev)
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{
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struct resource *res;
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int i;
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int config_bad = 0;
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for (i = 0; ; i++) {
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res = platform_get_resource(pdev, IORESOURCE_MEM, i);
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if (!res)
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break;
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}
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nbanks = i;
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for (i = 0; i < TEGRA_MAX_PINGROUP; i++) {
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if (pingroups[i].tri_bank >= nbanks) {
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dev_err(&pdev->dev, "pingroup %d: bad tri_bank\n", i);
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config_bad = 1;
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}
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if (pingroups[i].mux_bank >= nbanks) {
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dev_err(&pdev->dev, "pingroup %d: bad mux_bank\n", i);
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config_bad = 1;
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}
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if (pingroups[i].pupd_bank >= nbanks) {
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dev_err(&pdev->dev, "pingroup %d: bad pupd_bank\n", i);
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config_bad = 1;
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}
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}
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for (i = 0; i < TEGRA_MAX_DRIVE_PINGROUP; i++) {
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if (drive_pingroups[i].reg_bank >= nbanks) {
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dev_err(&pdev->dev,
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"drive pingroup %d: bad reg_bank\n", i);
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config_bad = 1;
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}
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}
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if (config_bad)
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return -ENODEV;
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regs = devm_kzalloc(&pdev->dev, nbanks * sizeof(*regs), GFP_KERNEL);
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if (!regs) {
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dev_err(&pdev->dev, "Can't alloc regs pointer\n");
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return -ENODEV;
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}
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for (i = 0; i < nbanks; i++) {
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res = platform_get_resource(pdev, IORESOURCE_MEM, i);
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if (!res) {
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dev_err(&pdev->dev, "Missing MEM resource\n");
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return -ENODEV;
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}
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if (!devm_request_mem_region(&pdev->dev, res->start,
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resource_size(res),
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dev_name(&pdev->dev))) {
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dev_err(&pdev->dev,
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"Couldn't request MEM resource %d\n", i);
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return -ENODEV;
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}
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regs[i] = devm_ioremap(&pdev->dev, res->start,
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resource_size(res));
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if (!regs) {
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dev_err(&pdev->dev, "Couldn't ioremap regs %d\n", i);
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return -ENODEV;
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}
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}
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return 0;
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}
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@ -710,6 +780,7 @@ static int dbg_pinmux_show(struct seq_file *s, void *unused)
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int len;
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for (i = 0; i < TEGRA_MAX_PINGROUP; i++) {
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unsigned long reg;
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unsigned long tri;
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unsigned long mux;
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unsigned long pupd;
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@ -722,8 +793,9 @@ static int dbg_pinmux_show(struct seq_file *s, void *unused)
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seq_printf(s, "TEGRA_MUX_NONE");
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len = strlen("NONE");
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} else {
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mux = (pg_readl(pingroups[i].mux_reg) >>
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pingroups[i].mux_bit) & 0x3;
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reg = pg_readl(pingroups[i].mux_bank,
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pingroups[i].mux_reg);
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mux = (reg >> pingroups[i].mux_bit) & 0x3;
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if (pingroups[i].funcs[mux] == TEGRA_MUX_RSVD) {
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seq_printf(s, "TEGRA_MUX_RSVD%1lu", mux+1);
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len = 5;
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@ -739,8 +811,9 @@ static int dbg_pinmux_show(struct seq_file *s, void *unused)
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seq_printf(s, "TEGRA_PUPD_NORMAL");
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len = strlen("NORMAL");
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} else {
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pupd = (pg_readl(pingroups[i].pupd_reg) >>
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pingroups[i].pupd_bit) & 0x3;
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reg = pg_readl(pingroups[i].pupd_bank,
|
||||
pingroups[i].pupd_reg);
|
||||
pupd = (reg >> pingroups[i].pupd_bit) & 0x3;
|
||||
seq_printf(s, "TEGRA_PUPD_%s", pupd_name(pupd));
|
||||
len = strlen(pupd_name(pupd));
|
||||
}
|
||||
|
|
@ -749,8 +822,9 @@ static int dbg_pinmux_show(struct seq_file *s, void *unused)
|
|||
if (pingroups[i].tri_reg < 0) {
|
||||
seq_printf(s, "TEGRA_TRI_NORMAL");
|
||||
} else {
|
||||
tri = (pg_readl(pingroups[i].tri_reg) >>
|
||||
pingroups[i].tri_bit) & 0x1;
|
||||
reg = pg_readl(pingroups[i].tri_bank,
|
||||
pingroups[i].tri_reg);
|
||||
tri = (reg >> pingroups[i].tri_bit) & 0x1;
|
||||
|
||||
seq_printf(s, "TEGRA_TRI_%s", tri_name(tri));
|
||||
}
|
||||
|
|
@ -785,7 +859,8 @@ static int dbg_drive_pinmux_show(struct seq_file *s, void *unused)
|
|||
dbg_pad_field(s, 7 - len);
|
||||
|
||||
|
||||
reg = pg_readl(drive_pingroups[i].reg);
|
||||
reg = pg_readl(drive_pingroups[i].reg_bank,
|
||||
drive_pingroups[i].reg);
|
||||
if (HSM_EN(reg)) {
|
||||
seq_printf(s, "TEGRA_HSM_ENABLE");
|
||||
len = 16;
|
||||
|
|
|
|||
Loading…
Reference in a new issue