V4L/DVB(7871): mxl5005s: Re-org code and update copyrights
Re-org code and update copyrights Signed-off-by: Steven Toth <stoth@hauppauge.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
This commit is contained in:
Steven Toth
Mauro Carvalho Chehab
parent
5c1b20514f
commit
48937295a6
2 changed files with 379 additions and 388 deletions
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@ -1,27 +1,62 @@
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/*
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* For the Realtek RTL chip RTL2831U
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* Realtek Release Date: 2008-03-14, ver 080314
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* Realtek version RTL2831 Linux driver version 080314
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* ver 080314
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*
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* for linux kernel version 2.6.21.4 - 2.6.22-14
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* support MXL5005s and MT2060 tuners (support tuner auto-detecting)
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* support two IR types -- RC5 and NEC
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*
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* Known boards with Realtek RTL chip RTL2821U
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* Freecom USB stick 14aa:0160 (version 4)
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* Conceptronic CTVDIGRCU
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*
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* Copyright (c) 2008 Realtek
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* Copyright (c) 2008 Jan Hoogenraad, Barnaby Shearer, Andy Hasper
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* This code is placed under the terms of the GNU General Public License
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*
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* Released by Realtek under GPLv2.
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* Thanks to Realtek for a lot of support we received !
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*
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* Revision: 080314 - original version
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*/
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MaxLinear MXL5005S VSB/QAM/DVBT tuner driver
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Copyright (C) 2008 MaxLinear
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Copyright (C) 2006 Steven Toth <stoth@hauppauge.com>
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Functions:
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mxl5005s_reset()
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mxl5005s_writereg()
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mxl5005s_writeregs()
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mxl5005s_init()
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mxl5005s_reconfigure()
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mxl5005s_AssignTunerMode()
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mxl5005s_set_params()
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mxl5005s_get_frequency()
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mxl5005s_get_bandwidth()
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mxl5005s_release()
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mxl5005s_attach()
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Copyright (c) 2008 Realtek
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Copyright (c) 2008 Jan Hoogenraad, Barnaby Shearer, Andy Hasper
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Functions:
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mxl5005s_SetRfFreqHz()
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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/*
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History of this driver (Steven Toth):
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I was given a public release of a linux driver that included
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support for the MaxLinear MXL5005S silicon tuner. Analysis of
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the tuner driver showed clearly three things.
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1. The tuner driver didn't support the LinuxTV tuner API
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so the code Realtek added had to be removed.
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2. A significant amount of the driver is reference driver code
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from MaxLinear, I felt it was important to identify and
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preserve this.
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3. New code has to be added to interface correctly with the
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LinuxTV API, as a regular kernel module.
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Other than the reference driver enum's, I've clearly marked
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sections of the code and retained the copyright of the
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respective owners.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/module.h>
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@ -31,10 +66,10 @@
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#include "dvb_frontend.h"
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#include "mxl5005s.h"
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static int debug;
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static int debug = 2;
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#define dprintk(level, arg...) do { \
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if (debug >= level) \
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if (level <= debug) \
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printk(arg); \
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} while (0)
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@ -50,13 +85,6 @@ static int debug;
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#define MXLCTRL_NUM 189
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#define MASTER_CONTROL_ADDR 9
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/* Enumeration of AGC Mode */
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typedef enum
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{
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MXL_DUAL_AGC = 0,
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MXL_SINGLE_AGC
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} AGC_Mode;
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/* Enumeration of Master Control Register State */
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typedef enum
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{
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@ -66,51 +94,6 @@ typedef enum
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MC_SEQ_OFF
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} Master_Control_State;
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/* Enumeration of MXL5005 Tuner Mode */
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typedef enum
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{
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MXL_ANALOG_MODE = 0,
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MXL_DIGITAL_MODE
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} Tuner_Mode;
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/* Enumeration of MXL5005 Tuner IF Mode */
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typedef enum
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{
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MXL_ZERO_IF = 0,
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MXL_LOW_IF
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} Tuner_IF_Mode;
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/* Enumeration of MXL5005 Tuner Clock Out Mode */
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typedef enum
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{
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MXL_CLOCK_OUT_DISABLE = 0,
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MXL_CLOCK_OUT_ENABLE
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} Tuner_Clock_Out;
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/* Enumeration of MXL5005 Tuner Div Out Mode */
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typedef enum
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{
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MXL_DIV_OUT_1 = 0,
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MXL_DIV_OUT_4
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} Tuner_Div_Out;
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/* Enumeration of MXL5005 Tuner Pull-up Cap Select Mode */
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typedef enum
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{
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MXL_CAP_SEL_DISABLE = 0,
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MXL_CAP_SEL_ENABLE
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} Tuner_Cap_Select;
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/* Enumeration of MXL5005 Tuner RSSI Mode */
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typedef enum
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{
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MXL_RSSI_DISABLE = 0,
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MXL_RSSI_ENABLE
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} Tuner_RSSI;
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/* Enumeration of MXL5005 Tuner Modulation Type */
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typedef enum
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{
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@ -122,22 +105,6 @@ typedef enum
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MXL_ANALOG_OTA
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} Tuner_Modu_Type;
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/* Enumeration of MXL5005 Tuner Tracking Filter Type */
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typedef enum
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{
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MXL_TF_DEFAULT = 0,
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MXL_TF_OFF,
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MXL_TF_C,
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MXL_TF_C_H,
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MXL_TF_D,
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MXL_TF_D_L,
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MXL_TF_E,
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MXL_TF_F,
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MXL_TF_E_2,
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MXL_TF_E_NA,
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MXL_TF_G
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} Tuner_TF_Type;
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/* MXL5005 Tuner Register Struct */
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typedef struct _TunerReg_struct
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{
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@ -268,33 +235,6 @@ enum
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};
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#define MXL5005S_BANDWIDTH_MODE_NUM 3
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/* Top modes */
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enum
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{
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MXL5005S_TOP_5P5 = 55,
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MXL5005S_TOP_7P2 = 72,
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MXL5005S_TOP_9P2 = 92,
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MXL5005S_TOP_11P0 = 110,
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MXL5005S_TOP_12P9 = 129,
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MXL5005S_TOP_14P7 = 147,
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MXL5005S_TOP_16P8 = 168,
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MXL5005S_TOP_19P4 = 194,
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MXL5005S_TOP_21P2 = 212,
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MXL5005S_TOP_23P2 = 232,
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MXL5005S_TOP_25P2 = 252,
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MXL5005S_TOP_27P1 = 271,
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MXL5005S_TOP_29P2 = 292,
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MXL5005S_TOP_31P7 = 317,
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MXL5005S_TOP_34P9 = 349,
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};
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/* IF output load */
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enum
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{
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MXL5005S_IF_OUTPUT_LOAD_200_OHM = 200,
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MXL5005S_IF_OUTPUT_LOAD_300_OHM = 300,
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};
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/* MXL5005 Tuner Control Struct */
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typedef struct _TunerControl_struct {
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u16 Ctrl_Num; /* Control Number */
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@ -349,13 +289,15 @@ struct mxl5005s_state
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TunerRegs[TUNER_REGS_NUM]; /* Tuner Register Array Pointer */
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/* Linux driver framework specific */
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const struct mxl5005s_config *config;
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struct mxl5005s_config *config;
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struct dvb_frontend *frontend;
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struct i2c_adapter *i2c;
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/* Cache values */
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u32 current_mode;
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};
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// funcs
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u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value);
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u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value);
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u16 MXL_GetMasterControl(u8 *MasterReg, int state);
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@ -372,14 +314,26 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq);
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void MXL_SynthIFLO_Calc(struct dvb_frontend *fe);
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void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe);
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u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, int *count);
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int mxl5005s_SetRegsWithTable(struct dvb_frontend *fe, u8 *pAddrTable, u8 *pByteTable, int TableLen);
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int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable, u8 *datatable, u8 len);
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u16 MXL_IFSynthInit(struct dvb_frontend *fe);
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static int mxl5005s_init2(struct dvb_frontend *fe);
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int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth);
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int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth);
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/* ----------------------------------------------------------------
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* Begin: Custom code salvaged from the Realtek driver.
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* Copyright (c) 2008 Realtek
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* Copyright (c) 2008 Jan Hoogenraad, Barnaby Shearer, Andy Hasper
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* This code is placed under the terms of the GNU General Public License
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*
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* Released by Realtek under GPLv2.
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* Thanks to Realtek for a lot of support we received !
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*
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* Revision: 080314 - original version
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*/
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int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz)
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{
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struct mxl5005s_state *state = fe->tuner_priv;
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u8 AgcMasterByte = state->config->AgcMasterByte;
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unsigned char AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
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unsigned char ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
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int TableLen;
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@ -396,7 +350,7 @@ int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz)
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AddrTable[0] = MASTER_CONTROL_ADDR;
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ByteTable[0] |= state->config->AgcMasterByte;
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mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, 1);
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mxl5005s_writeregs(fe, AddrTable, ByteTable, 1);
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// Tuner RF frequency setting stage 1
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MXL_TuneRF(fe, RfFreqHz);
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@ -410,13 +364,13 @@ int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz)
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MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START) ;
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AddrTable[TableLen] = MASTER_CONTROL_ADDR ;
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ByteTable[TableLen] = MasterControlByte | AgcMasterByte;
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ByteTable[TableLen] = MasterControlByte | state->config->AgcMasterByte;
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TableLen += 1;
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mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen);
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mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen);
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// Wait 30 ms.
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msleep(30);
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msleep(150);
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// Tuner RF frequency setting stage 2
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MXL_ControlWrite(fe, SEQ_FSM_PULSE, 1) ;
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@ -425,101 +379,21 @@ int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz)
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MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START) ;
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AddrTable[TableLen] = MASTER_CONTROL_ADDR ;
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ByteTable[TableLen] = MasterControlByte | AgcMasterByte ;
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ByteTable[TableLen] = MasterControlByte | state->config->AgcMasterByte ;
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TableLen += 1;
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mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen);
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mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen);
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msleep(100);
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return 0;
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}
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/* End: Custom code taken from the Realtek driver */
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/* Write a single byte to a single reg */
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static int mxl5005s_writereg(struct dvb_frontend *fe, u8 reg, u8 val)
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{
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struct mxl5005s_state *state = fe->tuner_priv;
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u8 buf[2] = { reg, val };
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struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0,
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.buf = buf, .len = 2 };
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if (i2c_transfer(state->i2c, &msg, 1) != 1) {
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printk(KERN_WARNING "mxl5005s I2C write failed\n");
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return -EREMOTEIO;
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}
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return 0;
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}
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/* Write a word to a single reg */
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static int mxl5005s_writereg16(struct dvb_frontend *fe, u8 reg, u16 val)
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{
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struct mxl5005s_state *state = fe->tuner_priv;
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u8 buf[3] = { reg, val >> 8 , val & 0xff };
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struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0,
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.buf = buf, .len = 3 };
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if (i2c_transfer(state->i2c, &msg, 1) != 1) {
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printk(KERN_WARNING "mxl5005s I2C write16 failed\n");
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return -EREMOTEIO;
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}
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return 0;
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}
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int mxl5005s_SetRegsWithTable(struct dvb_frontend *fe, u8 *pAddrTable, u8 *pByteTable, int TableLen)
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{
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int i, ret;
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u8 end_two_bytes_buf[]={ 0 , 0 };
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for( i = 0 ; i < TableLen - 1 ; i++)
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{
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ret = mxl5005s_writereg(fe, pAddrTable[i], pByteTable[i]);
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if (!ret)
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return ret;
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}
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end_two_bytes_buf[0] = pByteTable[i];
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end_two_bytes_buf[1] = MXL5005S_LATCH_BYTE;
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ret = mxl5005s_writereg16(fe, pAddrTable[i], (end_two_bytes_buf[0] << 8) | end_two_bytes_buf[1]);
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return ret;
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}
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int mxl5005s_SetRegMaskBits(struct dvb_frontend *fe,
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unsigned char RegAddr,
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unsigned char Msb,
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unsigned char Lsb,
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const unsigned char WritingValue
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)
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{
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int i;
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unsigned char Mask;
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unsigned char Shift;
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unsigned char RegByte;
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/* Generate mask and shift according to MSB and LSB. */
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Mask = 0;
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for(i = Lsb; i < (unsigned char)(Msb + 1); i++)
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Mask |= 0x1 << i;
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Shift = Lsb;
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/* Get tuner register byte according to register adddress. */
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MXL_RegRead(fe, RegAddr, &RegByte);
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/* Reserve register byte unmask bit with mask and inlay writing value into it. */
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RegByte &= ~Mask;
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RegByte |= (WritingValue << Shift) & Mask;
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/* Update tuner register byte table. */
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MXL_RegWrite(fe, RegAddr, RegByte);
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/* Write tuner register byte with writing byte. */
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return mxl5005s_SetRegsWithTable(fe, &RegAddr, &RegByte, 1);
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}
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// The following context is source code provided by MaxLinear.
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// MaxLinear source code - MXL5005_Initialize.cpp
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// DONE
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/* ----------------------------------------------------------------
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* Begin: Reference driver code found in the Realtek driver.
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* Copyright (c) 2008 MaxLinear
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*/
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u16 MXL5005_RegisterInit(struct dvb_frontend *fe)
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{
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struct mxl5005s_state *state = fe->tuner_priv;
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@ -841,7 +715,6 @@ u16 MXL5005_RegisterInit(struct dvb_frontend *fe)
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return 0 ;
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}
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// DONE
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u16 MXL5005_ControlInit(struct dvb_frontend *fe)
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{
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struct mxl5005s_state *state = fe->tuner_priv;
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@ -1785,7 +1658,6 @@ u16 MXL5005_ControlInit(struct dvb_frontend *fe)
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// MaxLinear source code - MXL5005_c.cpp
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// MXL5005.cpp : Defines the initialization routines for the DLL.
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// 2.6.12
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// DONE
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void InitTunerControls(struct dvb_frontend *fe)
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{
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MXL5005_RegisterInit(fe);
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@ -1828,7 +1700,6 @@ void InitTunerControls(struct dvb_frontend *fe)
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// > 0 : Failed //
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// //
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///////////////////////////////////////////////////////////////////////////////
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// DONE
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u16 MXL5005_TunerConfig(struct dvb_frontend *fe,
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u8 Mode, /* 0: Analog Mode ; 1: Digital Mode */
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u8 IF_mode, /* for Analog Mode, 0: zero IF; 1: low IF */
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@ -1898,7 +1769,6 @@ u16 MXL5005_TunerConfig(struct dvb_frontend *fe,
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// > 0 : Failed //
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// //
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///////////////////////////////////////////////////////////////////////////////
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// DONE
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void MXL_SynthIFLO_Calc(struct dvb_frontend *fe)
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{
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struct mxl5005s_state *state = fe->tuner_priv;
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@ -1937,7 +1807,6 @@ void MXL_SynthIFLO_Calc(struct dvb_frontend *fe)
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// > 0 : Failed //
|
||||
// //
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// DONE
|
||||
void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe)
|
||||
{
|
||||
struct mxl5005s_state *state = fe->tuner_priv;
|
||||
|
|
@ -1976,7 +1845,6 @@ void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe)
|
|||
// > 0 : Failed //
|
||||
// //
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// DONE
|
||||
u16 MXL_OverwriteICDefault(struct dvb_frontend *fe)
|
||||
{
|
||||
u16 status = 0;
|
||||
|
|
@ -2014,7 +1882,6 @@ u16 MXL_OverwriteICDefault(struct dvb_frontend *fe)
|
|||
// > 0 : Failed //
|
||||
// //
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// DONE
|
||||
u16 MXL_BlockInit(struct dvb_frontend *fe)
|
||||
{
|
||||
struct mxl5005s_state *state = fe->tuner_priv;
|
||||
|
|
@ -2042,6 +1909,7 @@ u16 MXL_BlockInit(struct dvb_frontend *fe)
|
|||
status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 2);
|
||||
break;
|
||||
case 6000000:
|
||||
printk("%s() doing 6MHz digital\n", __func__);
|
||||
status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 3);
|
||||
break;
|
||||
}
|
||||
|
|
@ -2072,7 +1940,6 @@ u16 MXL_BlockInit(struct dvb_frontend *fe)
|
|||
else /* Single AGC Mode Dig Ana */
|
||||
status += MXL_ControlWrite(fe, AGC_RF, state->Mode ? 15 : 12);
|
||||
|
||||
|
||||
if (state->TOP == 55) /* TOP == 5.5 */
|
||||
status += MXL_ControlWrite(fe, AGC_IF, 0x0);
|
||||
|
||||
|
|
@ -2302,6 +2169,8 @@ u16 MXL_BlockInit(struct dvb_frontend *fe)
|
|||
status += MXL_ControlWrite(fe, BB_IQSWAP, 0);
|
||||
else /* High IF */
|
||||
status += MXL_ControlWrite(fe, BB_IQSWAP, 1);
|
||||
status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 2);
|
||||
|
||||
}
|
||||
if (state->Mod_Type == MXL_ANALOG_CABLE) {
|
||||
/* Analog Cable Mode */
|
||||
|
|
@ -2338,7 +2207,7 @@ u16 MXL_BlockInit(struct dvb_frontend *fe)
|
|||
}
|
||||
|
||||
/* RSSI disable */
|
||||
if(state->EN_RSSI==0) {
|
||||
if(state->EN_RSSI == 0) {
|
||||
status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
|
||||
status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
|
||||
status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0);
|
||||
|
|
@ -2547,6 +2416,7 @@ u16 MXL_IFSynthInit(struct dvb_frontend *fe)
|
|||
Fref = 324000000UL ;
|
||||
}
|
||||
if (state->IF_LO == 5380000UL) {
|
||||
printk("%s() doing 5.38\n", __func__);
|
||||
status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ;
|
||||
status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ;
|
||||
Fref = 322800000UL ;
|
||||
|
|
@ -3229,6 +3099,7 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq)
|
|||
|
||||
if (state->TF_Type == MXL_TF_C_H) // Tracking Filter type C-H for Hauppauge only
|
||||
{
|
||||
printk("%s() CH filter\n", __func__);
|
||||
status += MXL_ControlWrite(fe, DAC_DIN_A, 0) ;
|
||||
|
||||
if (state->RF_IN >= 43000000 && state->RF_IN < 150000000)
|
||||
|
|
@ -3767,7 +3638,6 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq)
|
|||
return status ;
|
||||
}
|
||||
|
||||
// DONE
|
||||
u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val)
|
||||
{
|
||||
u16 status = 0;
|
||||
|
|
@ -3834,7 +3704,6 @@ u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val)
|
|||
// >0 : Value exceed maximum allowed for control number //
|
||||
// //
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// DONE
|
||||
u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value)
|
||||
{
|
||||
u16 status = 0;
|
||||
|
|
@ -3875,7 +3744,6 @@ u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value)
|
|||
// 2 : Control name not found //
|
||||
// //
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// DONE
|
||||
u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u16 controlGroup)
|
||||
{
|
||||
struct mxl5005s_state *state = fe->tuner_priv;
|
||||
|
|
@ -3982,7 +3850,6 @@ u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u
|
|||
// -1 : Invalid Register Address //
|
||||
// //
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// DONE
|
||||
u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal)
|
||||
{
|
||||
struct mxl5005s_state *state = fe->tuner_priv;
|
||||
|
|
@ -4022,7 +3889,6 @@ u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal)
|
|||
// -1 : Invalid Register Address //
|
||||
// //
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// DONE
|
||||
u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal)
|
||||
{
|
||||
struct mxl5005s_state *state = fe->tuner_priv;
|
||||
|
|
@ -4059,7 +3925,6 @@ u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal)
|
|||
// -1 : Invalid control name //
|
||||
// //
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// DONE
|
||||
u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value)
|
||||
{
|
||||
struct mxl5005s_state *state = fe->tuner_priv;
|
||||
|
|
@ -4131,7 +3996,6 @@ u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value)
|
|||
// -1 : Invalid control name //
|
||||
// //
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// DONE
|
||||
u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, u8 *RegNum, int * count)
|
||||
{
|
||||
struct mxl5005s_state *state = fe->tuner_priv;
|
||||
|
|
@ -4237,7 +4101,6 @@ u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, u8 *RegNum, int
|
|||
// NONE //
|
||||
// //
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// DONE
|
||||
void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal)
|
||||
{
|
||||
struct mxl5005s_state *state = fe->tuner_priv;
|
||||
|
|
@ -4285,7 +4148,6 @@ void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal)
|
|||
// Computed value //
|
||||
// //
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// DONE
|
||||
u32 MXL_Ceiling(u32 value, u32 resolution)
|
||||
{
|
||||
return (value/resolution + (value % resolution > 0 ? 1 : 0));
|
||||
|
|
@ -4294,7 +4156,6 @@ u32 MXL_Ceiling(u32 value, u32 resolution)
|
|||
//
|
||||
// Retrieve the Initialzation Registers
|
||||
//
|
||||
// DONE
|
||||
u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count)
|
||||
{
|
||||
u16 status = 0;
|
||||
|
|
@ -4317,7 +4178,6 @@ u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *c
|
|||
return status;
|
||||
}
|
||||
|
||||
// DONE
|
||||
u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count)
|
||||
{
|
||||
u16 status = 0;
|
||||
|
|
@ -4345,7 +4205,6 @@ u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *cou
|
|||
return status;
|
||||
}
|
||||
|
||||
// DONE
|
||||
u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count)
|
||||
{
|
||||
u16 status = 0;
|
||||
|
|
@ -4363,7 +4222,6 @@ u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, i
|
|||
return status;
|
||||
}
|
||||
|
||||
// DONE
|
||||
u16 MXL_GetCHRegister_LowIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count)
|
||||
{
|
||||
u16 status = 0;
|
||||
|
|
@ -4381,7 +4239,6 @@ u16 MXL_GetCHRegister_LowIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, in
|
|||
return status;
|
||||
}
|
||||
|
||||
// DONE
|
||||
u16 MXL_GetMasterControl(u8 *MasterReg, int state)
|
||||
{
|
||||
if (state == 1) /* Load_Start */
|
||||
|
|
@ -4526,7 +4383,6 @@ u16 MXL_VCORange_Test(struct dvb_frontend *fe, int VCO_Range)
|
|||
return status;
|
||||
}
|
||||
|
||||
// DONE
|
||||
u16 MXL_Hystersis_Test(struct dvb_frontend *fe, int Hystersis)
|
||||
{
|
||||
struct mxl5005s_state *state = fe->tuner_priv;
|
||||
|
|
@ -4537,87 +4393,206 @@ u16 MXL_Hystersis_Test(struct dvb_frontend *fe, int Hystersis)
|
|||
|
||||
return status;
|
||||
}
|
||||
|
||||
#endif
|
||||
/* End: Reference driver code found in the Realtek driver that
|
||||
* is copyright MaxLinear */
|
||||
|
||||
/* Linux driver related functions */
|
||||
/* ----------------------------------------------------------------
|
||||
* Begin: Everything after here is new code to adapt the
|
||||
* proprietary Realtek driver into a Linux API tuner.
|
||||
* Copyright (C) 2008 Steven Toth <stoth@hauppauge.com>
|
||||
*/
|
||||
static int mxl5005s_reset(struct dvb_frontend *fe)
|
||||
{
|
||||
struct mxl5005s_state *state = fe->tuner_priv;
|
||||
int ret = 0;
|
||||
|
||||
u8 buf[2] = { 0xff, 0x00 };
|
||||
struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0,
|
||||
.buf = buf, .len = 2 };
|
||||
|
||||
dprintk(2, "%s()\n", __func__);
|
||||
|
||||
if (fe->ops.i2c_gate_ctrl)
|
||||
fe->ops.i2c_gate_ctrl(fe, 1);
|
||||
|
||||
if (i2c_transfer(state->i2c, &msg, 1) != 1) {
|
||||
printk(KERN_WARNING "mxl5005s I2C reset failed\n");
|
||||
ret = -EREMOTEIO;
|
||||
}
|
||||
|
||||
if (fe->ops.i2c_gate_ctrl)
|
||||
fe->ops.i2c_gate_ctrl(fe, 0);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Write a single byte to a single reg, latch the value if required by
|
||||
* following the transaction with the latch byte.
|
||||
*/
|
||||
static int mxl5005s_writereg(struct dvb_frontend *fe, u8 reg, u8 val, int latch)
|
||||
{
|
||||
struct mxl5005s_state *state = fe->tuner_priv;
|
||||
u8 buf[3] = { reg, val, MXL5005S_LATCH_BYTE };
|
||||
struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0,
|
||||
.buf = buf, .len = 3 };
|
||||
|
||||
if (latch == 0)
|
||||
msg.len = 2;
|
||||
|
||||
dprintk(2, "%s(reg = 0x%x val = 0x%x addr = 0x%x)\n", __func__, reg, val, msg.addr);
|
||||
|
||||
if (i2c_transfer(state->i2c, &msg, 1) != 1) {
|
||||
printk(KERN_WARNING "mxl5005s I2C write failed\n");
|
||||
return -EREMOTEIO;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable, u8 *datatable, u8 len)
|
||||
{
|
||||
int ret = 0, i;
|
||||
|
||||
if (fe->ops.i2c_gate_ctrl)
|
||||
fe->ops.i2c_gate_ctrl(fe, 1);
|
||||
|
||||
for (i = 0 ; i < len-1; i++) {
|
||||
ret = mxl5005s_writereg(fe, addrtable[i], datatable[i], 0);
|
||||
if (ret < 0)
|
||||
break;
|
||||
}
|
||||
|
||||
ret = mxl5005s_writereg(fe, addrtable[i], datatable[i], 1);
|
||||
|
||||
if (fe->ops.i2c_gate_ctrl)
|
||||
fe->ops.i2c_gate_ctrl(fe, 0);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
int mxl5005s_init(struct dvb_frontend *fe)
|
||||
{
|
||||
int MxlModMode;
|
||||
int MxlIfMode;
|
||||
unsigned long MxlBandwitdh;
|
||||
unsigned long MxlIfFreqHz;
|
||||
unsigned long MxlCrystalFreqHz;
|
||||
int MxlAgcMode;
|
||||
unsigned short MxlTop;
|
||||
unsigned short MxlIfOutputLoad;
|
||||
int MxlClockOut;
|
||||
int MxlDivOut;
|
||||
int MxlCapSel;
|
||||
int MxlRssiOnOff;
|
||||
unsigned char MxlStandard;
|
||||
unsigned char MxlTfType;
|
||||
dprintk(1, "%s()\n", __func__);
|
||||
return mxl5005s_reconfigure(fe, MXL_QAM, MXL5005S_BANDWIDTH_6MHZ);
|
||||
}
|
||||
|
||||
int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth)
|
||||
{
|
||||
struct mxl5005s_state *state = fe->tuner_priv;
|
||||
|
||||
u8 AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
|
||||
u8 ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
|
||||
int TableLen;
|
||||
|
||||
dprintk(1, "%s(type=%d, bw=%d)\n", __func__, mod_type, bandwidth);
|
||||
|
||||
mxl5005s_reset(fe);
|
||||
|
||||
/* Tuner initialization stage 0 */
|
||||
MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET);
|
||||
AddrTable[0] = MASTER_CONTROL_ADDR;
|
||||
ByteTable[0] |= state->config->AgcMasterByte;
|
||||
|
||||
mxl5005s_writeregs(fe, AddrTable, ByteTable, 1);
|
||||
|
||||
mxl5005s_AssignTunerMode(fe, mod_type, bandwidth);
|
||||
|
||||
/* Tuner initialization stage 1 */
|
||||
MXL_GetInitRegister(fe, AddrTable, ByteTable, &TableLen);
|
||||
|
||||
mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth)
|
||||
{
|
||||
struct mxl5005s_state *state = fe->tuner_priv;
|
||||
struct mxl5005s_config *c = state->config;
|
||||
|
||||
InitTunerControls(fe);
|
||||
|
||||
/* Set MxL5005S parameters. */
|
||||
MxlModMode = MXL_DIGITAL_MODE;
|
||||
MxlIfMode = MXL_ZERO_IF;
|
||||
// steve
|
||||
//MxlBandwitdh = MXL5005S_BANDWIDTH_8MHZ;
|
||||
//MxlIfFreqHz = IF_FREQ_4570000HZ;
|
||||
MxlBandwitdh = MXL5005S_BANDWIDTH_6MHZ; // config
|
||||
MxlIfFreqHz = IF_FREQ_5380000HZ; // config
|
||||
MxlCrystalFreqHz = CRYSTAL_FREQ_16000000HZ; // config
|
||||
MxlAgcMode = MXL_SINGLE_AGC;
|
||||
MxlTop = MXL5005S_TOP_25P2;
|
||||
MxlIfOutputLoad = MXL5005S_IF_OUTPUT_LOAD_200_OHM;
|
||||
MxlClockOut = MXL_CLOCK_OUT_DISABLE;
|
||||
MxlDivOut = MXL_DIV_OUT_4;
|
||||
MxlCapSel = MXL_CAP_SEL_ENABLE;
|
||||
MxlRssiOnOff = MXL_RSSI_ENABLE; // config
|
||||
MxlTfType = MXL_TF_C_H; // config
|
||||
|
||||
MxlStandard = MXL_ATSC; // config
|
||||
|
||||
// TODO: this is bad, it trashes other configs
|
||||
// Set MxL5005S extra module.
|
||||
//pExtra->AgcMasterByte = (MxlAgcMode == MXL_DUAL_AGC) ? 0x4 : 0x0;
|
||||
|
||||
MXL5005_TunerConfig(
|
||||
fe,
|
||||
(unsigned char)MxlModMode,
|
||||
(unsigned char)MxlIfMode,
|
||||
MxlBandwitdh,
|
||||
MxlIfFreqHz,
|
||||
MxlCrystalFreqHz,
|
||||
(unsigned char)MxlAgcMode,
|
||||
MxlTop,
|
||||
MxlIfOutputLoad,
|
||||
(unsigned char)MxlClockOut,
|
||||
(unsigned char)MxlDivOut,
|
||||
(unsigned char)MxlCapSel,
|
||||
(unsigned char)MxlRssiOnOff,
|
||||
MxlStandard, MxlTfType);
|
||||
c->mod_mode,
|
||||
c->if_mode,
|
||||
bandwidth,
|
||||
c->if_freq,
|
||||
c->xtal_freq,
|
||||
c->agc_mode,
|
||||
c->top,
|
||||
c->output_load,
|
||||
c->clock_out,
|
||||
c->div_out,
|
||||
c->cap_select,
|
||||
c->rssi_enable,
|
||||
mod_type,
|
||||
c->tracking_filter);
|
||||
|
||||
return mxl5005s_init2(fe);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mxl5005s_set_params(struct dvb_frontend *fe,
|
||||
struct dvb_frontend_parameters *params)
|
||||
{
|
||||
u32 freq;
|
||||
u32 bw;
|
||||
struct mxl5005s_state *state = fe->tuner_priv;
|
||||
u32 req_mode, req_bw = 0;
|
||||
int ret;
|
||||
|
||||
if (fe->ops.info.type == FE_OFDM)
|
||||
bw = params->u.ofdm.bandwidth;
|
||||
else
|
||||
bw = MXL5005S_BANDWIDTH_6MHZ;
|
||||
dprintk(1, "%s()\n", __func__);
|
||||
|
||||
freq = params->frequency; /* Hz */
|
||||
dprintk(1, "%s() freq=%d bw=%d\n", __func__, freq, bw);
|
||||
if (fe->ops.info.type == FE_ATSC) {
|
||||
switch (params->u.vsb.modulation) {
|
||||
case VSB_8:
|
||||
req_mode = MXL_ATSC; break;
|
||||
default:
|
||||
case QAM_64:
|
||||
case QAM_256:
|
||||
case QAM_AUTO:
|
||||
req_mode = MXL_QAM; break;
|
||||
}
|
||||
}
|
||||
else req_mode = MXL_DVBT;
|
||||
|
||||
return mxl5005s_SetRfFreqHz(fe, freq);
|
||||
/* Change tuner for new modulation type if reqd */
|
||||
if (req_mode != state->current_mode) {
|
||||
switch (req_mode) {
|
||||
case VSB_8:
|
||||
case QAM_64:
|
||||
case QAM_256:
|
||||
case QAM_AUTO:
|
||||
req_bw = MXL5005S_BANDWIDTH_6MHZ;
|
||||
break;
|
||||
default:
|
||||
/* Assume DVB-T */
|
||||
switch (params->u.ofdm.bandwidth) {
|
||||
case BANDWIDTH_6_MHZ:
|
||||
req_bw = MXL5005S_BANDWIDTH_6MHZ;
|
||||
break;
|
||||
case BANDWIDTH_7_MHZ:
|
||||
req_bw = MXL5005S_BANDWIDTH_7MHZ;
|
||||
break;
|
||||
case BANDWIDTH_AUTO:
|
||||
case BANDWIDTH_8_MHZ:
|
||||
req_bw = MXL5005S_BANDWIDTH_8MHZ;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
state->current_mode = req_mode;
|
||||
ret = mxl5005s_reconfigure(fe, req_mode, req_bw);
|
||||
|
||||
} else
|
||||
ret = 0;
|
||||
|
||||
if (ret == 0) {
|
||||
dprintk(1, "%s() freq=%d\n", __func__, params->frequency);
|
||||
ret = mxl5005s_SetRfFreqHz(fe, params->frequency);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int mxl5005s_get_frequency(struct dvb_frontend *fe, u32 *frequency)
|
||||
|
|
@ -4640,42 +4615,6 @@ static int mxl5005s_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int mxl5005s_get_status(struct dvb_frontend *fe, u32 *status)
|
||||
{
|
||||
dprintk(1, "%s()\n", __func__);
|
||||
|
||||
*status = 0;
|
||||
// *status = TUNER_STATUS_LOCKED;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mxl5005s_init2(struct dvb_frontend *fe)
|
||||
{
|
||||
struct mxl5005s_state *state = fe->tuner_priv;
|
||||
u8 AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
|
||||
u8 ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
|
||||
int TableLen;
|
||||
|
||||
dprintk(1, "%s()\n", __func__);
|
||||
|
||||
/* Initialize MxL5005S tuner according to MxL5005S tuner example code. */
|
||||
|
||||
/* Tuner initialization stage 0 */
|
||||
MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET);
|
||||
AddrTable[0] = MASTER_CONTROL_ADDR;
|
||||
ByteTable[0] |= state->config->AgcMasterByte;
|
||||
|
||||
mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, 1);
|
||||
|
||||
/* Tuner initialization stage 1 */
|
||||
MXL_GetInitRegister(fe, AddrTable, ByteTable, &TableLen);
|
||||
|
||||
mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mxl5005s_release(struct dvb_frontend *fe)
|
||||
{
|
||||
dprintk(1, "%s()\n", __func__);
|
||||
|
|
@ -4698,7 +4637,6 @@ static const struct dvb_tuner_ops mxl5005s_tuner_ops = {
|
|||
.set_params = mxl5005s_set_params,
|
||||
.get_frequency = mxl5005s_get_frequency,
|
||||
.get_bandwidth = mxl5005s_get_bandwidth,
|
||||
.get_status = mxl5005s_get_status
|
||||
};
|
||||
|
||||
struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe,
|
||||
|
|
@ -4715,6 +4653,7 @@ struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe,
|
|||
state->frontend = fe;
|
||||
state->config = config;
|
||||
state->i2c = i2c;
|
||||
state->current_mode = MXL_QAM;
|
||||
|
||||
printk(KERN_INFO "MXL5005S: Attached at address 0x%02x\n", config->i2c_address);
|
||||
|
||||
|
|
@ -4726,8 +4665,5 @@ struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe,
|
|||
EXPORT_SYMBOL(mxl5005s_attach);
|
||||
|
||||
MODULE_DESCRIPTION("MaxLinear MXL5005S silicon tuner driver");
|
||||
MODULE_AUTHOR("Jan Hoogenraad");
|
||||
MODULE_AUTHOR("Barnaby Shearer");
|
||||
MODULE_AUTHOR("Andy Hasper");
|
||||
MODULE_AUTHOR("Steven Toth");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
|
|
|||
|
|
@ -1,63 +1,118 @@
|
|||
/*
|
||||
* For the Realtek RTL chip RTL2831U
|
||||
* Realtek Release Date: 2008-03-14, ver 080314
|
||||
* Realtek version RTL2831 Linux driver version 080314
|
||||
* ver 080314
|
||||
*
|
||||
* for linux kernel version 2.6.21.4 - 2.6.22-14
|
||||
* support MXL5005s and MT2060 tuners (support tuner auto-detecting)
|
||||
* support two IR types -- RC5 and NEC
|
||||
*
|
||||
* Known boards with Realtek RTL chip RTL2821U
|
||||
* Freecom USB stick 14aa:0160 (version 4)
|
||||
* Conceptronic CTVDIGRCU
|
||||
*
|
||||
* Copyright (c) 2008 Realtek
|
||||
* Copyright (c) 2008 Jan Hoogenraad, Barnaby Shearer, Andy Hasper
|
||||
* This code is placed under the terms of the GNU General Public License
|
||||
*
|
||||
* Released by Realtek under GPLv2.
|
||||
* Thanks to Realtek for a lot of support we received !
|
||||
*
|
||||
* Revision: 080314 - original version
|
||||
*/
|
||||
MaxLinear MXL5005S VSB/QAM/DVBT tuner driver
|
||||
|
||||
Copyright (C) 2008 MaxLinear
|
||||
Copyright (C) 2008 Steven Toth <stoth@hauppauge.com>
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
|
||||
*/
|
||||
|
||||
#ifndef __MXL5005S_H
|
||||
#define __MXL5005S_H
|
||||
|
||||
#include <linux/dvb/frontend.h>
|
||||
|
||||
/* IF frequency */
|
||||
enum IF_FREQ_HZ
|
||||
{
|
||||
IF_FREQ_4570000HZ = 4570000, ///< IF frequency = 4.57 MHz
|
||||
IF_FREQ_4571429HZ = 4571429, ///< IF frequency = 4.571 MHz
|
||||
IF_FREQ_5380000HZ = 5380000, ///< IF frequency = 5.38 MHz
|
||||
IF_FREQ_36000000HZ = 36000000, ///< IF frequency = 36.000 MHz
|
||||
IF_FREQ_36125000HZ = 36125000, ///< IF frequency = 36.125 MHz
|
||||
IF_FREQ_36166667HZ = 36166667, ///< IF frequency = 36.167 MHz
|
||||
IF_FREQ_44000000HZ = 44000000, ///< IF frequency = 44.000 MHz
|
||||
};
|
||||
|
||||
/* Crystal frequency */
|
||||
enum CRYSTAL_FREQ_HZ
|
||||
{
|
||||
CRYSTAL_FREQ_4000000HZ = 4000000, ///< Crystal frequency = 4.0 MHz
|
||||
CRYSTAL_FREQ_16000000HZ = 16000000, ///< Crystal frequency = 16.0 MHz
|
||||
CRYSTAL_FREQ_25000000HZ = 25000000, ///< Crystal frequency = 25.0 MHz
|
||||
CRYSTAL_FREQ_28800000HZ = 28800000, ///< Crystal frequency = 28.8 MHz
|
||||
};
|
||||
|
||||
struct mxl5005s_config
|
||||
{
|
||||
/* 7 bit i2c address */
|
||||
u8 i2c_address;
|
||||
|
||||
#define IF_FREQ_4570000HZ 4570000
|
||||
#define IF_FREQ_4571429HZ 4571429
|
||||
#define IF_FREQ_5380000HZ 5380000
|
||||
#define IF_FREQ_36000000HZ 36000000
|
||||
#define IF_FREQ_36125000HZ 36125000
|
||||
#define IF_FREQ_36166667HZ 36166667
|
||||
#define IF_FREQ_44000000HZ 44000000
|
||||
u32 if_freq;
|
||||
|
||||
#define CRYSTAL_FREQ_4000000HZ 4000000
|
||||
#define CRYSTAL_FREQ_16000000HZ 16000000
|
||||
#define CRYSTAL_FREQ_25000000HZ 25000000
|
||||
#define CRYSTAL_FREQ_28800000HZ 28800000
|
||||
u32 xtal_freq;
|
||||
|
||||
#define MXL_DUAL_AGC 0
|
||||
#define MXL_SINGLE_AGC 1
|
||||
u8 agc_mode;
|
||||
|
||||
#define MXL_TF_DEFAULT 0
|
||||
#define MXL_TF_OFF 1
|
||||
#define MXL_TF_C 2
|
||||
#define MXL_TF_C_H 3
|
||||
#define MXL_TF_D 4
|
||||
#define MXL_TF_D_L 5
|
||||
#define MXL_TF_E 6
|
||||
#define MXL_TF_F 7
|
||||
#define MXL_TF_E_2 8
|
||||
#define MXL_TF_E_NA 9
|
||||
#define MXL_TF_G 10
|
||||
u8 tracking_filter;
|
||||
|
||||
#define MXL_RSSI_DISABLE 0
|
||||
#define MXL_RSSI_ENABLE 1
|
||||
u8 rssi_enable;
|
||||
|
||||
#define MXL_CAP_SEL_DISABLE 0
|
||||
#define MXL_CAP_SEL_ENABLE 1
|
||||
u8 cap_select;
|
||||
|
||||
#define MXL_DIV_OUT_1 0
|
||||
#define MXL_DIV_OUT_4 1
|
||||
u8 div_out;
|
||||
|
||||
#define MXL_CLOCK_OUT_DISABLE 0
|
||||
#define MXL_CLOCK_OUT_ENABLE 1
|
||||
u8 clock_out;
|
||||
|
||||
#define MXL5005S_IF_OUTPUT_LOAD_200_OHM 200
|
||||
#define MXL5005S_IF_OUTPUT_LOAD_300_OHM 300
|
||||
u32 output_load;
|
||||
|
||||
#define MXL5005S_TOP_5P5 55
|
||||
#define MXL5005S_TOP_7P2 72
|
||||
#define MXL5005S_TOP_9P2 92
|
||||
#define MXL5005S_TOP_11P0 110
|
||||
#define MXL5005S_TOP_12P9 129
|
||||
#define MXL5005S_TOP_14P7 147
|
||||
#define MXL5005S_TOP_16P8 168
|
||||
#define MXL5005S_TOP_19P4 194
|
||||
#define MXL5005S_TOP_21P2 212
|
||||
#define MXL5005S_TOP_23P2 232
|
||||
#define MXL5005S_TOP_25P2 252
|
||||
#define MXL5005S_TOP_27P1 271
|
||||
#define MXL5005S_TOP_29P2 292
|
||||
#define MXL5005S_TOP_31P7 317
|
||||
#define MXL5005S_TOP_34P9 349
|
||||
u32 top;
|
||||
|
||||
#define MXL_ANALOG_MODE 0
|
||||
#define MXL_DIGITAL_MODE 1
|
||||
u8 mod_mode;
|
||||
|
||||
#define MXL_ZERO_IF 0
|
||||
#define MXL_LOW_IF 1
|
||||
u8 if_mode;
|
||||
|
||||
/* Stuff I don't know what to do with */
|
||||
u8 AgcMasterByte;
|
||||
};
|
||||
|
||||
#if defined(CONFIG_MEDIA_TUNER_MXL5005S) || (defined(CONFIG_MEDIA_TUNER_MXL5005S_MODULE) && defined(MODULE))
|
||||
#if defined(CONFIG_MEDIA_TUNER_MXL5005S) || \
|
||||
(defined(CONFIG_MEDIA_TUNER_MXL5005S_MODULE) && defined(MODULE))
|
||||
extern struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe,
|
||||
struct i2c_adapter *i2c,
|
||||
struct mxl5005s_config *config);
|
||||
|
|
|
|||
Loading…
Reference in a new issue