Merge branch 'drm-intel-fixes' into drm-intel-next
Apply the trivial conflicting regression fixes, but keep GPU semaphores enabled. Conflicts: drivers/gpu/drm/i915/i915_drv.h drivers/gpu/drm/i915/i915_gem_execbuffer.c
This commit is contained in:
Chris Wilson
commit
47ae63e0c2
9 changed files with 70 additions and 40 deletions
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@ -873,7 +873,7 @@ static int i915_cur_delayinfo(struct seq_file *m, void *unused)
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int max_freq;
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/* RPSTAT1 is in the GT power well */
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__gen6_force_wake_get(dev_priv);
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__gen6_gt_force_wake_get(dev_priv);
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rpstat = I915_READ(GEN6_RPSTAT1);
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rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
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@ -918,7 +918,7 @@ static int i915_cur_delayinfo(struct seq_file *m, void *unused)
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seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
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max_freq * 100);
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__gen6_force_wake_put(dev_priv);
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__gen6_gt_force_wake_put(dev_priv);
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} else {
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seq_printf(m, "no P-state info available\n");
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}
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@ -49,6 +49,9 @@ module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
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unsigned int i915_powersave = 1;
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module_param_named(powersave, i915_powersave, int, 0600);
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unsigned int i915_semaphores = 1;
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module_param_named(semaphores, i915_semaphores, int, 0600);
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unsigned int i915_enable_rc6 = 0;
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module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600);
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@ -260,7 +263,7 @@ void intel_detect_pch (struct drm_device *dev)
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}
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}
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void __gen6_force_wake_get(struct drm_i915_private *dev_priv)
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void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
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{
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int count;
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@ -276,12 +279,22 @@ void __gen6_force_wake_get(struct drm_i915_private *dev_priv)
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udelay(10);
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}
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void __gen6_force_wake_put(struct drm_i915_private *dev_priv)
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void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
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{
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I915_WRITE_NOTRACE(FORCEWAKE, 0);
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POSTING_READ(FORCEWAKE);
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}
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void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
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{
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int loop = 500;
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u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
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while (fifo < 20 && loop--) {
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udelay(10);
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fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
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}
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}
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static int i915_drm_freeze(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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@ -961,6 +961,7 @@ extern int i915_max_ioctl;
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extern unsigned int i915_fbpercrtc;
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extern int i915_panel_ignore_lid;
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extern unsigned int i915_powersave;
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extern unsigned int i915_semaphores;
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extern unsigned int i915_lvds_downclock;
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extern unsigned int i915_panel_use_ssc;
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extern int i915_vbt_sdvo_panel_type;
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@ -1172,6 +1173,9 @@ void i915_gem_detach_phys_object(struct drm_device *dev,
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void i915_gem_free_all_phys_object(struct drm_device *dev);
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void i915_gem_release(struct drm_device *dev, struct drm_file *file);
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uint32_t
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i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object *obj);
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/* i915_gem_gtt.c */
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void i915_gem_restore_gtt_mappings(struct drm_device *dev);
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int __must_check i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj);
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@ -1348,20 +1352,29 @@ __i915_write(64, q)
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* must be set to prevent GT core from power down and stale values being
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* returned.
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*/
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void __gen6_force_wake_get(struct drm_i915_private *dev_priv);
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void __gen6_force_wake_put (struct drm_i915_private *dev_priv);
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static inline u32 i915_safe_read(struct drm_i915_private *dev_priv, u32 reg)
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void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
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void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
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void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
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static inline u32 i915_gt_read(struct drm_i915_private *dev_priv, u32 reg)
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{
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u32 val;
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if (dev_priv->info->gen >= 6) {
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__gen6_force_wake_get(dev_priv);
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__gen6_gt_force_wake_get(dev_priv);
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val = I915_READ(reg);
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__gen6_force_wake_put(dev_priv);
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__gen6_gt_force_wake_put(dev_priv);
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} else
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val = I915_READ(reg);
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return val;
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}
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static inline void i915_gt_write(struct drm_i915_private *dev_priv,
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u32 reg, u32 val)
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{
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if (dev_priv->info->gen >= 6)
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__gen6_gt_wait_for_fifo(dev_priv);
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I915_WRITE(reg, val);
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}
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#endif
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@ -1404,7 +1404,7 @@ i915_gem_get_gtt_alignment(struct drm_i915_gem_object *obj)
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* Return the required GTT alignment for an object, only taking into account
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* unfenced tiled surface requirements.
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*/
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static uint32_t
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uint32_t
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i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object *obj)
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{
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struct drm_device *dev = obj->base.dev;
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@ -748,7 +748,8 @@ i915_gem_execbuffer_sync_rings(struct drm_i915_gem_object *obj,
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if (from == NULL || to == from)
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return 0;
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if (INTEL_INFO(obj->base.dev)->gen < 6)
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/* XXX gpu semaphores are implicated in various hard hangs on SNB */
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if (INTEL_INFO(obj->base.dev)->gen < 6 || !i915_semaphores)
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return i915_gem_object_wait_rendering(obj);
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idx = intel_ring_sync_index(from, to);
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@ -184,7 +184,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
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static bool
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i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
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{
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int tile_width, tile_height;
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int tile_width;
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/* Linear is always fine */
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if (tiling_mode == I915_TILING_NONE)
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@ -215,20 +215,6 @@ i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
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}
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}
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if (IS_GEN2(dev) ||
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(tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)))
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tile_height = 32;
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else
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tile_height = 8;
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/* i8xx is strange: It has 2 interleaved rows of tiles, so needs an even
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* number of tile rows. */
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if (IS_GEN2(dev))
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tile_height *= 2;
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/* Size needs to be aligned to a full tile row */
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if (size & (tile_height * stride - 1))
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return false;
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/* 965+ just needs multiples of tile width */
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if (INTEL_INFO(dev)->gen >= 4) {
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if (stride & (tile_width - 1))
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@ -298,6 +284,7 @@ i915_gem_set_tiling(struct drm_device *dev, void *data,
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struct drm_i915_gem_set_tiling *args = data;
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drm_i915_private_t *dev_priv = dev->dev_private;
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struct drm_i915_gem_object *obj;
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int ret = 0;
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obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
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if (&obj->base == NULL)
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@ -358,14 +345,27 @@ i915_gem_set_tiling(struct drm_device *dev, void *data,
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(obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end &&
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i915_gem_object_fence_ok(obj, args->tiling_mode));
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obj->tiling_changed = true;
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obj->tiling_mode = args->tiling_mode;
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obj->stride = args->stride;
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/* Rebind if we need a change of alignment */
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if (!obj->map_and_fenceable) {
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u32 unfenced_alignment =
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i915_gem_get_unfenced_gtt_alignment(obj);
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if (obj->gtt_offset & (unfenced_alignment - 1))
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ret = i915_gem_object_unbind(obj);
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}
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if (ret == 0) {
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obj->tiling_changed = true;
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obj->tiling_mode = args->tiling_mode;
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obj->stride = args->stride;
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}
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}
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/* we have to maintain this existing ABI... */
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args->stride = obj->stride;
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args->tiling_mode = obj->tiling_mode;
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drm_gem_object_unreference(&obj->base);
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mutex_unlock(&dev->struct_mutex);
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return 0;
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return ret;
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}
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/**
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@ -3318,6 +3318,8 @@
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#define FORCEWAKE 0xA18C
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#define FORCEWAKE_ACK 0x130090
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#define GT_FIFO_FREE_ENTRIES 0x120008
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#define GEN6_RPNSWREQ 0xA008
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#define GEN6_TURBO_DISABLE (1<<31)
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#define GEN6_FREQUENCY(x) ((x)<<25)
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@ -1825,7 +1825,7 @@ static void sandybridge_blit_fbc_update(struct drm_device *dev)
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u32 blt_ecoskpd;
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/* Make sure blitter notifies FBC of writes */
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__gen6_force_wake_get(dev_priv);
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__gen6_gt_force_wake_get(dev_priv);
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blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
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blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
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GEN6_BLITTER_LOCK_SHIFT;
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@ -1836,7 +1836,7 @@ static void sandybridge_blit_fbc_update(struct drm_device *dev)
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GEN6_BLITTER_LOCK_SHIFT);
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I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
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POSTING_READ(GEN6_BLITTER_ECOSKPD);
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__gen6_force_wake_put(dev_priv);
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__gen6_gt_force_wake_put(dev_priv);
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}
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static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
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@ -6856,7 +6856,7 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv)
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* userspace...
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*/
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I915_WRITE(GEN6_RC_STATE, 0);
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__gen6_force_wake_get(dev_priv);
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__gen6_gt_force_wake_get(dev_priv);
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/* disable the counters and set deterministic thresholds */
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I915_WRITE(GEN6_RC_CONTROL, 0);
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@ -6954,7 +6954,7 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv)
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/* enable all PM interrupts */
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I915_WRITE(GEN6_PMINTRMSK, 0);
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__gen6_force_wake_put(dev_priv);
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__gen6_gt_force_wake_put(dev_priv);
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}
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void intel_enable_clock_gating(struct drm_device *dev)
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@ -14,22 +14,23 @@ struct intel_hw_status_page {
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struct drm_i915_gem_object *obj;
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};
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#define I915_RING_READ(reg) i915_safe_read(dev_priv, reg)
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#define I915_RING_READ(reg) i915_gt_read(dev_priv, reg)
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#define I915_RING_WRITE(reg, val) i915_gt_write(dev_priv, reg, val)
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#define I915_READ_TAIL(ring) I915_RING_READ(RING_TAIL((ring)->mmio_base))
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#define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)
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#define I915_WRITE_TAIL(ring, val) I915_RING_WRITE(RING_TAIL((ring)->mmio_base), val)
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#define I915_READ_START(ring) I915_RING_READ(RING_START((ring)->mmio_base))
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#define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)
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#define I915_WRITE_START(ring, val) I915_RING_WRITE(RING_START((ring)->mmio_base), val)
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#define I915_READ_HEAD(ring) I915_RING_READ(RING_HEAD((ring)->mmio_base))
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#define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)
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#define I915_WRITE_HEAD(ring, val) I915_RING_WRITE(RING_HEAD((ring)->mmio_base), val)
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#define I915_READ_CTL(ring) I915_RING_READ(RING_CTL((ring)->mmio_base))
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#define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)
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#define I915_WRITE_CTL(ring, val) I915_RING_WRITE(RING_CTL((ring)->mmio_base), val)
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#define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)
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#define I915_READ_IMR(ring) I915_RING_READ(RING_IMR((ring)->mmio_base))
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#define I915_WRITE_IMR(ring, val) I915_RING_WRITE(RING_IMR((ring)->mmio_base), val)
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#define I915_READ_NOPID(ring) I915_RING_READ(RING_NOPID((ring)->mmio_base))
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#define I915_READ_SYNC_0(ring) I915_RING_READ(RING_SYNC_0((ring)->mmio_base))
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