arm64: dts: hisi: add hns-dsaf cpld control for the hip07 SoC
Add cpld-syscon node to support the cpld control for hns-dsaf on the hip07 SoC. Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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1 changed files with 8 additions and 0 deletions
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@ -1127,6 +1127,12 @@
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reg = <0x0 0xc0000000 0x0 0x10000>;
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reg = <0x0 0xc0000000 0x0 0x10000>;
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};
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};
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dsa_cpld: dsa_cpld@78000010 {
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compatible = "syscon";
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reg = <0x0 0x78000010 0x0 0x100>;
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reg-io-width = <2>;
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};
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pcie_subctl: pcie_subctl@a0000000 {
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pcie_subctl: pcie_subctl@a0000000 {
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compatible = "hisilicon,pcie-sas-subctrl", "syscon";
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compatible = "hisilicon,pcie-sas-subctrl", "syscon";
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reg = <0x0 0xa0000000 0x0 0x10000>;
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reg = <0x0 0xa0000000 0x0 0x10000>;
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@ -1258,6 +1264,7 @@
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port@0 {
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port@0 {
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reg = <0>;
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reg = <0>;
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serdes-syscon = <&serdes_ctrl>;
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serdes-syscon = <&serdes_ctrl>;
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cpld-syscon = <&dsa_cpld 0x0>;
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port-rst-offset = <0>;
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port-rst-offset = <0>;
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port-mode-offset = <0>;
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port-mode-offset = <0>;
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mc-mac-mask = [ff f0 00 00 00 00];
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mc-mac-mask = [ff f0 00 00 00 00];
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@ -1267,6 +1274,7 @@
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port@1 {
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port@1 {
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reg = <1>;
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reg = <1>;
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serdes-syscon= <&serdes_ctrl>;
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serdes-syscon= <&serdes_ctrl>;
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cpld-syscon = <&dsa_cpld 0x4>;
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port-rst-offset = <1>;
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port-rst-offset = <1>;
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port-mode-offset = <1>;
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port-mode-offset = <1>;
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mc-mac-mask = [ff f0 00 00 00 00];
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mc-mac-mask = [ff f0 00 00 00 00];
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