ixgbe: DCB, X540 devices do not respond to pause frames
DCB enabled X540 devices are not responding to pause frames due to a missing register set that was added for these devices that did not exist in other devices. Signed-off-by: John Fastabend <john.r.fastabend@intel.com> Tested-by: Ross Brattain <ross.b.brattain@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
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2 changed files with 9 additions and 2 deletions
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@ -301,12 +301,17 @@ s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, u8 pfc_en)
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IXGBE_WRITE_REG(hw, IXGBE_FCCFG, reg);
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/*
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* Enable Receive PFC
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* We will always honor XOFF frames we receive when
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* we are in PFC mode.
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* 82599 will always honor XOFF frames we receive when
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* we are in PFC mode however X540 only honors enabled
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* traffic classes.
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*/
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reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
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reg &= ~IXGBE_MFLCN_RFCE;
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reg |= IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_DPF;
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if (hw->mac.type == ixgbe_mac_X540)
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reg |= pfc_en << IXGBE_MFLCN_RPFCE_SHIFT;
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IXGBE_WRITE_REG(hw, IXGBE_MFLCN, reg);
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} else {
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@ -1728,6 +1728,8 @@
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#define IXGBE_MFLCN_RPFCE 0x00000004 /* Receive Priority FC Enable */
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#define IXGBE_MFLCN_RFCE 0x00000008 /* Receive FC Enable */
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#define IXGBE_MFLCN_RPFCE_SHIFT 4
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/* Multiple Receive Queue Control */
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#define IXGBE_MRQC_RSSEN 0x00000001 /* RSS Enable */
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#define IXGBE_MRQC_MRQE_MASK 0xF /* Bits 3:0 */
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