CRIS v10: Update drivers/gpio.c, fix locking and general improvements.
- Change all spin_lock/local_irq_save to spin_lock_irqsave. - Change multiple returns in functions where we have a lock to goto out. - Correct number of arguments to gpio_poll_timer_interrupt, gpio_pa_interrupt. - Break out gpio_write logic to smaller functions to make it readable. - In setget_input and setget_output, avoid extra if-indent level. - Change name LED_* -> CRIS_LED_* to avoid name clash. - Don't use braces around single statement ifs. - Fix whitespace errors. - Remove useless CVS id and log.
This commit is contained in:
Jesper Nilsson
parent
46aac058fe
commit
45a4127c10
1 changed files with 231 additions and 362 deletions
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@ -1,138 +1,11 @@
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/* $Id: gpio.c,v 1.17 2005/06/19 17:06:46 starvik Exp $
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*
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/*
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* Etrax general port I/O device
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*
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* Copyright (c) 1999, 2000, 2001, 2002 Axis Communications AB
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* Copyright (c) 1999-2007 Axis Communications AB
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*
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* Authors: Bjorn Wesen (initial version)
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* Ola Knutsson (LED handling)
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* Johan Adolfsson (read/set directions, write, port G)
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*
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* $Log: gpio.c,v $
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* Revision 1.17 2005/06/19 17:06:46 starvik
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* Merge of Linux 2.6.12.
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*
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* Revision 1.16 2005/03/07 13:02:29 starvik
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* Protect driver global states with spinlock
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*
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* Revision 1.15 2005/01/05 06:08:55 starvik
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* No need to do local_irq_disable after local_irq_save.
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*
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* Revision 1.14 2004/12/13 12:21:52 starvik
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* Added I/O and DMA allocators from Linux 2.4
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*
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* Revision 1.12 2004/08/24 07:19:59 starvik
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* Whitespace cleanup
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*
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* Revision 1.11 2004/05/14 07:58:03 starvik
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* Merge of changes from 2.4
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*
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* Revision 1.9 2003/09/11 07:29:48 starvik
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* Merge of Linux 2.6.0-test5
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*
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* Revision 1.8 2003/07/04 08:27:37 starvik
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* Merge of Linux 2.5.74
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*
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* Revision 1.7 2003/01/10 07:44:07 starvik
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* init_ioremap is now called by kernel before drivers are initialized
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*
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* Revision 1.6 2002/12/11 13:13:57 starvik
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* Added arch/ to v10 specific includes
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* Added fix from Linux 2.4 in serial.c (flush_to_flip_buffer)
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*
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* Revision 1.5 2002/11/20 11:56:11 starvik
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* Merge of Linux 2.5.48
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*
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* Revision 1.4 2002/11/18 10:10:05 starvik
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* Linux 2.5 port of latest gpio.c from Linux 2.4
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*
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* Revision 1.20 2002/10/16 21:16:24 johana
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* Added support for PA high level interrupt.
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* That gives 2ms response time with iodtest for high levels and 2-12 ms
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* response time on low levels if the check is not made in
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* process.c:cpu_idle() as well.
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*
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* Revision 1.19 2002/10/14 18:27:33 johana
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* Implemented alarm handling so select() now works.
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* Latency is around 6-9 ms with a etrax_gpio_wake_up_check() in
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* cpu_idle().
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* Otherwise I get 15-18 ms (same as doing the poll in userspace -
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* but less overhead).
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* TODO? Perhaps we should add the check in IMMEDIATE_BH (or whatever it
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* is in 2.4) as well?
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* TODO? Perhaps call request_irq()/free_irq() only when needed?
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* Increased version to 2.5
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*
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* Revision 1.18 2002/10/11 15:02:00 johana
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* Mask inverted 8 bit value in setget_input().
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*
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* Revision 1.17 2002/06/17 15:53:01 johana
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* Added IO_READ_INBITS, IO_READ_OUTBITS, IO_SETGET_INPUT and IO_SETGET_OUTPUT
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* that take a pointer as argument and thus can handle 32 bit ports (G)
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* correctly.
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* These should be used instead of IO_READBITS, IO_SETINPUT and IO_SETOUTPUT.
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* (especially if Port G bit 31 is used)
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*
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* Revision 1.16 2002/06/17 09:59:51 johana
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* Returning 32 bit values in the ioctl return value doesn't work if bit
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* 31 is set (could happen for port G), so mask it of with 0x7FFFFFFF.
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* A new set of ioctl's will be added.
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*
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* Revision 1.15 2002/05/06 13:19:13 johana
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* IO_SETINPUT returns mask with bit set = inputs for PA and PB as well.
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*
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* Revision 1.14 2002/04/12 12:01:53 johana
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* Use global r_port_g_data_shadow.
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* Moved gpio_init_port_g() closer to gpio_init() and marked it __init.
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*
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* Revision 1.13 2002/04/10 12:03:55 johana
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* Added support for port G /dev/gpiog (minor 3).
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* Changed indentation on switch cases.
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* Fixed other spaces to tabs.
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*
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* Revision 1.12 2001/11/12 19:42:15 pkj
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* * Corrected return values from gpio_leds_ioctl().
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* * Fixed compiler warnings.
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*
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* Revision 1.11 2001/10/30 14:39:12 johana
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* Added D() around gpio_write printk.
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*
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* Revision 1.10 2001/10/25 10:24:42 johana
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* Added IO_CFG_WRITE_MODE ioctl and write method that can do fast
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* bittoggling in the kernel. (This speeds up programming an FPGA with 450kB
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* from ~60 seconds to 4 seconds).
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* Added save_flags/cli/restore_flags in ioctl.
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*
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* Revision 1.9 2001/05/04 14:16:07 matsfg
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* Corrected spelling error
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*
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* Revision 1.8 2001/04/27 13:55:26 matsfg
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* Moved initioremap.
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* Turns off all LEDS on init.
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* Added support for shutdown and powerbutton.
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*
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* Revision 1.7 2001/04/04 13:30:08 matsfg
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* Added bitset and bitclear for leds. Calls init_ioremap to set up memmapping
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*
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* Revision 1.6 2001/03/26 16:03:06 bjornw
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* Needs linux/config.h
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*
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* Revision 1.5 2001/03/26 14:22:03 bjornw
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* Namechange of some config options
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*
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* Revision 1.4 2001/02/27 13:52:48 bjornw
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* malloc.h -> slab.h
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*
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* Revision 1.3 2001/01/24 15:06:48 bjornw
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* gpio_wq correct type
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*
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* Revision 1.2 2001/01/18 16:07:30 bjornw
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* 2.4 port
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*
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* Revision 1.1 2001/01/18 15:55:16 bjornw
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* Verbatim copy of etraxgpio.c from elinux 2.0 added
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*
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*
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*/
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@ -165,7 +38,7 @@ static int dp_cnt;
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#else
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#define DP(x)
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#endif
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static char gpio_name[] = "etrax gpio";
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#if 0
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@ -211,12 +84,12 @@ static DEFINE_SPINLOCK(gpio_lock); /* Protect directions etc */
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/* Port A and B use 8 bit access, but Port G is 32 bit */
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#define NUM_PORTS (GPIO_MINOR_B+1)
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static volatile unsigned char *ports[NUM_PORTS] = {
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R_PORT_PA_DATA,
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static volatile unsigned char *ports[NUM_PORTS] = {
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R_PORT_PA_DATA,
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R_PORT_PB_DATA,
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};
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static volatile unsigned char *shads[NUM_PORTS] = {
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&port_pa_data_shadow,
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&port_pa_data_shadow,
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&port_pb_data_shadow
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};
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@ -236,29 +109,29 @@ static volatile unsigned char *shads[NUM_PORTS] = {
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#endif
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static unsigned char changeable_dir[NUM_PORTS] = {
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static unsigned char changeable_dir[NUM_PORTS] = {
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CONFIG_ETRAX_PA_CHANGEABLE_DIR,
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CONFIG_ETRAX_PB_CHANGEABLE_DIR
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CONFIG_ETRAX_PB_CHANGEABLE_DIR
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};
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static unsigned char changeable_bits[NUM_PORTS] = {
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static unsigned char changeable_bits[NUM_PORTS] = {
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CONFIG_ETRAX_PA_CHANGEABLE_BITS,
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CONFIG_ETRAX_PB_CHANGEABLE_BITS
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CONFIG_ETRAX_PB_CHANGEABLE_BITS
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};
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static volatile unsigned char *dir[NUM_PORTS] = {
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R_PORT_PA_DIR,
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R_PORT_PB_DIR
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static volatile unsigned char *dir[NUM_PORTS] = {
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R_PORT_PA_DIR,
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R_PORT_PB_DIR
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};
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static volatile unsigned char *dir_shadow[NUM_PORTS] = {
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&port_pa_dir_shadow,
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&port_pb_dir_shadow
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&port_pa_dir_shadow,
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&port_pb_dir_shadow
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};
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/* All bits in port g that can change dir. */
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static const unsigned long int changeable_dir_g_mask = 0x01FFFF01;
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/* Port G is 32 bit, handle it special, some bits are both inputs
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/* Port G is 32 bit, handle it special, some bits are both inputs
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and outputs at the same time, only some of the bits can change direction
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and some of them in groups of 8 bit. */
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static unsigned long changeable_dir_g;
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@ -269,18 +142,17 @@ static unsigned long dir_g_shadow; /* 1=output */
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#define USE_PORTS(priv) ((priv)->minor <= GPIO_MINOR_B)
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static unsigned int
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gpio_poll(struct file *file,
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poll_table *wait)
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static unsigned int gpio_poll(struct file *file, poll_table *wait)
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{
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unsigned int mask = 0;
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struct gpio_private *priv = (struct gpio_private *)file->private_data;
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unsigned long data;
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spin_lock(&gpio_lock);
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unsigned long flags;
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spin_lock_irqsave(&gpio_lock, flags);
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poll_wait(file, &priv->alarm_wq, wait);
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if (priv->minor == GPIO_MINOR_A) {
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unsigned long flags;
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unsigned long tmp;
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data = *R_PORT_PA_DATA;
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/* PA has support for high level interrupt -
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@ -288,27 +160,25 @@ gpio_poll(struct file *file,
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*/
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tmp = ~data & priv->highalarm & 0xFF;
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tmp = (tmp << R_IRQ_MASK1_SET__pa0__BITNR);
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local_irq_save(flags);
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gpio_pa_irq_enabled_mask |= tmp;
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*R_IRQ_MASK1_SET = tmp;
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local_irq_restore(flags);
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} else if (priv->minor == GPIO_MINOR_B)
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data = *R_PORT_PB_DATA;
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else if (priv->minor == GPIO_MINOR_G)
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data = *R_PORT_G_DATA;
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else {
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spin_unlock(&gpio_lock);
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return 0;
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mask = 0;
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goto out;
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}
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if ((data & priv->highalarm) ||
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(~data & priv->lowalarm)) {
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mask = POLLIN|POLLRDNORM;
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}
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spin_unlock(&gpio_lock);
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out:
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spin_unlock_irqrestore(&gpio_lock, flags);
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DP(printk("gpio_poll ready: mask 0x%08X\n", mask));
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return mask;
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@ -316,16 +186,19 @@ gpio_poll(struct file *file,
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int etrax_gpio_wake_up_check(void)
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{
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struct gpio_private *priv = alarmlist;
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struct gpio_private *priv;
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unsigned long data = 0;
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int ret = 0;
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spin_lock(&gpio_lock);
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unsigned long flags;
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spin_lock_irqsave(&gpio_lock, flags);
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priv = alarmlist;
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while (priv) {
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if (USE_PORTS(priv)) {
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if (USE_PORTS(priv))
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data = *priv->port;
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} else if (priv->minor == GPIO_MINOR_G) {
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else if (priv->minor == GPIO_MINOR_G)
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data = *R_PORT_G_DATA;
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}
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if ((data & priv->highalarm) ||
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(~data & priv->lowalarm)) {
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DP(printk("etrax_gpio_wake_up_check %i\n",priv->minor));
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@ -334,12 +207,12 @@ int etrax_gpio_wake_up_check(void)
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}
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priv = priv->next;
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}
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spin_unlock(&gpio_lock);
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spin_unlock_irqrestore(&gpio_lock, flags);
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return ret;
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}
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static irqreturn_t
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gpio_poll_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
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gpio_poll_timer_interrupt(int irq, void *dev_id)
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{
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if (gpio_some_alarms) {
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etrax_gpio_wake_up_check();
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@ -349,10 +222,13 @@ gpio_poll_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
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}
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static irqreturn_t
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gpio_pa_interrupt(int irq, void *dev_id, struct pt_regs *regs)
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gpio_pa_interrupt(int irq, void *dev_id)
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{
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unsigned long tmp;
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spin_lock(&gpio_lock);
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unsigned long flags;
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spin_lock_irqsave(&gpio_lock, flags);
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/* Find what PA interrupts are active */
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tmp = (*R_IRQ_READ1);
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@ -363,75 +239,70 @@ gpio_pa_interrupt(int irq, void *dev_id, struct pt_regs *regs)
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*R_IRQ_MASK1_CLR = tmp;
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gpio_pa_irq_enabled_mask &= ~tmp;
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spin_unlock(&gpio_lock);
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spin_unlock_irqrestore(&gpio_lock, flags);
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if (gpio_some_alarms) {
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if (gpio_some_alarms)
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return IRQ_RETVAL(etrax_gpio_wake_up_check());
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}
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return IRQ_NONE;
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}
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static void gpio_write_bit(struct gpio_private *priv,
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unsigned char data, int bit)
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{
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*priv->port = *priv->shadow &= ~(priv->clk_mask);
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if (data & 1 << bit)
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*priv->port = *priv->shadow |= priv->data_mask;
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else
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*priv->port = *priv->shadow &= ~(priv->data_mask);
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/* For FPGA: min 5.0ns (DCC) before CCLK high */
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*priv->port = *priv->shadow |= priv->clk_mask;
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}
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static void gpio_write_byte(struct gpio_private *priv, unsigned char data)
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{
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int i;
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if (priv->write_msb)
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for (i = 7; i >= 0; i--)
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gpio_write_bit(priv, data, i);
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else
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for (i = 0; i <= 7; i++)
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gpio_write_bit(priv, data, i);
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}
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static ssize_t gpio_write(struct file * file, const char * buf, size_t count,
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loff_t *off)
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{
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struct gpio_private *priv = (struct gpio_private *)file->private_data;
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unsigned char data, clk_mask, data_mask, write_msb;
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unsigned long flags;
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spin_lock(&gpio_lock);
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ssize_t retval = count;
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if (priv->minor !=GPIO_MINOR_A && priv->minor != GPIO_MINOR_B) {
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retval = -EFAULT;
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goto out;
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}
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if (!access_ok(VERIFY_READ, buf, count)) {
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retval = -EFAULT;
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goto out;
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}
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clk_mask = priv->clk_mask;
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data_mask = priv->data_mask;
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if (priv->minor != GPIO_MINOR_A && priv->minor != GPIO_MINOR_B)
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return -EFAULT;
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if (!access_ok(VERIFY_READ, buf, count))
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return -EFAULT;
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spin_lock_irqsave(&gpio_lock, flags);
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/* It must have been configured using the IO_CFG_WRITE_MODE */
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/* Perhaps a better error code? */
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if (clk_mask == 0 || data_mask == 0) {
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if (priv->clk_mask == 0 || priv->data_mask == 0) {
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retval = -EPERM;
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goto out;
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}
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write_msb = priv->write_msb;
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D(printk("gpio_write: %lu to data 0x%02X clk 0x%02X msb: %i\n",count, data_mask, clk_mask, write_msb));
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while (count--) {
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int i;
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data = *buf++;
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if (priv->write_msb) {
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for (i = 7; i >= 0;i--) {
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local_irq_save(flags);
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*priv->port = *priv->shadow &= ~clk_mask;
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if (data & 1<<i)
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*priv->port = *priv->shadow |= data_mask;
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else
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*priv->port = *priv->shadow &= ~data_mask;
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/* For FPGA: min 5.0ns (DCC) before CCLK high */
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*priv->port = *priv->shadow |= clk_mask;
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local_irq_restore(flags);
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}
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} else {
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for (i = 0; i <= 7;i++) {
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local_irq_save(flags);
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*priv->port = *priv->shadow &= ~clk_mask;
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if (data & 1<<i)
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*priv->port = *priv->shadow |= data_mask;
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else
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*priv->port = *priv->shadow &= ~data_mask;
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/* For FPGA: min 5.0ns (DCC) before CCLK high */
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*priv->port = *priv->shadow |= clk_mask;
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local_irq_restore(flags);
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}
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}
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}
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D(printk(KERN_DEBUG "gpio_write: %02X to data 0x%02X "
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"clk 0x%02X msb: %i\n",
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count, priv->data_mask, priv->clk_mask, priv->write_msb));
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while (count--)
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gpio_write_byte(priv, *buf++);
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out:
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spin_unlock(&gpio_lock);
|
||||
spin_unlock_irqrestore(&gpio_lock, flags);
|
||||
return retval;
|
||||
}
|
||||
|
||||
|
|
@ -442,22 +313,22 @@ gpio_open(struct inode *inode, struct file *filp)
|
|||
{
|
||||
struct gpio_private *priv;
|
||||
int p = iminor(inode);
|
||||
unsigned long flags;
|
||||
|
||||
if (p > GPIO_MINOR_LAST)
|
||||
return -EINVAL;
|
||||
|
||||
priv = kmalloc(sizeof(struct gpio_private),
|
||||
GFP_KERNEL);
|
||||
priv = kmalloc(sizeof(struct gpio_private), GFP_KERNEL);
|
||||
|
||||
if (!priv)
|
||||
return -ENOMEM;
|
||||
|
||||
memset(priv, 0, sizeof(*priv));
|
||||
|
||||
priv->minor = p;
|
||||
|
||||
/* initialize the io/alarm struct and link it into our alarmlist */
|
||||
/* initialize the io/alarm struct */
|
||||
|
||||
priv->next = alarmlist;
|
||||
alarmlist = priv;
|
||||
if (USE_PORTS(priv)) { /* A and B */
|
||||
priv->port = ports[p];
|
||||
priv->shadow = shads[p];
|
||||
|
|
@ -482,6 +353,12 @@ gpio_open(struct inode *inode, struct file *filp)
|
|||
|
||||
filp->private_data = (void *)priv;
|
||||
|
||||
/* link it into our alarmlist */
|
||||
spin_lock_irqsave(&gpio_lock, flags);
|
||||
priv->next = alarmlist;
|
||||
alarmlist = priv;
|
||||
spin_unlock_irqrestore(&gpio_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -490,11 +367,12 @@ gpio_release(struct inode *inode, struct file *filp)
|
|||
{
|
||||
struct gpio_private *p;
|
||||
struct gpio_private *todel;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock(&gpio_lock);
|
||||
spin_lock_irqsave(&gpio_lock, flags);
|
||||
|
||||
p = alarmlist;
|
||||
todel = (struct gpio_private *)filp->private_data;
|
||||
p = alarmlist;
|
||||
todel = (struct gpio_private *)filp->private_data;
|
||||
|
||||
/* unlink from alarmlist and free the private structure */
|
||||
|
||||
|
|
@ -512,123 +390,114 @@ gpio_release(struct inode *inode, struct file *filp)
|
|||
while (p) {
|
||||
if (p->highalarm | p->lowalarm) {
|
||||
gpio_some_alarms = 1;
|
||||
spin_unlock(&gpio_lock);
|
||||
return 0;
|
||||
goto out;
|
||||
}
|
||||
p = p->next;
|
||||
}
|
||||
gpio_some_alarms = 0;
|
||||
spin_unlock(&gpio_lock);
|
||||
out:
|
||||
spin_unlock_irqrestore(&gpio_lock, flags);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Main device API. ioctl's to read/set/clear bits, as well as to
|
||||
/* Main device API. ioctl's to read/set/clear bits, as well as to
|
||||
* set alarms to wait for using a subsequent select().
|
||||
*/
|
||||
|
||||
unsigned long inline setget_input(struct gpio_private *priv, unsigned long arg)
|
||||
{
|
||||
/* Set direction 0=unchanged 1=input,
|
||||
* return mask with 1=input
|
||||
*/
|
||||
unsigned long flags;
|
||||
/* Set direction 0=unchanged 1=input,
|
||||
* return mask with 1=input */
|
||||
if (USE_PORTS(priv)) {
|
||||
local_irq_save(flags);
|
||||
*priv->dir = *priv->dir_shadow &=
|
||||
*priv->dir = *priv->dir_shadow &=
|
||||
~((unsigned char)arg & priv->changeable_dir);
|
||||
local_irq_restore(flags);
|
||||
return ~(*priv->dir_shadow) & 0xFF; /* Only 8 bits */
|
||||
} else if (priv->minor == GPIO_MINOR_G) {
|
||||
/* We must fiddle with R_GEN_CONFIG to change dir */
|
||||
local_irq_save(flags);
|
||||
if (((arg & dir_g_in_bits) != arg) &&
|
||||
(arg & changeable_dir_g)) {
|
||||
arg &= changeable_dir_g;
|
||||
/* Clear bits in genconfig to set to input */
|
||||
if (arg & (1<<0)) {
|
||||
genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG,g0dir);
|
||||
dir_g_in_bits |= (1<<0);
|
||||
dir_g_out_bits &= ~(1<<0);
|
||||
}
|
||||
if ((arg & 0x0000FF00) == 0x0000FF00) {
|
||||
genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG,g8_15dir);
|
||||
dir_g_in_bits |= 0x0000FF00;
|
||||
dir_g_out_bits &= ~0x0000FF00;
|
||||
}
|
||||
if ((arg & 0x00FF0000) == 0x00FF0000) {
|
||||
genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG,g16_23dir);
|
||||
dir_g_in_bits |= 0x00FF0000;
|
||||
dir_g_out_bits &= ~0x00FF0000;
|
||||
}
|
||||
if (arg & (1<<24)) {
|
||||
genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG,g24dir);
|
||||
dir_g_in_bits |= (1<<24);
|
||||
dir_g_out_bits &= ~(1<<24);
|
||||
}
|
||||
D(printk(KERN_INFO "gpio: SETINPUT on port G set "
|
||||
"genconfig to 0x%08lX "
|
||||
"in_bits: 0x%08lX "
|
||||
"out_bits: 0x%08lX\n",
|
||||
(unsigned long)genconfig_shadow,
|
||||
dir_g_in_bits, dir_g_out_bits));
|
||||
*R_GEN_CONFIG = genconfig_shadow;
|
||||
/* Must be a >120 ns delay before writing this again */
|
||||
|
||||
}
|
||||
local_irq_restore(flags);
|
||||
return dir_g_in_bits;
|
||||
}
|
||||
return 0;
|
||||
|
||||
if (priv->minor != GPIO_MINOR_G)
|
||||
return 0;
|
||||
|
||||
/* We must fiddle with R_GEN_CONFIG to change dir */
|
||||
if (((arg & dir_g_in_bits) != arg) &&
|
||||
(arg & changeable_dir_g)) {
|
||||
arg &= changeable_dir_g;
|
||||
/* Clear bits in genconfig to set to input */
|
||||
if (arg & (1<<0)) {
|
||||
genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, g0dir);
|
||||
dir_g_in_bits |= (1<<0);
|
||||
dir_g_out_bits &= ~(1<<0);
|
||||
}
|
||||
if ((arg & 0x0000FF00) == 0x0000FF00) {
|
||||
genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, g8_15dir);
|
||||
dir_g_in_bits |= 0x0000FF00;
|
||||
dir_g_out_bits &= ~0x0000FF00;
|
||||
}
|
||||
if ((arg & 0x00FF0000) == 0x00FF0000) {
|
||||
genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, g16_23dir);
|
||||
dir_g_in_bits |= 0x00FF0000;
|
||||
dir_g_out_bits &= ~0x00FF0000;
|
||||
}
|
||||
if (arg & (1<<24)) {
|
||||
genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, g24dir);
|
||||
dir_g_in_bits |= (1<<24);
|
||||
dir_g_out_bits &= ~(1<<24);
|
||||
}
|
||||
D(printk(KERN_DEBUG "gpio: SETINPUT on port G set "
|
||||
"genconfig to 0x%08lX "
|
||||
"in_bits: 0x%08lX "
|
||||
"out_bits: 0x%08lX\n",
|
||||
(unsigned long)genconfig_shadow,
|
||||
dir_g_in_bits, dir_g_out_bits));
|
||||
*R_GEN_CONFIG = genconfig_shadow;
|
||||
/* Must be a >120 ns delay before writing this again */
|
||||
|
||||
}
|
||||
return dir_g_in_bits;
|
||||
} /* setget_input */
|
||||
|
||||
unsigned long inline setget_output(struct gpio_private *priv, unsigned long arg)
|
||||
{
|
||||
unsigned long flags;
|
||||
if (USE_PORTS(priv)) {
|
||||
local_irq_save(flags);
|
||||
*priv->dir = *priv->dir_shadow |=
|
||||
((unsigned char)arg & priv->changeable_dir);
|
||||
local_irq_restore(flags);
|
||||
*priv->dir = *priv->dir_shadow |=
|
||||
((unsigned char)arg & priv->changeable_dir);
|
||||
return *priv->dir_shadow;
|
||||
} else if (priv->minor == GPIO_MINOR_G) {
|
||||
/* We must fiddle with R_GEN_CONFIG to change dir */
|
||||
local_irq_save(flags);
|
||||
if (((arg & dir_g_out_bits) != arg) &&
|
||||
(arg & changeable_dir_g)) {
|
||||
/* Set bits in genconfig to set to output */
|
||||
if (arg & (1<<0)) {
|
||||
genconfig_shadow |= IO_MASK(R_GEN_CONFIG,g0dir);
|
||||
dir_g_out_bits |= (1<<0);
|
||||
dir_g_in_bits &= ~(1<<0);
|
||||
}
|
||||
if ((arg & 0x0000FF00) == 0x0000FF00) {
|
||||
genconfig_shadow |= IO_MASK(R_GEN_CONFIG,g8_15dir);
|
||||
dir_g_out_bits |= 0x0000FF00;
|
||||
dir_g_in_bits &= ~0x0000FF00;
|
||||
}
|
||||
if ((arg & 0x00FF0000) == 0x00FF0000) {
|
||||
genconfig_shadow |= IO_MASK(R_GEN_CONFIG,g16_23dir);
|
||||
dir_g_out_bits |= 0x00FF0000;
|
||||
dir_g_in_bits &= ~0x00FF0000;
|
||||
}
|
||||
if (arg & (1<<24)) {
|
||||
genconfig_shadow |= IO_MASK(R_GEN_CONFIG,g24dir);
|
||||
dir_g_out_bits |= (1<<24);
|
||||
dir_g_in_bits &= ~(1<<24);
|
||||
}
|
||||
D(printk(KERN_INFO "gpio: SETOUTPUT on port G set "
|
||||
"genconfig to 0x%08lX "
|
||||
"in_bits: 0x%08lX "
|
||||
"out_bits: 0x%08lX\n",
|
||||
(unsigned long)genconfig_shadow,
|
||||
dir_g_in_bits, dir_g_out_bits));
|
||||
*R_GEN_CONFIG = genconfig_shadow;
|
||||
/* Must be a >120 ns delay before writing this again */
|
||||
}
|
||||
local_irq_restore(flags);
|
||||
return dir_g_out_bits & 0x7FFFFFFF;
|
||||
}
|
||||
return 0;
|
||||
if (priv->minor != GPIO_MINOR_G)
|
||||
return 0;
|
||||
|
||||
/* We must fiddle with R_GEN_CONFIG to change dir */
|
||||
if (((arg & dir_g_out_bits) != arg) &&
|
||||
(arg & changeable_dir_g)) {
|
||||
/* Set bits in genconfig to set to output */
|
||||
if (arg & (1<<0)) {
|
||||
genconfig_shadow |= IO_MASK(R_GEN_CONFIG, g0dir);
|
||||
dir_g_out_bits |= (1<<0);
|
||||
dir_g_in_bits &= ~(1<<0);
|
||||
}
|
||||
if ((arg & 0x0000FF00) == 0x0000FF00) {
|
||||
genconfig_shadow |= IO_MASK(R_GEN_CONFIG, g8_15dir);
|
||||
dir_g_out_bits |= 0x0000FF00;
|
||||
dir_g_in_bits &= ~0x0000FF00;
|
||||
}
|
||||
if ((arg & 0x00FF0000) == 0x00FF0000) {
|
||||
genconfig_shadow |= IO_MASK(R_GEN_CONFIG, g16_23dir);
|
||||
dir_g_out_bits |= 0x00FF0000;
|
||||
dir_g_in_bits &= ~0x00FF0000;
|
||||
}
|
||||
if (arg & (1<<24)) {
|
||||
genconfig_shadow |= IO_MASK(R_GEN_CONFIG, g24dir);
|
||||
dir_g_out_bits |= (1<<24);
|
||||
dir_g_in_bits &= ~(1<<24);
|
||||
}
|
||||
D(printk(KERN_INFO "gpio: SETOUTPUT on port G set "
|
||||
"genconfig to 0x%08lX "
|
||||
"in_bits: 0x%08lX "
|
||||
"out_bits: 0x%08lX\n",
|
||||
(unsigned long)genconfig_shadow,
|
||||
dir_g_in_bits, dir_g_out_bits));
|
||||
*R_GEN_CONFIG = genconfig_shadow;
|
||||
/* Must be a >120 ns delay before writing this again */
|
||||
}
|
||||
return dir_g_out_bits & 0x7FFFFFFF;
|
||||
} /* setget_output */
|
||||
|
||||
static int
|
||||
|
|
@ -643,11 +512,10 @@ gpio_ioctl(struct inode *inode, struct file *file,
|
|||
int ret = 0;
|
||||
|
||||
struct gpio_private *priv = (struct gpio_private *)file->private_data;
|
||||
if (_IOC_TYPE(cmd) != ETRAXGPIO_IOCTYPE) {
|
||||
if (_IOC_TYPE(cmd) != ETRAXGPIO_IOCTYPE)
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
spin_lock(&gpio_lock);
|
||||
spin_lock_irqsave(&gpio_lock, flags);
|
||||
|
||||
switch (_IOC_NR(cmd)) {
|
||||
case IO_READBITS: /* Use IO_READ_INBITS and IO_READ_OUTBITS instead */
|
||||
|
|
@ -659,7 +527,6 @@ gpio_ioctl(struct inode *inode, struct file *file,
|
|||
}
|
||||
break;
|
||||
case IO_SETBITS:
|
||||
local_irq_save(flags);
|
||||
// set changeable bits with a 1 in arg
|
||||
if (USE_PORTS(priv)) {
|
||||
*priv->port = *priv->shadow |=
|
||||
|
|
@ -667,10 +534,8 @@ gpio_ioctl(struct inode *inode, struct file *file,
|
|||
} else if (priv->minor == GPIO_MINOR_G) {
|
||||
*R_PORT_G_DATA = port_g_data_shadow |= (arg & dir_g_out_bits);
|
||||
}
|
||||
local_irq_restore(flags);
|
||||
break;
|
||||
case IO_CLRBITS:
|
||||
local_irq_save(flags);
|
||||
// clear changeable bits with a 1 in arg
|
||||
if (USE_PORTS(priv)) {
|
||||
*priv->port = *priv->shadow &=
|
||||
|
|
@ -678,7 +543,6 @@ gpio_ioctl(struct inode *inode, struct file *file,
|
|||
} else if (priv->minor == GPIO_MINOR_G) {
|
||||
*R_PORT_G_DATA = port_g_data_shadow &= ~((unsigned long)arg & dir_g_out_bits);
|
||||
}
|
||||
local_irq_restore(flags);
|
||||
break;
|
||||
case IO_HIGHALARM:
|
||||
// set alarm when bits with 1 in arg go high
|
||||
|
|
@ -698,6 +562,8 @@ gpio_ioctl(struct inode *inode, struct file *file,
|
|||
/* Must update gpio_some_alarms */
|
||||
struct gpio_private *p = alarmlist;
|
||||
int some_alarms;
|
||||
spin_lock_irq(&gpio_lock);
|
||||
p = alarmlist;
|
||||
some_alarms = 0;
|
||||
while (p) {
|
||||
if (p->highalarm | p->lowalarm) {
|
||||
|
|
@ -707,6 +573,7 @@ gpio_ioctl(struct inode *inode, struct file *file,
|
|||
p = p->next;
|
||||
}
|
||||
gpio_some_alarms = some_alarms;
|
||||
spin_unlock_irq(&gpio_lock);
|
||||
}
|
||||
break;
|
||||
case IO_READDIR: /* Use IO_SETGET_INPUT/OUTPUT instead! */
|
||||
|
|
@ -796,8 +663,7 @@ gpio_ioctl(struct inode *inode, struct file *file,
|
|||
/* bits set in *arg is set to output,
|
||||
* *arg updated with current output pins.
|
||||
*/
|
||||
if (copy_from_user(&val, (unsigned long*)arg, sizeof(val)))
|
||||
{
|
||||
if (copy_from_user(&val, (unsigned long *)arg, sizeof(val))) {
|
||||
ret = -EFAULT;
|
||||
break;
|
||||
}
|
||||
|
|
@ -812,7 +678,7 @@ gpio_ioctl(struct inode *inode, struct file *file,
|
|||
ret = -EINVAL;
|
||||
} /* switch */
|
||||
|
||||
spin_unlock(&gpio_lock);
|
||||
spin_unlock_irqrestore(&gpio_lock, flags);
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
@ -824,18 +690,18 @@ gpio_leds_ioctl(unsigned int cmd, unsigned long arg)
|
|||
|
||||
switch (_IOC_NR(cmd)) {
|
||||
case IO_LEDACTIVE_SET:
|
||||
green = ((unsigned char) arg) & 1;
|
||||
red = (((unsigned char) arg) >> 1) & 1;
|
||||
LED_ACTIVE_SET_G(green);
|
||||
LED_ACTIVE_SET_R(red);
|
||||
green = ((unsigned char)arg) & 1;
|
||||
red = (((unsigned char)arg) >> 1) & 1;
|
||||
CRIS_LED_ACTIVE_SET_G(green);
|
||||
CRIS_LED_ACTIVE_SET_R(red);
|
||||
break;
|
||||
|
||||
case IO_LED_SETBIT:
|
||||
LED_BIT_SET(arg);
|
||||
CRIS_LED_BIT_SET(arg);
|
||||
break;
|
||||
|
||||
case IO_LED_CLRBIT:
|
||||
LED_BIT_CLR(arg);
|
||||
CRIS_LED_BIT_CLR(arg);
|
||||
break;
|
||||
|
||||
default:
|
||||
|
|
@ -854,16 +720,18 @@ const struct file_operations gpio_fops = {
|
|||
.release = gpio_release,
|
||||
};
|
||||
|
||||
|
||||
void ioif_watcher(const unsigned int gpio_in_available,
|
||||
const unsigned int gpio_out_available,
|
||||
const unsigned char pa_available,
|
||||
const unsigned char pb_available)
|
||||
{
|
||||
unsigned long int flags;
|
||||
D(printk("gpio.c: ioif_watcher called\n"));
|
||||
D(printk("gpio.c: G in: 0x%08x G out: 0x%08x PA: 0x%02x PB: 0x%02x\n",
|
||||
gpio_in_available, gpio_out_available, pa_available, pb_available));
|
||||
|
||||
D(printk(KERN_DEBUG "gpio.c: ioif_watcher called\n"));
|
||||
D(printk(KERN_DEBUG "gpio.c: G in: 0x%08x G out: 0x%08x "
|
||||
"PA: 0x%02x PB: 0x%02x\n",
|
||||
gpio_in_available, gpio_out_available,
|
||||
pa_available, pb_available));
|
||||
|
||||
spin_lock_irqsave(&gpio_lock, flags);
|
||||
|
||||
|
|
@ -872,7 +740,7 @@ void ioif_watcher(const unsigned int gpio_in_available,
|
|||
|
||||
/* Initialise the dir_g_shadow etc. depending on genconfig */
|
||||
/* 0=input 1=output */
|
||||
if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, g0dir, out))
|
||||
if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, g0dir, out))
|
||||
dir_g_shadow |= (1 << 0);
|
||||
if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, g8_15dir, out))
|
||||
dir_g_shadow |= 0x0000FF00;
|
||||
|
|
@ -884,7 +752,8 @@ void ioif_watcher(const unsigned int gpio_in_available,
|
|||
changeable_dir_g = changeable_dir_g_mask;
|
||||
changeable_dir_g &= dir_g_out_bits;
|
||||
changeable_dir_g &= dir_g_in_bits;
|
||||
/* Correct the bits that can change direction */
|
||||
|
||||
/* Correct the bits that can change direction */
|
||||
dir_g_out_bits &= ~changeable_dir_g;
|
||||
dir_g_out_bits |= dir_g_shadow;
|
||||
dir_g_in_bits &= ~changeable_dir_g;
|
||||
|
|
@ -892,7 +761,8 @@ void ioif_watcher(const unsigned int gpio_in_available,
|
|||
|
||||
spin_unlock_irqrestore(&gpio_lock, flags);
|
||||
|
||||
printk(KERN_INFO "GPIO port G: in_bits: 0x%08lX out_bits: 0x%08lX val: %08lX\n",
|
||||
printk(KERN_INFO "GPIO port G: in_bits: 0x%08lX out_bits: 0x%08lX "
|
||||
"val: %08lX\n",
|
||||
dir_g_in_bits, dir_g_out_bits, (unsigned long)*R_PORT_G_DATA);
|
||||
printk(KERN_INFO "GPIO port G: dir: %08lX changeable: %08lX\n",
|
||||
dir_g_shadow, changeable_dir_g);
|
||||
|
|
@ -907,9 +777,6 @@ gpio_init(void)
|
|||
#if defined (CONFIG_ETRAX_CSP0_LEDS)
|
||||
int i;
|
||||
#endif
|
||||
printk("gpio init\n");
|
||||
|
||||
/* do the formalities */
|
||||
|
||||
res = register_chrdev(GPIO_MAJOR, gpio_name, &gpio_fops);
|
||||
if (res < 0) {
|
||||
|
|
@ -919,39 +786,41 @@ gpio_init(void)
|
|||
|
||||
/* Clear all leds */
|
||||
#if defined (CONFIG_ETRAX_CSP0_LEDS) || defined (CONFIG_ETRAX_PA_LEDS) || defined (CONFIG_ETRAX_PB_LEDS)
|
||||
LED_NETWORK_SET(0);
|
||||
LED_ACTIVE_SET(0);
|
||||
LED_DISK_READ(0);
|
||||
LED_DISK_WRITE(0);
|
||||
CRIS_LED_NETWORK_SET(0);
|
||||
CRIS_LED_ACTIVE_SET(0);
|
||||
CRIS_LED_DISK_READ(0);
|
||||
CRIS_LED_DISK_WRITE(0);
|
||||
|
||||
#if defined (CONFIG_ETRAX_CSP0_LEDS)
|
||||
for (i = 0; i < 32; i++) {
|
||||
LED_BIT_SET(i);
|
||||
}
|
||||
for (i = 0; i < 32; i++)
|
||||
CRIS_LED_BIT_SET(i);
|
||||
#endif
|
||||
|
||||
#endif
|
||||
/* The I/O interface allocation watcher will be called when
|
||||
* registering it. */
|
||||
if (cris_io_interface_register_watcher(ioif_watcher)){
|
||||
printk(KERN_WARNING "gpio_init: Failed to install IO if allocator watcher\n");
|
||||
printk(KERN_WARNING "gpio_init: Failed to install IO "
|
||||
"if allocator watcher\n");
|
||||
}
|
||||
|
||||
printk(KERN_INFO "ETRAX 100LX GPIO driver v2.5, (c) 2001, 2002, 2003, 2004 Axis Communications AB\n");
|
||||
printk(KERN_INFO "ETRAX 100LX GPIO driver v2.5, (c) 2001-2008 "
|
||||
"Axis Communications AB\n");
|
||||
/* We call etrax_gpio_wake_up_check() from timer interrupt and
|
||||
* from cpu_idle() in kernel/process.c
|
||||
* The check in cpu_idle() reduces latency from ~15 ms to ~6 ms
|
||||
* in some tests.
|
||||
*/
|
||||
if (request_irq(TIMER0_IRQ_NBR, gpio_poll_timer_interrupt,
|
||||
IRQF_SHARED | IRQF_DISABLED,"gpio poll", NULL)) {
|
||||
*/
|
||||
res = request_irq(TIMER0_IRQ_NBR, gpio_poll_timer_interrupt,
|
||||
IRQF_SHARED | IRQF_DISABLED, "gpio poll", gpio_name);
|
||||
if (res) {
|
||||
printk(KERN_CRIT "err: timer0 irq for gpio\n");
|
||||
return res;
|
||||
}
|
||||
if (request_irq(PA_IRQ_NBR, gpio_pa_interrupt,
|
||||
IRQF_SHARED | IRQF_DISABLED,"gpio PA", NULL)) {
|
||||
res = request_irq(PA_IRQ_NBR, gpio_pa_interrupt,
|
||||
IRQF_SHARED | IRQF_DISABLED, "gpio PA", gpio_name);
|
||||
if (res)
|
||||
printk(KERN_CRIT "err: PA irq for gpio\n");
|
||||
}
|
||||
|
||||
|
||||
return res;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in a new issue