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ARM: SoC fixes for 3.16

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A new set of bug fixes for 3.16, containing patches for seven platforms:
 
 at91:
     - drivers/misc fix for Kconfig PWM symbol
     - correction of several values in DT after conversion to CCF
     - fix at91sam9261/at91sam9261ek mistake in slow crystal vs. slow RC osc
 
 imx:
     - Use GPIO for card CD/WP on imx51-babbage and eukrea-mbimxsd51,
       because controller base CD/WP is not working in esdhc driver due to
       runtime PM support
     - A couple of random ventana gw5xxx board fixes
     - Add IMX_IPUV3_CORE back to defconfig, which gets lost when moving
       IPUv3 driver out of staging tree
     - Fix enet/fec clock selection on imx6sl
     - Fix display node on imx53-m53evk board
     - A couple of Cubox-i updates from Russell, which were omitted from
       the merge window due to dependency
 
 integrator:
     - fix an OF-related regression against 3.15
 
 mvebu:
     - mvebu (v7)
        - Fix broken SoC ID detection
        - Select ARM_CPU_SUSPEND for v7
        - Remove armada38x compatible string (no users yet)
        - Enable Dove SoC in mvebu_v7_defconfig
     - kirkwood
        - Fix phy-connection-type on GuruPlug board
 
 qcom:
     - enable gsbi driver in defconfig
     - fix section mismatch warning in serial driver
 
 samsung:
     - use WFI macro in platform_do_lowpower because exynos cpuhotplug
       includes a hardcoded WFI instruction and it causes compile error
       in Thumb-2 mode.
     - fix GIC reg sizes for exynos4 SoCs
     - remove reset timer counter value during boot and resume for mct
       to fix a big jump in printk timestamps
     - fix pm code to check cortex-A9 for another exynos SoCs
     - don't rely on firmware's secondary_cpu_start for mcpm
 
 sti:
     - Ethernet clocks were wrongly defined for STiH415/416 platforms
     - STiH416 B2020 revision E DTS file name contained uppercase, change to
       lowercase.
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Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC fixes from Arnd Bergmann:
 "A new set of bug fixes for 3.16, containing patches for seven
  platforms:

  at91:
    - drivers/misc fix for Kconfig PWM symbol
    - correction of several values in DT after conversion to CCF
    - fix at91sam9261/at91sam9261ek mistake in slow crystal vs. slow RC osc

  imx:
    - Use GPIO for card CD/WP on imx51-babbage and eukrea-mbimxsd51,
      because controller base CD/WP is not working in esdhc driver due to
      runtime PM support
    - A couple of random ventana gw5xxx board fixes
    - Add IMX_IPUV3_CORE back to defconfig, which gets lost when moving
      IPUv3 driver out of staging tree
    - Fix enet/fec clock selection on imx6sl
    - Fix display node on imx53-m53evk board
    - A couple of Cubox-i updates from Russell, which were omitted from
      the merge window due to dependency

  integrator:
    - fix an OF-related regression against 3.15

  mvebu:
    - mvebu (v7)
       - Fix broken SoC ID detection
       - Select ARM_CPU_SUSPEND for v7
       - Remove armada38x compatible string (no users yet)
       - Enable Dove SoC in mvebu_v7_defconfig
    - kirkwood
       - Fix phy-connection-type on GuruPlug board

  qcom:
    - enable gsbi driver in defconfig
    - fix section mismatch warning in serial driver

  samsung:
    - use WFI macro in platform_do_lowpower because exynos cpuhotplug
      includes a hardcoded WFI instruction and it causes compile error
      in Thumb-2 mode.
    - fix GIC reg sizes for exynos4 SoCs
    - remove reset timer counter value during boot and resume for mct
      to fix a big jump in printk timestamps
    - fix pm code to check cortex-A9 for another exynos SoCs
    - don't rely on firmware's secondary_cpu_start for mcpm

  sti:
    - Ethernet clocks were wrongly defined for STiH415/416 platforms
    - STiH416 B2020 revision E DTS file name contained uppercase, change to
      lowercase"

* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (33 commits)
  ARM: at91/dt: sam9261: remove slow RC osc
  ARM: at91/dt: define sam9261ek slow crystal frequency
  ARM: at91/dt: sam9261: correctly define mainck
  ARM: at91/dt: sam9n12: correct PLLA ICPLL and OUT values
  ARM: at91/dt: sam9x5: correct PLLA ICPLL and OUT values
  misc: atmel_pwm: fix Kconfig symbols
  ARM: integrator: fix OF-related regression
  ARM: mvebu: Fix the improper use of the compatible string armada38x using a wildcard
  ARM: dts: kirkwood: fix phy-connection-type for Guruplug
  ARM: EXYNOS: Don't rely on firmware's secondary_cpu_start for mcpm
  ARM: dts: imx51-eukrea-mbimxsd51-baseboard: unbreak esdhc.
  ARM: dts: imx51-babbage: Fix esdhc setup
  ARM: dts: mx5: Move the display out of soc {} node
  ARM: dts: mx5: Fix IPU port node placement
  ARM: mvebu: select ARM_CPU_SUSPEND for Marvell EBU v7 platforms
  ARM: mvebu: Fix broken SoC ID detection
  ARM: imx_v6_v7_defconfig: Enable CONFIG_IMX_IPUV3_CORE
  ARM: multi_v7_defconfig: Add QCOM GSBI driver
  ARM: stih41x: Rename stih416-b2020-revE.dts to stih416-b2020e.dts
  tty: serial: msm: Fix section mismatch warning
  ...
This commit is contained in:
Linus Torvalds 2014-06-25 12:19:01 -07:00
commit 456febd299
43 changed files with 157 additions and 146 deletions
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14
Documentation/devicetree/bindings/arm/armada-38x.txt
View file

@ -6,5 +6,15 @@ following property:
Required root node property:
- compatible: must contain either "marvell,armada380" or
"marvell,armada385" depending on the variant of the SoC being used.
- compatible: must contain "marvell,armada380"
In addition, boards using the Marvell Armada 385 SoC shall have the
following property before the previous one:
Required root node property:
compatible: must contain "marvell,armada385"
Example:
compatible = "marvell,a385-rd", "marvell,armada385", "marvell,armada380";

2
arch/arm/boot/dts/Makefile
View file

@ -357,7 +357,7 @@ dtb-$(CONFIG_ARCH_STI)+= stih407-b2120.dtb \
stih415-b2020.dtb \
stih416-b2000.dtb \
stih416-b2020.dtb \
stih416-b2020-revE.dtb
stih416-b2020e.dtb
dtb-$(CONFIG_MACH_SUN4I) += \
sun4i-a10-a1000.dtb \
sun4i-a10-cubieboard.dtb \

2
arch/arm/boot/dts/armada-380.dtsi
View file

@ -16,7 +16,7 @@
/ {
model = "Marvell Armada 380 family SoC";
compatible = "marvell,armada380", "marvell,armada38x";
compatible = "marvell,armada380";
cpus {
#address-cells = <1>;

2
arch/arm/boot/dts/armada-385-db.dts
View file

@ -16,7 +16,7 @@
/ {
model = "Marvell Armada 385 Development Board";
compatible = "marvell,a385-db", "marvell,armada385", "marvell,armada38x";
compatible = "marvell,a385-db", "marvell,armada385", "marvell,armada380";
chosen {
bootargs = "console=ttyS0,115200 earlyprintk";

2
arch/arm/boot/dts/armada-385-rd.dts
View file

@ -17,7 +17,7 @@
/ {
model = "Marvell Armada 385 Reference Design";
compatible = "marvell,a385-rd", "marvell,armada385", "marvell,armada38x";
compatible = "marvell,a385-rd", "marvell,armada385", "marvell,armada380";
chosen {
bootargs = "console=ttyS0,115200 earlyprintk";

2
arch/arm/boot/dts/armada-385.dtsi
View file

@ -16,7 +16,7 @@
/ {
model = "Marvell Armada 385 family SoC";
compatible = "marvell,armada385", "marvell,armada38x";
compatible = "marvell,armada385", "marvell,armada380";
cpus {
#address-cells = <1>;

2
arch/arm/boot/dts/armada-38x.dtsi
View file

@ -20,7 +20,7 @@
/ {
model = "Marvell Armada 38x family SoC";
compatible = "marvell,armada38x";
compatible = "marvell,armada380";
aliases {
gpio0 = &gpio0;

21
arch/arm/boot/dts/at91sam9261.dtsi
View file

@ -568,24 +568,17 @@
#size-cells = <0>;
#interrupt-cells = <1>;
slow_rc_osc: slow_rc_osc {
compatible = "fixed-clock";
main_osc: main_osc {
compatible = "atmel,at91rm9200-clk-main-osc";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-accuracy = <50000000>;
};
clk32k: slck {
compatible = "atmel,at91sam9260-clk-slow";
#clock-cells = <0>;
clocks = <&slow_rc_osc &slow_xtal>;
interrupts-extended = <&pmc AT91_PMC_MOSCS>;
clocks = <&main_xtal>;
};
main: mainck {
compatible = "atmel,at91rm9200-clk-main";
#clock-cells = <0>;
interrupts-extended = <&pmc AT91_PMC_MOSCS>;
clocks = <&main_xtal>;
clocks = <&main_osc>;
};
plla: pllack {
@ -615,7 +608,7 @@
compatible = "atmel,at91rm9200-clk-master";
#clock-cells = <0>;
interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
atmel,clk-output-range = <0 94000000>;
atmel,clk-divisors = <1 2 4 0>;
};
@ -632,7 +625,7 @@
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&pmc>;
clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
prog0: prog0 {
#clock-cells = <0>;

4
arch/arm/boot/dts/at91sam9261ek.dts
View file

@ -20,6 +20,10 @@
reg = <0x20000000 0x4000000>;
};
slow_xtal {
clock-frequency = <32768>;
};
main_xtal {
clock-frequency = <18432000>;
};

4
arch/arm/boot/dts/at91sam9n12.dtsi
View file

@ -132,8 +132,8 @@
<595000000 650000000 3 0>,
<545000000 600000000 0 1>,
<495000000 555000000 1 1>,
<445000000 500000000 1 2>,
<400000000 450000000 1 3>;
<445000000 500000000 2 1>,
<400000000 450000000 3 1>;
};
plladiv: plladivck {

4
arch/arm/boot/dts/at91sam9x5.dtsi
View file

@ -140,8 +140,8 @@
595000000 650000000 3 0
545000000 600000000 0 1
495000000 555000000 1 1
445000000 500000000 1 2
400000000 450000000 1 3>;
445000000 500000000 2 1
400000000 450000000 3 1>;
};
plladiv: plladivck {

2
arch/arm/boot/dts/exynos4.dtsi
View file

@ -113,7 +113,7 @@
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x10490000 0x1000>, <0x10480000 0x100>;
reg = <0x10490000 0x10000>, <0x10480000 0x10000>;
};
combiner: interrupt-controller@10440000 {

10
arch/arm/boot/dts/imx51-babbage.dts
View file

@ -315,15 +315,15 @@
&esdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1>;
fsl,cd-controller;
fsl,wp-controller;
cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&esdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc2>;
cd-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
cd-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
status = "okay";
};
@ -468,8 +468,8 @@
MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
MX51_PAD_GPIO1_0__SD1_CD 0x20d5
MX51_PAD_GPIO1_1__SD1_WP 0x20d5
MX51_PAD_GPIO1_0__GPIO1_0 0x100
MX51_PAD_GPIO1_1__GPIO1_1 0x100
>;
};

4
arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts
View file

@ -107,7 +107,7 @@
&esdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1 &pinctrl_esdhc1_cd>;
fsl,cd-controller;
cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
status = "okay";
};
@ -206,7 +206,7 @@
pinctrl_esdhc1_cd: esdhc1_cd {
fsl,pins = <
MX51_PAD_GPIO1_0__SD1_CD 0x20d5
MX51_PAD_GPIO1_0__GPIO1_0 0xd5
>;
};

38
arch/arm/boot/dts/imx53-m53evk.dts
View file

@ -21,27 +21,25 @@
<0xb0000000 0x20000000>;
};
soc {
display1: display@di1 {
compatible = "fsl,imx-parallel-display";
interface-pix-fmt = "bgr666";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu_disp1>;
display1: display@di1 {
compatible = "fsl,imx-parallel-display";
interface-pix-fmt = "bgr666";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu_disp1>;
display-timings {
800x480p60 {
native-mode;
clock-frequency = <31500000>;
hactive = <800>;
vactive = <480>;
hfront-porch = <40>;
hback-porch = <88>;
hsync-len = <128>;
vback-porch = <33>;
vfront-porch = <9>;
vsync-len = <3>;
vsync-active = <1>;
};
display-timings {
800x480p60 {
native-mode;
clock-frequency = <31500000>;
hactive = <800>;
vactive = <480>;
hfront-porch = <40>;
hback-porch = <88>;
hsync-len = <128>;
vback-porch = <33>;
vfront-porch = <9>;
vsync-len = <3>;
vsync-active = <1>;
};
};

10
arch/arm/boot/dts/imx6dl-hummingboard.dts
View file

@ -143,6 +143,14 @@
fsl,pins = <MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0>;
};
pinctrl_hummingboard_usbotg_id: hummingboard-usbotg-id {
/*
* Similar to pinctrl_usbotg_2, but we want it
* pulled down for a fixed host connection.
*/
fsl,pins = <MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059>;
};
pinctrl_hummingboard_usbotg_vbus: hummingboard-usbotg-vbus {
fsl,pins = <MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0>;
};
@ -178,6 +186,8 @@
};
&usbotg {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hummingboard_usbotg_id>;
vbus-supply = <&reg_usbotg_vbus>;
status = "okay";
};

2
arch/arm/boot/dts/imx6q-gw51xx.dts
View file

@ -11,7 +11,7 @@
/dts-v1/;
#include "imx6q.dtsi"
#include "imx6qdl-gw54xx.dtsi"
#include "imx6qdl-gw51xx.dtsi"
/ {
model = "Gateworks Ventana i.MX6 Quad GW51XX";

27
arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
View file

@ -12,6 +12,19 @@
pinctrl-0 = <&pinctrl_cubox_i_ir>;
};
pwmleds {
compatible = "pwm-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_cubox_i_pwm1>;
front {
active-low;
label = "imx6:red:front";
max-brightness = <248>;
pwms = <&pwm1 0 50000>;
};
};
regulators {
compatible = "simple-bus";
@ -109,6 +122,10 @@
>;
};
pinctrl_cubox_i_pwm1: cubox-i-pwm1-front-led {
fsl,pins = <MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b0>;
};
pinctrl_cubox_i_spdif: cubox-i-spdif {
fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x13091>;
};
@ -117,6 +134,14 @@
fsl,pins = <MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x4001b0b0>;
};
pinctrl_cubox_i_usbotg_id: cubox-i-usbotg-id {
/*
* The Cubox-i pulls this low, but as it's pointless
* leaving it as a pull-up, even if it is just 10uA.
*/
fsl,pins = <MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059>;
};
pinctrl_cubox_i_usbotg_vbus: cubox-i-usbotg-vbus {
fsl,pins = <MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x4001b0b0>;
};
@ -153,6 +178,8 @@
};
&usbotg {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_cubox_i_usbotg_id>;
vbus-supply = <&reg_usbotg_vbus>;
status = "okay";
};

2
arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
View file

@ -161,7 +161,7 @@
status = "okay";
pmic: ltc3676@3c {
compatible = "ltc,ltc3676";
compatible = "lltc,ltc3676";
reg = <0x3c>;
regulators {

4
arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
View file

@ -220,7 +220,7 @@
};
pmic: ltc3676@3c {
compatible = "ltc,ltc3676";
compatible = "lltc,ltc3676";
reg = <0x3c>;
regulators {
@ -288,7 +288,7 @@
codec: sgtl5000@0a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
clocks = <&clks 169>;
clocks = <&clks 201>;
VDDA-supply = <&reg_1p8v>;
VDDIO-supply = <&reg_3p3v>;
};

2
arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
View file

@ -234,7 +234,7 @@
};
pmic: ltc3676@3c {
compatible = "ltc,ltc3676";
compatible = "lltc,ltc3676";
reg = <0x3c>;
regulators {

13
arch/arm/boot/dts/imx6qdl-microsom.dtsi
View file

@ -10,14 +10,6 @@
MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
>;
};
pinctrl_microsom_usbotg: microsom-usbotg {
/*
* Similar to pinctrl_usbotg_2, but we want it
* pulled down for a fixed host connection.
*/
fsl,pins = <MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059>;
};
};
};
@ -26,8 +18,3 @@
pinctrl-0 = <&pinctrl_microsom_uart1>;
status = "okay";
};
&usbotg {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_microsom_usbotg>;
};

2
arch/arm/boot/dts/imx6sl.dtsi
View file

@ -686,7 +686,7 @@
compatible = "fsl,imx6sl-fec", "fsl,imx25-fec";
reg = <0x02188000 0x4000>;
interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_ENET_REF>,
clocks = <&clks IMX6SL_CLK_ENET>,
<&clks IMX6SL_CLK_ENET_REF>;
clock-names = "ipg", "ahb";
status = "disabled";

4
arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
View file

@ -105,7 +105,6 @@
compatible = "ethernet-phy-id0141.0cb0",
"ethernet-phy-ieee802.3-c22";
reg = <0>;
phy-connection-type = "rgmii-id";
};
ethphy1: ethernet-phy@1 {
@ -113,7 +112,6 @@
compatible = "ethernet-phy-id0141.0cb0",
"ethernet-phy-ieee802.3-c22";
reg = <1>;
phy-connection-type = "rgmii-id";
};
};
@ -121,6 +119,7 @@
status = "okay";
ethernet0-port@0 {
phy-handle = <&ethphy0>;
phy-connection-type = "rgmii-id";
};
};
@ -128,5 +127,6 @@
status = "okay";
ethernet1-port@0 {
phy-handle = <&ethphy1>;
phy-connection-type = "rgmii-id";
};
};

8
arch/arm/boot/dts/stih415.dtsi
View file

@ -169,8 +169,8 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mii0>;
clock-names = "stmmaceth";
clocks = <&clk_s_a1_ls CLK_GMAC0_PHY>;
clock-names = "stmmaceth", "sti-ethclk";
clocks = <&clk_s_a1_ls CLK_ICN_IF_2>, <&clk_s_a1_ls CLK_GMAC0_PHY>;
};
ethernet1: dwmac@fef08000 {
@ -192,8 +192,8 @@
reset-names = "stmmaceth";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mii1>;
clock-names = "stmmaceth";
clocks = <&clk_s_a0_ls CLK_ETH1_PHY>;
clock-names = "stmmaceth", "sti-ethclk";
clocks = <&clk_s_a0_ls CLK_ICN_REG>, <&clk_s_a0_ls CLK_ETH1_PHY>;
};
rc: rc@fe518000 {

0
arch/arm/boot/dts/stih416-b2020-revE.dts → arch/arm/boot/dts/stih416-b2020e.dts
View file

8
arch/arm/boot/dts/stih416.dtsi
View file

@ -175,8 +175,8 @@
reset-names = "stmmaceth";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mii0>;
clock-names = "stmmaceth";
clocks = <&clk_s_a1_ls CLK_GMAC0_PHY>;
clock-names = "stmmaceth", "sti-ethclk";
clocks = <&clk_s_a1_ls CLK_ICN_IF_2>, <&clk_s_a1_ls CLK_GMAC0_PHY>;
};
ethernet1: dwmac@fef08000 {
@ -197,8 +197,8 @@
reset-names = "stmmaceth";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mii1>;
clock-names = "stmmaceth";
clocks = <&clk_s_a0_ls CLK_ETH1_PHY>;
clock-names = "stmmaceth", "sti-ethclk";
clocks = <&clk_s_a0_ls CLK_ICN_REG>, <&clk_s_a0_ls CLK_ETH1_PHY>;
};
rc: rc@fe518000 {

1
arch/arm/configs/imx_v6_v7_defconfig
View file

@ -186,6 +186,7 @@ CONFIG_VIDEO_MX3=y
CONFIG_V4L_MEM2MEM_DRIVERS=y
CONFIG_VIDEO_CODA=y
CONFIG_SOC_CAMERA_OV2640=y
CONFIG_IMX_IPUV3_CORE=y
CONFIG_DRM=y
CONFIG_DRM_PANEL_SIMPLE=y
CONFIG_BACKLIGHT_LCD_SUPPORT=y

1
arch/arm/configs/multi_v7_defconfig
View file

@ -353,6 +353,7 @@ CONFIG_MFD_NVEC=y
CONFIG_KEYBOARD_NVEC=y
CONFIG_SERIO_NVEC_PS2=y
CONFIG_NVEC_POWER=y
CONFIG_QCOM_GSBI=y
CONFIG_COMMON_CLK_QCOM=y
CONFIG_MSM_GCC_8660=y
CONFIG_MSM_MMCC_8960=y

2
arch/arm/configs/mvebu_v7_defconfig
View file

@ -14,6 +14,7 @@ CONFIG_MACH_ARMADA_370=y
CONFIG_MACH_ARMADA_375=y
CONFIG_MACH_ARMADA_38X=y
CONFIG_MACH_ARMADA_XP=y
CONFIG_MACH_DOVE=y
CONFIG_NEON=y
# CONFIG_CACHE_L2X0 is not set
# CONFIG_SWP_EMULATE is not set
@ -52,6 +53,7 @@ CONFIG_INPUT_EVDEV=y
CONFIG_KEYBOARD_GPIO=y
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_I2C=y
CONFIG_SPI=y
CONFIG_SPI_ORION=y

8
arch/arm/mach-exynos/hotplug.c
View file

@ -46,13 +46,7 @@ static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
if (cpu == 1)
exynos_cpu_power_down(cpu);
/*
* here's the WFI
*/
asm(".word 0xe320f003\n"
:
:
: "memory", "cc");
wfi();
if (pen_release == cpu_logical_map(cpu)) {
/*

11
arch/arm/mach-exynos/mcpm-exynos.c
View file

@ -25,7 +25,6 @@
#define EXYNOS5420_CPUS_PER_CLUSTER 4
#define EXYNOS5420_NR_CLUSTERS 2
#define MCPM_BOOT_ADDR_OFFSET 0x1c
/*
* The common v7_exit_coherency_flush API could not be used because of the
@ -343,11 +342,13 @@ static int __init exynos_mcpm_init(void)
pr_info("Exynos MCPM support installed\n");
/*
* Future entries into the kernel can now go
* through the cluster entry vectors.
* U-Boot SPL is hardcoded to jump to the start of ns_sram_base_addr
* as part of secondary_cpu_start(). Let's redirect it to the
* mcpm_entry_point().
*/
__raw_writel(virt_to_phys(mcpm_entry_point),
ns_sram_base_addr + MCPM_BOOT_ADDR_OFFSET);
__raw_writel(0xe59f0000, ns_sram_base_addr); /* ldr r0, [pc, #0] */
__raw_writel(0xe12fff10, ns_sram_base_addr + 4); /* bx r0 */
__raw_writel(virt_to_phys(mcpm_entry_point), ns_sram_base_addr + 8);
iounmap(ns_sram_base_addr);

15
arch/arm/mach-exynos/pm.c
View file

@ -300,7 +300,7 @@ static int exynos_pm_suspend(void)
tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0);
__raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
if (!soc_is_exynos5250())
if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
exynos_cpu_save_register();
return 0;
@ -334,7 +334,7 @@ static void exynos_pm_resume(void)
if (exynos_pm_central_resume())
goto early_wakeup;
if (!soc_is_exynos5250())
if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
exynos_cpu_restore_register();
/* For release retention */
@ -353,7 +353,7 @@ static void exynos_pm_resume(void)
s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
if (!soc_is_exynos5250())
if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
scu_enable(S5P_VA_SCU);
early_wakeup:
@ -440,15 +440,18 @@ static int exynos_cpu_pm_notifier(struct notifier_block *self,
case CPU_PM_ENTER:
if (cpu == 0) {
exynos_pm_central_suspend();
exynos_cpu_save_register();
if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
exynos_cpu_save_register();
}
break;
case CPU_PM_EXIT:
if (cpu == 0) {
if (!soc_is_exynos5250())
if (read_cpuid_part_number() ==
ARM_CPU_PART_CORTEX_A9) {
scu_enable(S5P_VA_SCU);
exynos_cpu_restore_register();
exynos_cpu_restore_register();
}
exynos_pm_central_resume();
}
break;

1
arch/arm/mach-imx/clk-imx6sl.c
View file

@ -312,6 +312,7 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
clks[IMX6SL_CLK_ECSPI2] = imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2);
clks[IMX6SL_CLK_ECSPI3] = imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4);
clks[IMX6SL_CLK_ECSPI4] = imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6);
clks[IMX6SL_CLK_ENET] = imx_clk_gate2("enet", "ipg", base + 0x6c, 10);
clks[IMX6SL_CLK_EPIT1] = imx_clk_gate2("epit1", "perclk", base + 0x6c, 12);
clks[IMX6SL_CLK_EPIT2] = imx_clk_gate2("epit2", "perclk", base + 0x6c, 14);
clks[IMX6SL_CLK_EXTERN_AUDIO] = imx_clk_gate2("extern_audio", "extern_audio_podf", base + 0x6c, 16);

26
arch/arm/mach-integrator/integrator_ap.c
View file

@ -480,25 +480,18 @@ static const struct of_device_id ebi_match[] = {
static void __init ap_init_of(void)
{
unsigned long sc_dec;
struct device_node *root;
struct device_node *syscon;
struct device_node *ebi;
struct device *parent;
struct soc_device *soc_dev;
struct soc_device_attribute *soc_dev_attr;
u32 ap_sc_id;
int err;
int i;
/* Here we create an SoC device for the root node */
root = of_find_node_by_path("/");
if (!root)
return;
syscon = of_find_matching_node(root, ap_syscon_match);
syscon = of_find_matching_node(NULL, ap_syscon_match);
if (!syscon)
return;
ebi = of_find_matching_node(root, ebi_match);
ebi = of_find_matching_node(NULL, ebi_match);
if (!ebi)
return;
@ -509,19 +502,17 @@ static void __init ap_init_of(void)
if (!ebi_base)
return;
of_platform_populate(NULL, of_default_bus_match_table,
ap_auxdata_lookup, NULL);
ap_sc_id = readl(ap_syscon_base);
soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
if (!soc_dev_attr)
return;
err = of_property_read_string(root, "compatible",
&soc_dev_attr->soc_id);
if (err)
return;
err = of_property_read_string(root, "model", &soc_dev_attr->machine);
if (err)
return;
soc_dev_attr->soc_id = "XVC";
soc_dev_attr->machine = "Integrator/AP";
soc_dev_attr->family = "Integrator";
soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%c",
'A' + (ap_sc_id & 0x0f));
@ -536,9 +527,6 @@ static void __init ap_init_of(void)
parent = soc_device_to_device(soc_dev);
integrator_init_sysfs(parent, ap_sc_id);
of_platform_populate(root, of_default_bus_match_table,
ap_auxdata_lookup, parent);
sc_dec = readl(ap_syscon_base + INTEGRATOR_SC_DEC_OFFSET);
for (i = 0; i < 4; i++) {
struct lm_device *lmdev;

23
arch/arm/mach-integrator/integrator_cp.c
View file

@ -279,20 +279,13 @@ static const struct of_device_id intcp_syscon_match[] = {
static void __init intcp_init_of(void)
{
struct device_node *root;
struct device_node *cpcon;
struct device *parent;
struct soc_device *soc_dev;
struct soc_device_attribute *soc_dev_attr;
u32 intcp_sc_id;
int err;
/* Here we create an SoC device for the root node */
root = of_find_node_by_path("/");
if (!root)
return;
cpcon = of_find_matching_node(root, intcp_syscon_match);
cpcon = of_find_matching_node(NULL, intcp_syscon_match);
if (!cpcon)
return;
@ -300,19 +293,17 @@ static void __init intcp_init_of(void)
if (!intcp_con_base)
return;
of_platform_populate(NULL, of_default_bus_match_table,
intcp_auxdata_lookup, NULL);
intcp_sc_id = readl(intcp_con_base);
soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
if (!soc_dev_attr)
return;
err = of_property_read_string(root, "compatible",
&soc_dev_attr->soc_id);
if (err)
return;
err = of_property_read_string(root, "model", &soc_dev_attr->machine);
if (err)
return;
soc_dev_attr->soc_id = "XCV";
soc_dev_attr->machine = "Integrator/CP";
soc_dev_attr->family = "Integrator";
soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%c",
'A' + (intcp_sc_id & 0x0f));
@ -326,8 +317,6 @@ static void __init intcp_init_of(void)
parent = soc_device_to_device(soc_dev);
integrator_init_sysfs(parent, intcp_sc_id);
of_platform_populate(root, of_default_bus_match_table,
intcp_auxdata_lookup, parent);
}
static const char * intcp_dt_board_compat[] = {

2
arch/arm/mach-mvebu/Kconfig
View file

@ -10,6 +10,7 @@ menuconfig ARCH_MVEBU
select ZONE_DMA if ARM_LPAE
select ARCH_REQUIRE_GPIOLIB
select PCI_QUIRKS if PCI
select OF_ADDRESS_PCI
if ARCH_MVEBU
@ -17,6 +18,7 @@ config MACH_MVEBU_V7
bool
select ARMADA_370_XP_TIMER
select CACHE_L2X0
select ARM_CPU_SUSPEND
config MACH_ARMADA_370
bool "Marvell Armada 370 boards" if ARCH_MULTI_V7

9
drivers/clocksource/exynos_mct.c
View file

@ -153,13 +153,10 @@ static void exynos4_mct_write(unsigned int value, unsigned long offset)
}
/* Clocksource handling */
static void exynos4_mct_frc_start(u32 hi, u32 lo)
static void exynos4_mct_frc_start(void)
{
u32 reg;
exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L);
exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U);
reg = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
reg |= MCT_G_TCON_START;
exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
@ -181,7 +178,7 @@ static cycle_t exynos4_frc_read(struct clocksource *cs)
static void exynos4_frc_resume(struct clocksource *cs)
{
exynos4_mct_frc_start(0, 0);
exynos4_mct_frc_start();
}
struct clocksource mct_frc = {
@ -200,7 +197,7 @@ static u64 notrace exynos4_read_sched_clock(void)
static void __init exynos4_clocksource_init(void)
{
exynos4_mct_frc_start(0, 0);
exynos4_mct_frc_start();
if (clocksource_register_hz(&mct_frc, clk_rate))
panic("%s: can't register clocksource\n", mct_frc.name);

2
drivers/misc/Kconfig
View file

@ -54,7 +54,7 @@ config AD525X_DPOT_SPI
config ATMEL_PWM
tristate "Atmel AT32/AT91 PWM support"
depends on HAVE_CLK
depends on AVR32 || AT91SAM9263 || AT91SAM9RL || AT91SAM9G45
depends on AVR32 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_AT91SAM9G45
help
This option enables device driver support for the PWM channels
on certain Atmel processors. Pulse Width Modulation is used for

2
drivers/tty/serial/msm_serial.c
View file

@ -991,7 +991,7 @@ static const struct of_device_id msm_uartdm_table[] = {
{ }
};
static int __init msm_serial_probe(struct platform_device *pdev)
static int msm_serial_probe(struct platform_device *pdev)
{
struct msm_port *msm_port;
struct resource *resource;

3
include/dt-bindings/clock/imx6sl-clock.h
View file

@ -145,6 +145,7 @@
#define IMX6SL_CLK_USDHC4 132
#define IMX6SL_CLK_PLL4_AUDIO_DIV 133
#define IMX6SL_CLK_SPBA 134
#define IMX6SL_CLK_END 135
#define IMX6SL_CLK_ENET 135
#define IMX6SL_CLK_END 136
#endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */

1
include/dt-bindings/clock/stih415-clks.h
View file

@ -10,6 +10,7 @@
#define CLK_ETH1_PHY 4
/* CLOCKGEN A1 */
#define CLK_ICN_IF_2 0
#define CLK_GMAC0_PHY 3
#endif

1
include/dt-bindings/clock/stih416-clks.h
View file

@ -10,6 +10,7 @@
#define CLK_ETH1_PHY 4
/* CLOCKGEN A1 */
#define CLK_ICN_IF_2 0
#define CLK_GMAC0_PHY 3
#endif