Techwizz/kernel-fxtec-pro1x
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

MIPS: Hibernation: Remove SMP TLB and cacheflushing code.

Browse source 
We can't perform any flushes on SMP from swsusp_arch_resume because
interrupts are disabled.  A cross-CPU flush is unnecessary anyway
because all but the local CPU have already been disabled.  A local
flush is not needed either because we didn't change any mappings.  So
just delete the code.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle 2009-06-19 15:01:44 +01:00
parent 631330f584
commit 44eeab6741
1 changed files with 0 additions and 9 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

9
arch/mips/power/hibernate.S
View file

@ -43,15 +43,6 @@ LEAF(swsusp_arch_resume)
bne t1, t3, 1b
PTR_L t0, PBE_NEXT(t0)
bnez t0, 0b
/* flush caches to make sure context is in memory */
PTR_L t0, __flush_cache_all
jalr t0
/* flush tlb entries */
#ifdef CONFIG_SMP
jal flush_tlb_all
#else
jal local_flush_tlb_all
#endif
PTR_LA t0, saved_regs
PTR_L ra, PT_R31(t0)
PTR_L sp, PT_R29(t0)