[MIPS] Treat R14000 like R10000.
Signed-off-by: Joshua Kinard <kumba@gentoo.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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714bfad60f
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44d921b246
6 changed files with 19 additions and 1 deletions
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@ -433,6 +433,15 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
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MIPS_CPU_LLSC;
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c->tlbsize = 64;
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break;
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case PRID_IMP_R14000:
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c->cputype = CPU_R14000;
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c->isa_level = MIPS_CPU_ISA_IV;
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c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
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MIPS_CPU_FPU | MIPS_CPU_32FPR |
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MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
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MIPS_CPU_LLSC;
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c->tlbsize = 64;
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break;
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}
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}
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@ -42,6 +42,7 @@ static const char *cpu_name[] = {
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[CPU_R8000] = "R8000",
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[CPU_R10000] = "R10000",
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[CPU_R12000] = "R12000",
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[CPU_R14000] = "R14000",
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[CPU_R4300] = "R4300",
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[CPU_R4650] = "R4650",
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[CPU_R4700] = "R4700",
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@ -335,6 +335,7 @@ static inline void local_r4k___flush_cache_all(void * args)
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case CPU_R4400MC:
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case CPU_R10000:
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case CPU_R12000:
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case CPU_R14000:
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r4k_blast_scache();
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}
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}
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@ -833,6 +834,7 @@ static void __init probe_pcache(void)
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case CPU_R10000:
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case CPU_R12000:
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case CPU_R14000:
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icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29));
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c->icache.linesz = 64;
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c->icache.ways = 2;
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@ -986,6 +988,7 @@ static void __init probe_pcache(void)
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c->dcache.flags |= MIPS_CACHE_PINDEX;
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case CPU_R10000:
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case CPU_R12000:
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case CPU_R14000:
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case CPU_SB1:
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break;
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case CPU_24K:
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@ -1113,6 +1116,7 @@ static void __init setup_scache(void)
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case CPU_R10000:
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case CPU_R12000:
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case CPU_R14000:
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scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16);
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c->scache.linesz = 64 << ((config >> 13) & 1);
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c->scache.ways = 2;
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@ -357,6 +357,7 @@ void __init build_clear_page(void)
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case CPU_R10000:
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case CPU_R12000:
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case CPU_R14000:
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pref_src_mode = Pref_LoadStreamed;
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pref_dst_mode = Pref_StoreStreamed;
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break;
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@ -875,6 +875,7 @@ static __init void build_tlb_write_entry(u32 **p, struct label **l,
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case CPU_R10000:
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case CPU_R12000:
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case CPU_R14000:
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case CPU_4KC:
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case CPU_SB1:
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case CPU_SB1A:
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@ -51,6 +51,7 @@
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#define PRID_IMP_R4300 0x0b00
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#define PRID_IMP_VR41XX 0x0c00
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#define PRID_IMP_R12000 0x0e00
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#define PRID_IMP_R14000 0x0f00
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#define PRID_IMP_R8000 0x1000
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#define PRID_IMP_PR4450 0x1200
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#define PRID_IMP_R4600 0x2000
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@ -198,7 +199,8 @@
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#define CPU_PR4450 61
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#define CPU_SB1A 62
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#define CPU_74K 63
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#define CPU_LAST 63
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#define CPU_R14000 64
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#define CPU_LAST 64
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/*
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* ISA Level encodings
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