arm/arm64: KVM: rework MPIDR assignment and add accessors
The virtual MPIDR registers (containing topology information) for the guest are currently mapped linearily to the vcpu_id. Improve this mapping for arm64 by using three levels to not artificially limit the number of vCPUs. To help this, change and rename the kvm_vcpu_get_mpidr() function to mask off the non-affinity bits in the MPIDR register. Also add an accessor to later allow easier access to a vCPU with a given MPIDR. Use this new accessor in the PSCI emulation. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
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7 changed files with 39 additions and 18 deletions
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@ -23,6 +23,7 @@
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#include <asm/kvm_asm.h>
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#include <asm/kvm_mmio.h>
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#include <asm/kvm_arm.h>
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#include <asm/cputype.h>
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unsigned long *vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num);
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unsigned long *vcpu_spsr(struct kvm_vcpu *vcpu);
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@ -167,9 +168,9 @@ static inline u32 kvm_vcpu_hvc_get_imm(struct kvm_vcpu *vcpu)
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return kvm_vcpu_get_hsr(vcpu) & HSR_HVC_IMM_MASK;
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}
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static inline unsigned long kvm_vcpu_get_mpidr(struct kvm_vcpu *vcpu)
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static inline unsigned long kvm_vcpu_get_mpidr_aff(struct kvm_vcpu *vcpu)
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{
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return vcpu->arch.cp15[c0_MPIDR];
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return vcpu->arch.cp15[c0_MPIDR] & MPIDR_HWID_BITMASK;
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}
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static inline void kvm_vcpu_set_be(struct kvm_vcpu *vcpu)
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@ -236,6 +236,8 @@ int kvm_perf_teardown(void);
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void kvm_mmu_wp_memory_region(struct kvm *kvm, int slot);
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struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr);
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static inline void kvm_arch_hardware_disable(void) {}
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static inline void kvm_arch_hardware_unsetup(void) {}
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static inline void kvm_arch_sync_events(struct kvm *kvm) {}
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@ -1075,6 +1075,19 @@ static void check_kvm_target_cpu(void *ret)
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*(int *)ret = kvm_target_cpu();
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}
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struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr)
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{
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struct kvm_vcpu *vcpu;
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int i;
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mpidr &= MPIDR_HWID_BITMASK;
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kvm_for_each_vcpu(i, vcpu, kvm) {
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if (mpidr == kvm_vcpu_get_mpidr_aff(vcpu))
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return vcpu;
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}
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return NULL;
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}
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/**
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* Initialize Hyp-mode and memory mappings on all CPUs.
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*/
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@ -22,6 +22,7 @@
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#include <asm/cputype.h>
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#include <asm/kvm_emulate.h>
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#include <asm/kvm_psci.h>
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#include <asm/kvm_host.h>
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/*
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* This is an implementation of the Power State Coordination Interface
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@ -66,25 +67,17 @@ static void kvm_psci_vcpu_off(struct kvm_vcpu *vcpu)
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static unsigned long kvm_psci_vcpu_on(struct kvm_vcpu *source_vcpu)
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{
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struct kvm *kvm = source_vcpu->kvm;
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struct kvm_vcpu *vcpu = NULL, *tmp;
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struct kvm_vcpu *vcpu = NULL;
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wait_queue_head_t *wq;
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unsigned long cpu_id;
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unsigned long context_id;
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unsigned long mpidr;
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phys_addr_t target_pc;
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int i;
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cpu_id = *vcpu_reg(source_vcpu, 1);
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cpu_id = *vcpu_reg(source_vcpu, 1) & MPIDR_HWID_BITMASK;
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if (vcpu_mode_is_32bit(source_vcpu))
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cpu_id &= ~((u32) 0);
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kvm_for_each_vcpu(i, tmp, kvm) {
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mpidr = kvm_vcpu_get_mpidr(tmp);
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if ((mpidr & MPIDR_HWID_BITMASK) == (cpu_id & MPIDR_HWID_BITMASK)) {
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vcpu = tmp;
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break;
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}
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}
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vcpu = kvm_mpidr_to_vcpu(kvm, cpu_id);
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/*
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* Make sure the caller requested a valid CPU and that the CPU is
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@ -155,7 +148,7 @@ static unsigned long kvm_psci_vcpu_affinity_info(struct kvm_vcpu *vcpu)
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* then ON else OFF
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*/
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kvm_for_each_vcpu(i, tmp, kvm) {
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mpidr = kvm_vcpu_get_mpidr(tmp);
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mpidr = kvm_vcpu_get_mpidr_aff(tmp);
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if (((mpidr & target_affinity_mask) == target_affinity) &&
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!tmp->arch.pause) {
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return PSCI_0_2_AFFINITY_LEVEL_ON;
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@ -27,6 +27,7 @@
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#include <asm/kvm_arm.h>
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#include <asm/kvm_mmio.h>
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#include <asm/ptrace.h>
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#include <asm/cputype.h>
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unsigned long *vcpu_reg32(const struct kvm_vcpu *vcpu, u8 reg_num);
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unsigned long *vcpu_spsr32(const struct kvm_vcpu *vcpu);
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@ -192,9 +193,9 @@ static inline u8 kvm_vcpu_trap_get_fault_type(const struct kvm_vcpu *vcpu)
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return kvm_vcpu_get_hsr(vcpu) & ESR_EL2_FSC_TYPE;
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}
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static inline unsigned long kvm_vcpu_get_mpidr(struct kvm_vcpu *vcpu)
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static inline unsigned long kvm_vcpu_get_mpidr_aff(struct kvm_vcpu *vcpu)
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{
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return vcpu_sys_reg(vcpu, MPIDR_EL1);
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return vcpu_sys_reg(vcpu, MPIDR_EL1) & MPIDR_HWID_BITMASK;
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}
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static inline void kvm_vcpu_set_be(struct kvm_vcpu *vcpu)
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@ -207,6 +207,8 @@ int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *run,
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int kvm_perf_init(void);
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int kvm_perf_teardown(void);
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struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr);
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static inline void __cpu_init_hyp_mode(phys_addr_t boot_pgd_ptr,
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phys_addr_t pgd_ptr,
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unsigned long hyp_stack_ptr,
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@ -252,10 +252,19 @@ static void reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
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static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
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{
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u64 mpidr;
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/*
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* Simply map the vcpu_id into the Aff0 field of the MPIDR.
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* Map the vcpu_id into the first three affinity level fields of
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* the MPIDR. We limit the number of VCPUs in level 0 due to a
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* limitation to 16 CPUs in that level in the ICC_SGIxR registers
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* of the GICv3 to be able to address each CPU directly when
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* sending IPIs.
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*/
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vcpu_sys_reg(vcpu, MPIDR_EL1) = (1UL << 31) | (vcpu->vcpu_id & 0xff);
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mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0);
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mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1);
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mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2);
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vcpu_sys_reg(vcpu, MPIDR_EL1) = (1ULL << 31) | mpidr;
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}
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/* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
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