gpio: msm: Add device tree and irqdomain support for gpio-msm-v2
This cleans up the gpio-msm-v2 driver of all the global define usage. The number of gpios are now defined in the device tree. This enables adding irqdomain support as well. Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org> Acked-by: Grant Likely <grant.likely@linaro.org> Signed-off-by: David Brown <davidb@codeaurora.org>
This commit is contained in:
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eda9dcfa56
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43f68444bc
5 changed files with 167 additions and 83 deletions
26
Documentation/devicetree/bindings/gpio/gpio-msm.txt
Normal file
26
Documentation/devicetree/bindings/gpio/gpio-msm.txt
Normal file
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@ -0,0 +1,26 @@
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MSM GPIO controller bindings
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Required properties:
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- compatible:
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- "qcom,msm-gpio" for MSM controllers
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- #gpio-cells : Should be two.
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- first cell is the pin number
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- second cell is used to specify optional parameters (unused)
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- gpio-controller : Marks the device node as a GPIO controller.
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- #interrupt-cells : Should be 2.
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- interrupt-controller: Mark the device node as an interrupt controller
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- interrupts : Specify the TLMM summary interrupt number
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- ngpio : Specify the number of MSM GPIOs
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Example:
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msmgpio: gpio@fd510000 {
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compatible = "qcom,msm-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0xfd510000 0x4000>;
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interrupts = <0 208 0>;
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ngpio = <150>;
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};
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@ -26,6 +26,17 @@
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cpu-offset = <0x40000>;
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};
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msmgpio: gpio@800000 {
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compatible = "qcom,msm-gpio";
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reg = <0x00800000 0x1000>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpio = <173>;
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interrupts = <0 32 0x4>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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serial@19c400000 {
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compatible = "qcom,msm-hsuart", "qcom,msm-uart";
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reg = <0x19c40000 0x1000>,
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@ -26,6 +26,17 @@
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cpu-offset = <0x80000>;
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};
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msmgpio: gpio@fd510000 {
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compatible = "qcom,msm-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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ngpio = <150>;
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interrupts = <0 32 0x4>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0xfd510000 0x4000>;
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};
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serial@19c400000 {
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compatible = "qcom,msm-hsuart", "qcom,msm-uart";
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reg = <0x16440000 0x1000>,
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@ -165,7 +165,7 @@ config GPIO_MSM_V1
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config GPIO_MSM_V2
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tristate "Qualcomm MSM GPIO v2"
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depends on GPIOLIB && ARCH_MSM
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depends on GPIOLIB && OF && ARCH_MSM
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help
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Say yes here to support the GPIO interface on ARM v7 based
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Qualcomm MSM chips. Most of the pins on the MSM can be
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@ -19,17 +19,21 @@
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#include <linux/bitmap.h>
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#include <linux/bitops.h>
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#include <linux/err.h>
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#include <linux/gpio.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#include <linux/slab.h>
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#include <mach/msm_iomap.h>
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#define MAX_NR_GPIO 300
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/* Bits of interest in the GPIO_IN_OUT register.
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*/
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@ -76,13 +80,6 @@ enum {
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TARGET_PROC_NONE = 7,
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};
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#define GPIO_INTR_CFG_SU(gpio) (MSM_TLMM_BASE + 0x0400 + (0x04 * (gpio)))
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#define GPIO_CONFIG(gpio) (MSM_TLMM_BASE + 0x1000 + (0x10 * (gpio)))
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#define GPIO_IN_OUT(gpio) (MSM_TLMM_BASE + 0x1004 + (0x10 * (gpio)))
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#define GPIO_INTR_CFG(gpio) (MSM_TLMM_BASE + 0x1008 + (0x10 * (gpio)))
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#define GPIO_INTR_STATUS(gpio) (MSM_TLMM_BASE + 0x100c + (0x10 * (gpio)))
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/**
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* struct msm_gpio_dev: the MSM8660 SoC GPIO device structure
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*
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@ -101,11 +98,27 @@ enum {
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*/
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struct msm_gpio_dev {
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struct gpio_chip gpio_chip;
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DECLARE_BITMAP(enabled_irqs, NR_GPIO_IRQS);
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DECLARE_BITMAP(wake_irqs, NR_GPIO_IRQS);
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DECLARE_BITMAP(dual_edge_irqs, NR_GPIO_IRQS);
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DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO);
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DECLARE_BITMAP(wake_irqs, MAX_NR_GPIO);
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DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO);
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struct irq_domain *domain;
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unsigned int summary_irq;
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void __iomem *msm_tlmm_base;
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};
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struct msm_gpio_dev msm_gpio;
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#define GPIO_INTR_CFG_SU(gpio) (msm_gpio.msm_tlmm_base + 0x0400 + \
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(0x04 * (gpio)))
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#define GPIO_CONFIG(gpio) (msm_gpio.msm_tlmm_base + 0x1000 + \
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(0x10 * (gpio)))
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#define GPIO_IN_OUT(gpio) (msm_gpio.msm_tlmm_base + 0x1004 + \
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(0x10 * (gpio)))
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#define GPIO_INTR_CFG(gpio) (msm_gpio.msm_tlmm_base + 0x1008 + \
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(0x10 * (gpio)))
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#define GPIO_INTR_STATUS(gpio) (msm_gpio.msm_tlmm_base + 0x100c + \
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(0x10 * (gpio)))
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static DEFINE_SPINLOCK(tlmm_lock);
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static inline struct msm_gpio_dev *to_msm_gpio_dev(struct gpio_chip *chip)
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@ -168,27 +181,19 @@ static void msm_gpio_free(struct gpio_chip *chip, unsigned offset)
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static int msm_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
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{
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return MSM_GPIO_TO_INT(chip->base + offset);
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struct msm_gpio_dev *g_dev = to_msm_gpio_dev(chip);
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struct irq_domain *domain = g_dev->domain;
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return irq_create_mapping(domain, offset);
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}
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static inline int msm_irq_to_gpio(struct gpio_chip *chip, unsigned irq)
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{
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return irq - MSM_GPIO_TO_INT(chip->base);
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struct irq_data *irq_data = irq_get_irq_data(irq);
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return irq_data->hwirq;
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}
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static struct msm_gpio_dev msm_gpio = {
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.gpio_chip = {
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.base = 0,
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.ngpio = NR_GPIO_IRQS,
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.direction_input = msm_gpio_direction_input,
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.direction_output = msm_gpio_direction_output,
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.get = msm_gpio_get,
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.set = msm_gpio_set,
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.to_irq = msm_gpio_to_irq,
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.request = msm_gpio_request,
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.free = msm_gpio_free,
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},
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};
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/* For dual-edge interrupts in software, since the hardware has no
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* such support:
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@ -226,9 +231,9 @@ static void msm_gpio_update_dual_edge_pos(unsigned gpio)
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if (intstat || val == val2)
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return;
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} while (loop_limit-- > 0);
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pr_err("dual-edge irq failed to stabilize, "
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pr_err("%s: dual-edge irq failed to stabilize, "
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"interrupts dropped. %#08x != %#08x\n",
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val, val2);
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__func__, val, val2);
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}
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static void msm_gpio_irq_ack(struct irq_data *d)
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@ -315,10 +320,10 @@ static void msm_summary_irq_handler(unsigned int irq, struct irq_desc *desc)
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chained_irq_enter(chip, desc);
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for_each_set_bit(i, msm_gpio.enabled_irqs, NR_GPIO_IRQS) {
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for_each_set_bit(i, msm_gpio.enabled_irqs, MAX_NR_GPIO) {
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if (readl(GPIO_INTR_STATUS(i)) & BIT(INTR_STATUS))
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generic_handle_irq(msm_gpio_to_irq(&msm_gpio.gpio_chip,
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i));
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generic_handle_irq(irq_find_mapping(msm_gpio.domain,
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i));
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}
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chained_irq_exit(chip, desc);
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@ -329,13 +334,13 @@ static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
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int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq);
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if (on) {
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if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS))
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irq_set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 1);
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if (bitmap_empty(msm_gpio.wake_irqs, MAX_NR_GPIO))
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irq_set_irq_wake(msm_gpio.summary_irq, 1);
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set_bit(gpio, msm_gpio.wake_irqs);
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} else {
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clear_bit(gpio, msm_gpio.wake_irqs);
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if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS))
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irq_set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 0);
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if (bitmap_empty(msm_gpio.wake_irqs, MAX_NR_GPIO))
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irq_set_irq_wake(msm_gpio.summary_irq, 0);
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}
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return 0;
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.irq_set_wake = msm_gpio_irq_set_wake,
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};
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static int msm_gpio_probe(struct platform_device *dev)
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static struct lock_class_key msm_gpio_lock_class;
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static int msm_gpio_irq_domain_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hwirq)
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{
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int i, irq, ret;
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irq_set_lockdep_class(irq, &msm_gpio_lock_class);
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irq_set_chip_and_handler(irq, &msm_gpio_irq_chip,
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handle_level_irq);
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set_irq_flags(irq, IRQF_VALID);
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bitmap_zero(msm_gpio.enabled_irqs, NR_GPIO_IRQS);
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bitmap_zero(msm_gpio.wake_irqs, NR_GPIO_IRQS);
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bitmap_zero(msm_gpio.dual_edge_irqs, NR_GPIO_IRQS);
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msm_gpio.gpio_chip.label = dev->name;
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ret = gpiochip_add(&msm_gpio.gpio_chip);
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if (ret < 0)
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return ret;
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for (i = 0; i < msm_gpio.gpio_chip.ngpio; ++i) {
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irq = msm_gpio_to_irq(&msm_gpio.gpio_chip, i);
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irq_set_chip_and_handler(irq, &msm_gpio_irq_chip,
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handle_level_irq);
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set_irq_flags(irq, IRQF_VALID);
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}
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irq_set_chained_handler(TLMM_SCSS_SUMMARY_IRQ,
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msm_summary_irq_handler);
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return 0;
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}
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static const struct irq_domain_ops msm_gpio_irq_domain_ops = {
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.xlate = irq_domain_xlate_twocell,
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.map = msm_gpio_irq_domain_map,
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};
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static int msm_gpio_probe(struct platform_device *pdev)
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{
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int ret, ngpio;
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struct resource *res;
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if (!of_property_read_u32(pdev->dev.of_node, "ngpio", &ngpio)) {
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dev_err(&pdev->dev, "%s: ngpio property missing\n", __func__);
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return -EINVAL;
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}
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if (ngpio > MAX_NR_GPIO)
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WARN(1, "ngpio exceeds the MAX_NR_GPIO. Increase MAX_NR_GPIO\n");
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bitmap_zero(msm_gpio.enabled_irqs, MAX_NR_GPIO);
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bitmap_zero(msm_gpio.wake_irqs, MAX_NR_GPIO);
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bitmap_zero(msm_gpio.dual_edge_irqs, MAX_NR_GPIO);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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msm_gpio.msm_tlmm_base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(msm_gpio.msm_tlmm_base))
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return PTR_ERR(msm_gpio.msm_tlmm_base);
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msm_gpio.gpio_chip.ngpio = ngpio;
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msm_gpio.gpio_chip.label = pdev->name;
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msm_gpio.gpio_chip.dev = &pdev->dev;
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msm_gpio.gpio_chip.base = 0;
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msm_gpio.gpio_chip.direction_input = msm_gpio_direction_input;
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msm_gpio.gpio_chip.direction_output = msm_gpio_direction_output;
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msm_gpio.gpio_chip.get = msm_gpio_get;
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msm_gpio.gpio_chip.set = msm_gpio_set;
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msm_gpio.gpio_chip.to_irq = msm_gpio_to_irq;
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msm_gpio.gpio_chip.request = msm_gpio_request;
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msm_gpio.gpio_chip.free = msm_gpio_free;
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ret = gpiochip_add(&msm_gpio.gpio_chip);
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if (ret < 0) {
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dev_err(&pdev->dev, "gpiochip_add failed with error %d\n", ret);
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return ret;
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}
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msm_gpio.summary_irq = platform_get_irq(pdev, 0);
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if (msm_gpio.summary_irq < 0) {
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dev_err(&pdev->dev, "No Summary irq defined for msmgpio\n");
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return msm_gpio.summary_irq;
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}
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msm_gpio.domain = irq_domain_add_linear(pdev->dev.of_node, ngpio,
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&msm_gpio_irq_domain_ops,
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&msm_gpio);
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if (!msm_gpio.domain)
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return -ENODEV;
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irq_set_chained_handler(msm_gpio.summary_irq, msm_summary_irq_handler);
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return 0;
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}
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static struct of_device_id msm_gpio_of_match[] = {
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{ .compatible = "qcom,msm-gpio", },
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{ },
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};
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static int msm_gpio_remove(struct platform_device *dev)
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{
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int ret = gpiochip_remove(&msm_gpio.gpio_chip);
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if (ret < 0)
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return ret;
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irq_set_handler(TLMM_SCSS_SUMMARY_IRQ, NULL);
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irq_set_handler(msm_gpio.summary_irq, NULL);
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return 0;
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}
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.driver = {
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.name = "msmgpio",
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.owner = THIS_MODULE,
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.of_match_table = msm_gpio_of_match,
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},
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};
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static struct platform_device msm_device_gpio = {
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.name = "msmgpio",
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.id = -1,
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};
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static int __init msm_gpio_init(void)
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{
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int rc;
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rc = platform_driver_register(&msm_gpio_driver);
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if (!rc) {
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rc = platform_device_register(&msm_device_gpio);
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if (rc)
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platform_driver_unregister(&msm_gpio_driver);
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}
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return rc;
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}
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static void __exit msm_gpio_exit(void)
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{
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platform_device_unregister(&msm_device_gpio);
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platform_driver_unregister(&msm_gpio_driver);
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}
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postcore_initcall(msm_gpio_init);
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module_exit(msm_gpio_exit);
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module_platform_driver(msm_gpio_driver)
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MODULE_AUTHOR("Gregory Bean <gbean@codeaurora.org>");
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MODULE_DESCRIPTION("Driver for Qualcomm MSM TLMMv2 SoC GPIOs");
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