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drm/i915: Work around gen7 BLT ring synchronization issues.

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Previous to this commit, testing easily reproduced a failure where the
seqno would apparently arrive after the IRQ associated with it, with test programs as simple as:

for (;;) {
    glCopyPixels(0, 0, 1, 1);
    glFinish();
}

Various workarounds we've seen for previous generations didn't work to
fix this issue, so until new information comes in, replace the IRQ
waits on the BLT ring with polling.

Signed-off-by: Eric Anholt <eric@anholt.net>
Tested-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Keith Packard <keithp@keithp.com>
This commit is contained in:
Eric Anholt 2011-12-22 14:55:00 -08:00 committed by Keith Packard
parent 7ea29b13e5
commit 42ff6572e5
1 changed files with 14 additions and 0 deletions
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14
drivers/gpu/drm/i915/intel_ringbuffer.c
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@ -791,6 +791,17 @@ ring_add_request(struct intel_ring_buffer *ring,
return 0;
}
static bool
gen7_blt_ring_get_irq(struct intel_ring_buffer *ring)
{
/* The BLT ring on IVB appears to have broken synchronization
* between the seqno write and the interrupt, so that the
* interrupt appears first. Returning false here makes
* i915_wait_request() do a polling loop, instead.
*/
return false;
}
static bool
gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
{
@ -1557,5 +1568,8 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
*ring = gen6_blt_ring;
if (IS_GEN7(dev))
ring->irq_get = gen7_blt_ring_get_irq;
return intel_init_ring_buffer(dev, ring);
}