tg3: Consolidate autoneg advertisement setup code
Autonegotiation setup has gotten a little more complicated since the tg3 driver was created. This patch consolidates autoneg setup into one routine and modifies the call sites accordingly. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Reviewed-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Matt Carlson
David S. Miller
parent
b0c5943f1c
commit
42b64a450b
1 changed files with 100 additions and 119 deletions
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@ -2929,102 +2929,54 @@ static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8
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}
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}
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static void tg3_phy_copper_begin(struct tg3 *tp)
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static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
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{
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u32 new_adv;
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int i;
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int err = 0;
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u32 val, new_adv;
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if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
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/* Entering low power mode. Disable gigabit and
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* 100baseT advertisements.
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*/
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tg3_writephy(tp, MII_TG3_CTRL, 0);
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new_adv = ADVERTISE_CSMA;
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if (advertise & ADVERTISED_10baseT_Half)
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new_adv |= ADVERTISE_10HALF;
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if (advertise & ADVERTISED_10baseT_Full)
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new_adv |= ADVERTISE_10FULL;
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if (advertise & ADVERTISED_100baseT_Half)
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new_adv |= ADVERTISE_100HALF;
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if (advertise & ADVERTISED_100baseT_Full)
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new_adv |= ADVERTISE_100FULL;
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new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
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ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
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if (tg3_flag(tp, WOL_SPEED_100MB))
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new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
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new_adv |= tg3_advert_flowctrl_1000T(flowctrl);
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tg3_writephy(tp, MII_ADVERTISE, new_adv);
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} else if (tp->link_config.speed == SPEED_INVALID) {
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if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
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tp->link_config.advertising &=
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~(ADVERTISED_1000baseT_Half |
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ADVERTISED_1000baseT_Full);
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err = tg3_writephy(tp, MII_ADVERTISE, new_adv);
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if (err)
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goto done;
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new_adv = ADVERTISE_CSMA;
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if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
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new_adv |= ADVERTISE_10HALF;
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if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
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new_adv |= ADVERTISE_10FULL;
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if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
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new_adv |= ADVERTISE_100HALF;
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if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
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new_adv |= ADVERTISE_100FULL;
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if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
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goto done;
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new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
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new_adv = 0;
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if (advertise & ADVERTISED_1000baseT_Half)
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new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
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if (advertise & ADVERTISED_1000baseT_Full)
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new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
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tg3_writephy(tp, MII_ADVERTISE, new_adv);
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if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
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tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
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new_adv |= (MII_TG3_CTRL_AS_MASTER |
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MII_TG3_CTRL_ENABLE_AS_MASTER);
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if (tp->link_config.advertising &
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(ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
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new_adv = 0;
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if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
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new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
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if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
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new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
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if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY) &&
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(tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
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tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
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new_adv |= (MII_TG3_CTRL_AS_MASTER |
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MII_TG3_CTRL_ENABLE_AS_MASTER);
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tg3_writephy(tp, MII_TG3_CTRL, new_adv);
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} else {
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tg3_writephy(tp, MII_TG3_CTRL, 0);
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}
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} else {
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new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
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new_adv |= ADVERTISE_CSMA;
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err = tg3_writephy(tp, MII_TG3_CTRL, new_adv);
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if (err)
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goto done;
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/* Asking for a specific link mode. */
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if (tp->link_config.speed == SPEED_1000) {
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tg3_writephy(tp, MII_ADVERTISE, new_adv);
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if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
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goto done;
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if (tp->link_config.duplex == DUPLEX_FULL)
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new_adv = MII_TG3_CTRL_ADV_1000_FULL;
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else
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new_adv = MII_TG3_CTRL_ADV_1000_HALF;
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if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
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tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
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new_adv |= (MII_TG3_CTRL_AS_MASTER |
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MII_TG3_CTRL_ENABLE_AS_MASTER);
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} else {
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if (tp->link_config.speed == SPEED_100) {
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if (tp->link_config.duplex == DUPLEX_FULL)
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new_adv |= ADVERTISE_100FULL;
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else
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new_adv |= ADVERTISE_100HALF;
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} else {
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if (tp->link_config.duplex == DUPLEX_FULL)
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new_adv |= ADVERTISE_10FULL;
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else
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new_adv |= ADVERTISE_10HALF;
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}
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tg3_writephy(tp, MII_ADVERTISE, new_adv);
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tw32(TG3_CPMU_EEE_MODE,
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tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
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new_adv = 0;
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}
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tg3_writephy(tp, MII_TG3_CTRL, new_adv);
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}
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if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
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u32 val;
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tw32(TG3_CPMU_EEE_MODE,
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tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
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TG3_PHY_AUXCTL_SMDSP_ENABLE(tp);
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err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp);
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if (!err) {
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u32 err2;
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switch (GET_ASIC_REV(tp->pci_chip_rev_id)) {
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case ASIC_REV_5717:
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@ -3041,19 +2993,66 @@ static void tg3_phy_copper_begin(struct tg3 *tp)
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}
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val = 0;
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if (tp->link_config.autoneg == AUTONEG_ENABLE) {
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/* Advertise 100-BaseTX EEE ability */
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if (tp->link_config.advertising &
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ADVERTISED_100baseT_Full)
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val |= MDIO_AN_EEE_ADV_100TX;
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/* Advertise 1000-BaseT EEE ability */
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if (tp->link_config.advertising &
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ADVERTISED_1000baseT_Full)
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val |= MDIO_AN_EEE_ADV_1000T;
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}
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tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
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/* Advertise 100-BaseTX EEE ability */
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if (advertise & ADVERTISED_100baseT_Full)
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val |= MDIO_AN_EEE_ADV_100TX;
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/* Advertise 1000-BaseT EEE ability */
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if (advertise & ADVERTISED_1000baseT_Full)
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val |= MDIO_AN_EEE_ADV_1000T;
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err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
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TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
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err2 = TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
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if (!err)
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err = err2;
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}
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done:
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return err;
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}
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static void tg3_phy_copper_begin(struct tg3 *tp)
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{
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u32 new_adv;
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int i;
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if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
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new_adv = ADVERTISED_10baseT_Half |
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ADVERTISED_10baseT_Full;
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if (tg3_flag(tp, WOL_SPEED_100MB))
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new_adv |= ADVERTISED_100baseT_Half |
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ADVERTISED_100baseT_Full;
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tg3_phy_autoneg_cfg(tp, new_adv,
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FLOW_CTRL_TX | FLOW_CTRL_RX);
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} else if (tp->link_config.speed == SPEED_INVALID) {
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if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
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tp->link_config.advertising &=
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~(ADVERTISED_1000baseT_Half |
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ADVERTISED_1000baseT_Full);
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tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
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tp->link_config.flowctrl);
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} else {
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/* Asking for a specific link mode. */
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if (tp->link_config.speed == SPEED_1000) {
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if (tp->link_config.duplex == DUPLEX_FULL)
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new_adv = ADVERTISED_1000baseT_Full;
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else
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new_adv = ADVERTISED_1000baseT_Half;
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} else if (tp->link_config.speed == SPEED_100) {
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if (tp->link_config.duplex == DUPLEX_FULL)
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new_adv = ADVERTISED_100baseT_Full;
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else
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new_adv = ADVERTISED_100baseT_Half;
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} else {
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if (tp->link_config.duplex == DUPLEX_FULL)
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new_adv = ADVERTISED_10baseT_Full;
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else
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new_adv = ADVERTISED_10baseT_Half;
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}
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tg3_phy_autoneg_cfg(tp, new_adv,
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tp->link_config.flowctrl);
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}
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if (tp->link_config.autoneg == AUTONEG_DISABLE &&
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@ -12953,7 +12952,7 @@ static int __devinit tg3_phy_probe(struct tg3 *tp)
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if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
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!tg3_flag(tp, ENABLE_APE) &&
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!tg3_flag(tp, ENABLE_ASF)) {
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u32 bmsr, adv_reg, tg3_ctrl, mask;
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u32 bmsr, mask;
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tg3_readphy(tp, MII_BMSR, &bmsr);
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if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
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@ -12964,36 +12963,18 @@ static int __devinit tg3_phy_probe(struct tg3 *tp)
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if (err)
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return err;
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adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
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ADVERTISE_100HALF | ADVERTISE_100FULL |
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ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
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tg3_ctrl = 0;
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if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
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tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
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MII_TG3_CTRL_ADV_1000_FULL);
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if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
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tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
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tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
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MII_TG3_CTRL_ENABLE_AS_MASTER);
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}
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tg3_phy_set_wirespeed(tp);
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mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
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ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
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ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
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if (!tg3_copper_is_advertising_all(tp, mask)) {
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tg3_writephy(tp, MII_ADVERTISE, adv_reg);
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if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
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tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
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tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
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tp->link_config.flowctrl);
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tg3_writephy(tp, MII_BMCR,
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BMCR_ANENABLE | BMCR_ANRESTART);
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}
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tg3_phy_set_wirespeed(tp);
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tg3_writephy(tp, MII_ADVERTISE, adv_reg);
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if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
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tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
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}
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skip_phy_reset:
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