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perf, x86: Add Nehalem programming quirk to Westmere

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According to the Xeon-5600 errata the Westmere suffers the same PMU
programming bug as the original Nehalem did.

Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Peter Zijlstra 2010-03-29 16:37:17 +02:00 committed by Ingo Molnar
parent caaa8be3b6
commit 40b91cd10f
1 changed files with 2 additions and 0 deletions
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2
arch/x86/kernel/cpu/perf_event_intel.c
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@ -488,6 +488,7 @@ static void intel_pmu_enable_all(int added)
* Workaround for:
* Intel Errata AAK100 (model 26)
* Intel Errata AAP53 (model 30)
* Intel Errata BD53 (model 44)
*
* These chips need to be 'reset' when adding counters by programming
* the magic three (non counting) events 0x4300D2, 0x4300B1 and 0x4300B5
@ -980,6 +981,7 @@ static __init int intel_pmu_init(void)
intel_pmu_lbr_init_nhm();
x86_pmu.event_constraints = intel_westmere_event_constraints;
x86_pmu.enable_all = intel_pmu_nhm_enable_all;
pr_cont("Westmere events, ");
break;