ARM: S5P: add required chained_irq_enter/exit to gpio-int code
This patch adds chained IRQ enter/exit functions to gpio interrupt handler in order to function correctly on primary controllers with different methods of flow control. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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1 changed files with 6 additions and 0 deletions
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@ -23,6 +23,8 @@
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#include <plat/gpio-core.h>
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#include <plat/gpio-cfg.h>
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#include <asm/mach/irq.h>
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#define GPIO_BASE(chip) (((unsigned long)(chip)->base) & 0xFFFFF000u)
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#define CON_OFFSET 0x700
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@ -81,6 +83,9 @@ static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc)
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int group, pend_offset, mask_offset;
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unsigned int pend, mask;
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struct irq_chip *chip = irq_get_chip(irq);
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chained_irq_enter(chip, desc);
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for (group = 0; group < bank->nr_groups; group++) {
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struct s3c_gpio_chip *chip = bank->chips[group];
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if (!chip)
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@ -102,6 +107,7 @@ static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc)
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pend &= ~BIT(offset);
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}
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}
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chained_irq_exit(chip, desc);
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}
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static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip)
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