Techwizz/kernel-fxtec-pro1x
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Merge branch 'pxa-all' into devel

Browse source 
Conflicts:

	arch/arm/mach-pxa/Kconfig
	arch/arm/mach-pxa/corgi.c
	arch/arm/mach-pxa/include/mach/hardware.h
	arch/arm/mach-pxa/spitz.c
This commit is contained in:
Russell King 2008-10-09 21:33:02 +01:00 committed by Russell King
commit 3f30a09a61
193 changed files with 15252 additions and 5410 deletions
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12
Documentation/sound/alsa/soc/dapm.txt
View file

@ -135,11 +135,7 @@ when the Mic is inserted:-
static int spitz_mic_bias(struct snd_soc_dapm_widget* w, int event)
{
if(SND_SOC_DAPM_EVENT_ON(event))
set_scoop_gpio(&spitzscoop2_device.dev, SPITZ_SCP2_MIC_BIAS);
else
reset_scoop_gpio(&spitzscoop2_device.dev, SPITZ_SCP2_MIC_BIAS);
gpio_set_value(SPITZ_GPIO_MIC_BIAS, SND_SOC_DAPM_EVENT_ON(event));
return 0;
}
@ -269,11 +265,7 @@ powered only when the spk is in use.
/* turn speaker amplifier on/off depending on use */
static int corgi_amp_event(struct snd_soc_dapm_widget *w, int event)
{
if (SND_SOC_DAPM_EVENT_ON(event))
set_scoop_gpio(&corgiscoop_device.dev, CORGI_SCP_APM_ON);
else
reset_scoop_gpio(&corgiscoop_device.dev, CORGI_SCP_APM_ON);
gpio_set_value(CORGI_GPIO_APM_ON, SND_SOC_DAPM_EVENT_ON(event));
return 0;
}

8
MAINTAINERS
View file

@ -497,7 +497,7 @@ M: kernel@wantstofly.org
L: linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only)
S: Maintained
ARM/COMPULAB CM-X270/EM-X270 MACHINE SUPPORT
ARM/COMPULAB CM-X270/EM-X270 and CM-X300 MACHINE SUPPORT
P: Mike Rapoport
M: mike@compulab.co.il
L: linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only)
@ -629,6 +629,12 @@ M: marek.vasut@gmail.com
W: http://hackndev.com
S: Maintained
ARM/PALMZ72 SUPPORT
P: Sergey Lapin
M: slapin@ossfans.org
W: http://hackndev.com
S: Maintained
ARM/PLEB SUPPORT
P: Peter Chubb
M: pleb@gelato.unsw.edu.au

2
arch/arm/Kconfig
View file

@ -876,7 +876,7 @@ config LEDS
ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
ARCH_AT91 || MACH_TRIZEPS4 || ARCH_DAVINCI || \
ARCH_AT91 || ARCH_DAVINCI || \
ARCH_KS8695 || MACH_RD88F5182
help
If you say Y here, the LEDs on your machine will be used

14
arch/arm/common/it8152.c
View file

@ -66,14 +66,6 @@ static void it8152_unmask_irq(unsigned int irq)
}
}
static inline void it8152_irq(int irq)
{
struct irq_desc *desc;
desc = irq_desc + irq;
desc_handle_irq(irq, desc);
}
static struct irq_chip it8152_irq_chip = {
.name = "it8152",
.ack = it8152_mask_irq,
@ -128,21 +120,21 @@ void it8152_irq_demux(unsigned int irq, struct irq_desc *desc)
bits_pd &= ((1 << IT8152_PD_IRQ_COUNT) - 1);
while (bits_pd) {
i = __ffs(bits_pd);
it8152_irq(IT8152_PD_IRQ(i));
generic_handle_irq(IT8152_PD_IRQ(i));
bits_pd &= ~(1 << i);
}
bits_lp &= ((1 << IT8152_LP_IRQ_COUNT) - 1);
while (bits_lp) {
i = __ffs(bits_lp);
it8152_irq(IT8152_LP_IRQ(i));
generic_handle_irq(IT8152_LP_IRQ(i));
bits_lp &= ~(1 << i);
}
bits_ld &= ((1 << IT8152_LD_IRQ_COUNT) - 1);
while (bits_ld) {
i = __ffs(bits_ld);
it8152_irq(IT8152_LD_IRQ(i));
generic_handle_irq(IT8152_LD_IRQ(i));
bits_ld &= ~(1 << i);
}
}

26
arch/arm/common/locomo.c
View file

@ -169,7 +169,6 @@ static struct locomo_dev_info locomo_devices[] = {
static void locomo_handler(unsigned int irq, struct irq_desc *desc)
{
int req, i;
struct irq_desc *d;
void __iomem *mapbase = get_irq_chip_data(irq);
/* Acknowledge the parent IRQ */
@ -181,10 +180,9 @@ static void locomo_handler(unsigned int irq, struct irq_desc *desc)
if (req) {
/* generate the next interrupt(s) */
irq = LOCOMO_IRQ_START;
d = irq_desc + irq;
for (i = 0; i <= 3; i++, d++, irq++) {
for (i = 0; i <= 3; i++, irq++) {
if (req & (0x0100 << i)) {
desc_handle_irq(irq, d);
generic_handle_irq(irq);
}
}
@ -222,12 +220,10 @@ static struct irq_chip locomo_chip = {
static void locomo_key_handler(unsigned int irq, struct irq_desc *desc)
{
struct irq_desc *d;
void __iomem *mapbase = get_irq_chip_data(irq);
if (locomo_readl(mapbase + LOCOMO_KEYBOARD + LOCOMO_KIC) & 0x0001) {
d = irq_desc + LOCOMO_IRQ_KEY_START;
desc_handle_irq(LOCOMO_IRQ_KEY_START, d);
generic_handle_irq(LOCOMO_IRQ_KEY_START);
}
}
@ -268,7 +264,6 @@ static struct irq_chip locomo_key_chip = {
static void locomo_gpio_handler(unsigned int irq, struct irq_desc *desc)
{
int req, i;
struct irq_desc *d;
void __iomem *mapbase = get_irq_chip_data(irq);
req = locomo_readl(mapbase + LOCOMO_GIR) &
@ -277,10 +272,9 @@ static void locomo_gpio_handler(unsigned int irq, struct irq_desc *desc)
if (req) {
irq = LOCOMO_IRQ_GPIO_START;
d = irq_desc + LOCOMO_IRQ_GPIO_START;
for (i = 0; i <= 15; i++, irq++, d++) {
for (i = 0; i <= 15; i++, irq++) {
if (req & (0x0001 << i)) {
desc_handle_irq(irq, d);
generic_handle_irq(irq);
}
}
}
@ -361,12 +355,10 @@ static struct irq_chip locomo_gpio_chip = {
static void locomo_lt_handler(unsigned int irq, struct irq_desc *desc)
{
struct irq_desc *d;
void __iomem *mapbase = get_irq_chip_data(irq);
if (locomo_readl(mapbase + LOCOMO_LTINT) & 0x0001) {
d = irq_desc + LOCOMO_IRQ_LT_START;
desc_handle_irq(LOCOMO_IRQ_LT_START, d);
generic_handle_irq(LOCOMO_IRQ_LT_START);
}
}
@ -407,17 +399,15 @@ static struct irq_chip locomo_lt_chip = {
static void locomo_spi_handler(unsigned int irq, struct irq_desc *desc)
{
int req, i;
struct irq_desc *d;
void __iomem *mapbase = get_irq_chip_data(irq);
req = locomo_readl(mapbase + LOCOMO_SPI + LOCOMO_SPIIR) & 0x000F;
if (req) {
irq = LOCOMO_IRQ_SPI_START;
d = irq_desc + irq;
for (i = 0; i <= 3; i++, irq++, d++) {
for (i = 0; i <= 3; i++, irq++) {
if (req & (0x0001 << i)) {
desc_handle_irq(irq, d);
generic_handle_irq(irq);
}
}
}

2
arch/arm/common/sharpsl_param.c
View file

@ -12,6 +12,7 @@
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/string.h>
#include <asm/mach/sharpsl_param.h>
@ -36,6 +37,7 @@
#define PHAD_MAGIC MAGIC_CHG('P','H','A','D')
struct sharpsl_param_info sharpsl_param;
EXPORT_SYMBOL(sharpsl_param);
void sharpsl_save_param(void)
{

1466
arch/arm/configs/cm_x300_defconfig Normal file
View file

File diff suppressed because it is too large Load diff

951
arch/arm/configs/palmz72_defconfig Normal file
View file

@ -0,0 +1,951 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.27-rc4
# Sun Aug 24 02:29:27 2008
#
CONFIG_ARM=y
CONFIG_HAVE_PWM=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
CONFIG_GENERIC_GPIO=y
CONFIG_GENERIC_TIME=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_MMU=y
# CONFIG_NO_IOPORT is not set
CONFIG_GENERIC_HARDIRQS=y
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_HAVE_LATENCYTOP_SUPPORT=y
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
# CONFIG_ARCH_HAS_ILOG2_U64 is not set
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_ARCH_SUPPORTS_AOUT=y
CONFIG_ZONE_DMA=y
CONFIG_ARCH_MTD_XIP=y
CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
CONFIG_VECTORS_BASE=0xffff0000
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
#
# General setup
#
CONFIG_EXPERIMENTAL=y
CONFIG_BROKEN_ON_SMP=y
CONFIG_LOCK_KERNEL=y
CONFIG_INIT_ENV_ARG_LIMIT=32
CONFIG_LOCALVERSION=""
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_SWAP=y
CONFIG_SYSVIPC=y
CONFIG_SYSVIPC_SYSCTL=y
# CONFIG_POSIX_MQUEUE is not set
# CONFIG_BSD_PROCESS_ACCT is not set
# CONFIG_TASKSTATS is not set
# CONFIG_AUDIT is not set
# CONFIG_IKCONFIG is not set
CONFIG_LOG_BUF_SHIFT=14
# CONFIG_CGROUPS is not set
# CONFIG_GROUP_SCHED is not set
CONFIG_SYSFS_DEPRECATED=y
CONFIG_SYSFS_DEPRECATED_V2=y
# CONFIG_RELAY is not set
CONFIG_NAMESPACES=y
# CONFIG_UTS_NS is not set
# CONFIG_IPC_NS is not set
# CONFIG_USER_NS is not set
# CONFIG_PID_NS is not set
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_SYSCTL=y
# CONFIG_EMBEDDED is not set
CONFIG_UID16=y
CONFIG_SYSCTL_SYSCALL=y
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_EXTRA_PASS is not set
CONFIG_HOTPLUG=y
CONFIG_PRINTK=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
CONFIG_COMPAT_BRK=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_ANON_INODES=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_SLAB=y
# CONFIG_SLUB is not set
# CONFIG_SLOB is not set
# CONFIG_PROFILING is not set
# CONFIG_MARKERS is not set
CONFIG_HAVE_OPROFILE=y
# CONFIG_KPROBES is not set
# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
# CONFIG_HAVE_IOREMAP_PROT is not set
CONFIG_HAVE_KPROBES=y
CONFIG_HAVE_KRETPROBES=y
# CONFIG_HAVE_ARCH_TRACEHOOK is not set
# CONFIG_HAVE_DMA_ATTRS is not set
# CONFIG_USE_GENERIC_SMP_HELPERS is not set
CONFIG_HAVE_CLK=y
CONFIG_PROC_PAGE_MONITOR=y
CONFIG_HAVE_GENERIC_DMA_COHERENT=y
CONFIG_SLABINFO=y
CONFIG_RT_MUTEXES=y
# CONFIG_TINY_SHMEM is not set
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
# CONFIG_MODULE_FORCE_LOAD is not set
CONFIG_MODULE_UNLOAD=y
# CONFIG_MODULE_FORCE_UNLOAD is not set
# CONFIG_MODVERSIONS is not set
# CONFIG_MODULE_SRCVERSION_ALL is not set
CONFIG_KMOD=y
CONFIG_BLOCK=y
# CONFIG_LBD is not set
# CONFIG_BLK_DEV_IO_TRACE is not set
# CONFIG_LSF is not set
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_BLK_DEV_INTEGRITY is not set
#
# IO Schedulers
#
CONFIG_IOSCHED_NOOP=y
CONFIG_IOSCHED_AS=y
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_DEFAULT_AS=y
# CONFIG_DEFAULT_DEADLINE is not set
# CONFIG_DEFAULT_CFQ is not set
# CONFIG_DEFAULT_NOOP is not set
CONFIG_DEFAULT_IOSCHED="anticipatory"
CONFIG_CLASSIC_RCU=y
#
# System Type
#
# CONFIG_ARCH_AAEC2000 is not set
# CONFIG_ARCH_INTEGRATOR is not set
# CONFIG_ARCH_REALVIEW is not set
# CONFIG_ARCH_VERSATILE is not set
# CONFIG_ARCH_AT91 is not set
# CONFIG_ARCH_CLPS7500 is not set
# CONFIG_ARCH_CLPS711X is not set
# CONFIG_ARCH_EBSA110 is not set
# CONFIG_ARCH_EP93XX is not set
# CONFIG_ARCH_FOOTBRIDGE is not set
# CONFIG_ARCH_NETX is not set
# CONFIG_ARCH_H720X is not set
# CONFIG_ARCH_IMX is not set
# CONFIG_ARCH_IOP13XX is not set
# CONFIG_ARCH_IOP32X is not set
# CONFIG_ARCH_IOP33X is not set
# CONFIG_ARCH_IXP23XX is not set
# CONFIG_ARCH_IXP2000 is not set
# CONFIG_ARCH_IXP4XX is not set
# CONFIG_ARCH_L7200 is not set
# CONFIG_ARCH_KIRKWOOD is not set
# CONFIG_ARCH_KS8695 is not set
# CONFIG_ARCH_NS9XXX is not set
# CONFIG_ARCH_LOKI is not set
# CONFIG_ARCH_MV78XX0 is not set
# CONFIG_ARCH_MXC is not set
# CONFIG_ARCH_ORION5X is not set
# CONFIG_ARCH_PNX4008 is not set
CONFIG_ARCH_PXA=y
# CONFIG_ARCH_RPC is not set
# CONFIG_ARCH_SA1100 is not set
# CONFIG_ARCH_S3C2410 is not set
# CONFIG_ARCH_SHARK is not set
# CONFIG_ARCH_LH7A40X is not set
# CONFIG_ARCH_DAVINCI is not set
# CONFIG_ARCH_OMAP is not set
# CONFIG_ARCH_MSM7X00A is not set
#
# Intel PXA2xx/PXA3xx Implementations
#
# CONFIG_ARCH_GUMSTIX is not set
# CONFIG_ARCH_LUBBOCK is not set
# CONFIG_MACH_LOGICPD_PXA270 is not set
# CONFIG_MACH_MAINSTONE is not set
# CONFIG_ARCH_PXA_IDP is not set
# CONFIG_PXA_SHARPSL is not set
# CONFIG_ARCH_PXA_ESERIES is not set
# CONFIG_MACH_TRIZEPS4 is not set
# CONFIG_MACH_EM_X270 is not set
# CONFIG_MACH_COLIBRI is not set
# CONFIG_MACH_ZYLONITE is not set
# CONFIG_MACH_LITTLETON is not set
# CONFIG_MACH_TAVOREVB is not set
# CONFIG_MACH_SAAR is not set
# CONFIG_MACH_ARMCORE is not set
# CONFIG_MACH_MAGICIAN is not set
# CONFIG_MACH_PCM027 is not set
CONFIG_ARCH_PXA_PALM=y
# CONFIG_MACH_PALMTX is not set
CONFIG_MACH_PALMZ72=y
# CONFIG_PXA_EZX is not set
CONFIG_PXA27x=y
CONFIG_PXA_PWM=y
#
# Boot options
#
#
# Power management
#
#
# Processor Type
#
CONFIG_CPU_32=y
CONFIG_CPU_XSCALE=y
CONFIG_CPU_32v5=y
CONFIG_CPU_ABRT_EV5T=y
CONFIG_CPU_PABRT_NOIFAR=y
CONFIG_CPU_CACHE_VIVT=y
CONFIG_CPU_TLB_V4WBI=y
CONFIG_CPU_CP15=y
CONFIG_CPU_CP15_MMU=y
#
# Processor Features
#
CONFIG_ARM_THUMB=y
# CONFIG_CPU_DCACHE_DISABLE is not set
# CONFIG_OUTER_CACHE is not set
CONFIG_IWMMXT=y
CONFIG_XSCALE_PMU=y
#
# Bus support
#
# CONFIG_PCI_SYSCALL is not set
# CONFIG_ARCH_SUPPORTS_MSI is not set
# CONFIG_PCCARD is not set
#
# Kernel Features
#
CONFIG_TICK_ONESHOT=y
# CONFIG_NO_HZ is not set
# CONFIG_HIGH_RES_TIMERS is not set
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
CONFIG_PREEMPT=y
CONFIG_HZ=100
CONFIG_AEABI=y
CONFIG_OABI_COMPAT=y
# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
CONFIG_SELECT_MEMORY_MODEL=y
CONFIG_FLATMEM_MANUAL=y
# CONFIG_DISCONTIGMEM_MANUAL is not set
# CONFIG_SPARSEMEM_MANUAL is not set
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
# CONFIG_SPARSEMEM_STATIC is not set
# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
CONFIG_PAGEFLAGS_EXTENDED=y
CONFIG_SPLIT_PTLOCK_CPUS=4096
# CONFIG_RESOURCES_64BIT is not set
CONFIG_ZONE_DMA_FLAG=1
CONFIG_BOUNCE=y
CONFIG_VIRT_TO_BUS=y
CONFIG_ALIGNMENT_TRAP=y
#
# Boot options
#
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="mem=32M console=tty root=/dev/mmcblk0"
# CONFIG_XIP_KERNEL is not set
# CONFIG_KEXEC is not set
#
# CPU Frequency scaling
#
# CONFIG_CPU_FREQ is not set
#
# Floating point emulation
#
#
# At least one emulation must be selected
#
CONFIG_FPE_NWFPE=y
# CONFIG_FPE_NWFPE_XP is not set
# CONFIG_FPE_FASTFPE is not set
#
# Userspace binary formats
#
CONFIG_BINFMT_ELF=y
# CONFIG_BINFMT_AOUT is not set
# CONFIG_BINFMT_MISC is not set
#
# Power management options
#
CONFIG_PM=y
# CONFIG_PM_DEBUG is not set
CONFIG_PM_SLEEP=y
CONFIG_SUSPEND=y
CONFIG_SUSPEND_FREEZER=y
CONFIG_APM_EMULATION=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_NET=y
#
# Networking options
#
CONFIG_PACKET=y
# CONFIG_PACKET_MMAP is not set
CONFIG_UNIX=y
# CONFIG_NET_KEY is not set
CONFIG_INET=y
# CONFIG_IP_MULTICAST is not set
# CONFIG_IP_ADVANCED_ROUTER is not set
CONFIG_IP_FIB_HASH=y
CONFIG_IP_PNP=y
# CONFIG_IP_PNP_DHCP is not set
CONFIG_IP_PNP_BOOTP=y
# CONFIG_IP_PNP_RARP is not set
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set
# CONFIG_ARPD is not set
# CONFIG_SYN_COOKIES is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
# CONFIG_INET_XFRM_TUNNEL is not set
# CONFIG_INET_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_LRO is not set
CONFIG_INET_DIAG=y
CONFIG_INET_TCP_DIAG=y
# CONFIG_TCP_CONG_ADVANCED is not set
CONFIG_TCP_CONG_CUBIC=y
CONFIG_DEFAULT_TCP_CONG="cubic"
# CONFIG_TCP_MD5SIG is not set
# CONFIG_IPV6 is not set
# CONFIG_NETWORK_SECMARK is not set
# CONFIG_NETFILTER is not set
# CONFIG_IP_DCCP is not set
# CONFIG_IP_SCTP is not set
# CONFIG_TIPC is not set
# CONFIG_ATM is not set
# CONFIG_BRIDGE is not set
# CONFIG_VLAN_8021Q is not set
# CONFIG_DECNET is not set
# CONFIG_LLC2 is not set
# CONFIG_IPX is not set
# CONFIG_ATALK is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
# CONFIG_NET_SCHED is not set
#
# Network testing
#
# CONFIG_NET_PKTGEN is not set
# CONFIG_HAMRADIO is not set
# CONFIG_CAN is not set
# CONFIG_IRDA is not set
# CONFIG_BT is not set
# CONFIG_AF_RXRPC is not set
#
# Wireless
#
# CONFIG_CFG80211 is not set
# CONFIG_WIRELESS_EXT is not set
# CONFIG_MAC80211 is not set
# CONFIG_IEEE80211 is not set
# CONFIG_RFKILL is not set
# CONFIG_NET_9P is not set
#
# Device Drivers
#
#
# Generic Driver Options
#
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
CONFIG_FW_LOADER=y
CONFIG_FIRMWARE_IN_KERNEL=y
CONFIG_EXTRA_FIRMWARE=""
# CONFIG_SYS_HYPERVISOR is not set
# CONFIG_CONNECTOR is not set
# CONFIG_MTD is not set
# CONFIG_PARPORT is not set
CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_COW_COMMON is not set
CONFIG_BLK_DEV_LOOP=y
# CONFIG_BLK_DEV_CRYPTOLOOP is not set
# CONFIG_BLK_DEV_NBD is not set
# CONFIG_BLK_DEV_RAM is not set
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_ATA_OVER_ETH is not set
# CONFIG_MISC_DEVICES is not set
CONFIG_HAVE_IDE=y
# CONFIG_IDE is not set
#
# SCSI device support
#
# CONFIG_RAID_ATTRS is not set
# CONFIG_SCSI is not set
# CONFIG_SCSI_DMA is not set
# CONFIG_SCSI_NETLINK is not set
# CONFIG_ATA is not set
# CONFIG_MD is not set
# CONFIG_NETDEVICES is not set
# CONFIG_ISDN is not set
#
# Input device support
#
CONFIG_INPUT=y
# CONFIG_INPUT_FF_MEMLESS is not set
# CONFIG_INPUT_POLLDEV is not set
#
# Userland interfaces
#
CONFIG_INPUT_MOUSEDEV=y
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
# CONFIG_INPUT_JOYDEV is not set
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_EVBUG is not set
#
# Input Device Drivers
#
CONFIG_INPUT_KEYBOARD=y
# CONFIG_KEYBOARD_ATKBD is not set
# CONFIG_KEYBOARD_SUNKBD is not set
# CONFIG_KEYBOARD_LKKBD is not set
# CONFIG_KEYBOARD_XTKBD is not set
# CONFIG_KEYBOARD_NEWTON is not set
# CONFIG_KEYBOARD_STOWAWAY is not set
CONFIG_KEYBOARD_PXA27x=y
# CONFIG_KEYBOARD_GPIO is not set
# CONFIG_KEYBOARD_MATRIX is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TABLET is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
# CONFIG_INPUT_MISC is not set
#
# Hardware I/O ports
#
# CONFIG_SERIO is not set
# CONFIG_GAMEPORT is not set
#
# Character devices
#
CONFIG_VT=y
CONFIG_CONSOLE_TRANSLATIONS=y
CONFIG_VT_CONSOLE=y
CONFIG_HW_CONSOLE=y
# CONFIG_VT_HW_CONSOLE_BINDING is not set
CONFIG_DEVKMEM=y
# CONFIG_SERIAL_NONSTANDARD is not set
#
# Serial drivers
#
# CONFIG_SERIAL_8250 is not set
#
# Non-8250 serial port support
#
# CONFIG_SERIAL_PXA is not set
CONFIG_UNIX98_PTYS=y
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
# CONFIG_IPMI_HANDLER is not set
# CONFIG_HW_RANDOM is not set
# CONFIG_NVRAM is not set
# CONFIG_R3964 is not set
# CONFIG_RAW_DRIVER is not set
# CONFIG_TCG_TPM is not set
CONFIG_I2C=y
CONFIG_I2C_BOARDINFO=y
# CONFIG_I2C_CHARDEV is not set
CONFIG_I2C_HELPER_AUTO=y
#
# I2C Hardware Bus support
#
#
# I2C system bus drivers (mostly embedded / system-on-chip)
#
# CONFIG_I2C_GPIO is not set
# CONFIG_I2C_OCORES is not set
CONFIG_I2C_PXA=y
# CONFIG_I2C_PXA_SLAVE is not set
# CONFIG_I2C_SIMTEC is not set
#
# External I2C/SMBus adapter drivers
#
# CONFIG_I2C_PARPORT_LIGHT is not set
# CONFIG_I2C_TAOS_EVM is not set
#
# Other I2C/SMBus bus drivers
#
# CONFIG_I2C_PCA_PLATFORM is not set
# CONFIG_I2C_STUB is not set
#
# Miscellaneous I2C Chip support
#
# CONFIG_DS1682 is not set
# CONFIG_AT24 is not set
# CONFIG_SENSORS_EEPROM is not set
# CONFIG_SENSORS_PCF8574 is not set
# CONFIG_PCF8575 is not set
# CONFIG_SENSORS_PCA9539 is not set
# CONFIG_SENSORS_PCF8591 is not set
# CONFIG_TPS65010 is not set
# CONFIG_SENSORS_MAX6875 is not set
# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
# CONFIG_I2C_DEBUG_CHIP is not set
CONFIG_SPI=y
CONFIG_SPI_MASTER=y
#
# SPI Master Controller Drivers
#
# CONFIG_SPI_BITBANG is not set
# CONFIG_SPI_PXA2XX is not set
#
# SPI Protocol Masters
#
# CONFIG_SPI_AT25 is not set
CONFIG_SPI_SPIDEV=y
# CONFIG_SPI_TLE62X0 is not set
CONFIG_ARCH_REQUIRE_GPIOLIB=y
CONFIG_GPIOLIB=y
CONFIG_GPIO_SYSFS=y
#
# I2C GPIO expanders:
#
# CONFIG_GPIO_MAX732X is not set
# CONFIG_GPIO_PCA953X is not set
# CONFIG_GPIO_PCF857X is not set
#
# PCI GPIO expanders:
#
#
# SPI GPIO expanders:
#
# CONFIG_GPIO_MAX7301 is not set
# CONFIG_GPIO_MCP23S08 is not set
# CONFIG_W1 is not set
CONFIG_POWER_SUPPLY=y
# CONFIG_POWER_SUPPLY_DEBUG is not set
CONFIG_PDA_POWER=y
# CONFIG_APM_POWER is not set
# CONFIG_BATTERY_DS2760 is not set
# CONFIG_HWMON is not set
# CONFIG_WATCHDOG is not set
#
# Sonics Silicon Backplane
#
CONFIG_SSB_POSSIBLE=y
# CONFIG_SSB is not set
#
# Multifunction device drivers
#
# CONFIG_MFD_CORE is not set
# CONFIG_MFD_SM501 is not set
# CONFIG_HTC_EGPIO is not set
# CONFIG_HTC_PASIC3 is not set
# CONFIG_MFD_TMIO is not set
# CONFIG_MFD_T7L66XB is not set
# CONFIG_MFD_TC6387XB is not set
# CONFIG_MFD_TC6393XB is not set
#
# Multimedia devices
#
#
# Multimedia core support
#
# CONFIG_VIDEO_DEV is not set
# CONFIG_DVB_CORE is not set
# CONFIG_VIDEO_MEDIA is not set
#
# Multimedia drivers
#
# CONFIG_DAB is not set
#
# Graphics support
#
# CONFIG_VGASTATE is not set
# CONFIG_VIDEO_OUTPUT_CONTROL is not set
CONFIG_FB=y
# CONFIG_FIRMWARE_EDID is not set
# CONFIG_FB_DDC is not set
CONFIG_FB_CFB_FILLRECT=y
CONFIG_FB_CFB_COPYAREA=y
CONFIG_FB_CFB_IMAGEBLIT=y
# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
# CONFIG_FB_SYS_FILLRECT is not set
# CONFIG_FB_SYS_COPYAREA is not set
# CONFIG_FB_SYS_IMAGEBLIT is not set
# CONFIG_FB_FOREIGN_ENDIAN is not set
# CONFIG_FB_SYS_FOPS is not set
# CONFIG_FB_SVGALIB is not set
# CONFIG_FB_MACMODES is not set
# CONFIG_FB_BACKLIGHT is not set
# CONFIG_FB_MODE_HELPERS is not set
# CONFIG_FB_TILEBLITTING is not set
#
# Frame buffer hardware drivers
#
# CONFIG_FB_S1D13XXX is not set
CONFIG_FB_PXA=y
# CONFIG_FB_PXA_SMARTPANEL is not set
# CONFIG_FB_PXA_PARAMETERS is not set
# CONFIG_FB_MBX is not set
# CONFIG_FB_W100 is not set
# CONFIG_FB_AM200EPD is not set
# CONFIG_FB_VIRTUAL is not set
CONFIG_BACKLIGHT_LCD_SUPPORT=y
# CONFIG_LCD_CLASS_DEVICE is not set
CONFIG_BACKLIGHT_CLASS_DEVICE=y
# CONFIG_BACKLIGHT_CORGI is not set
CONFIG_BACKLIGHT_PWM=y
#
# Display device support
#
CONFIG_DISPLAY_SUPPORT=y
#
# Display hardware drivers
#
#
# Console display driver support
#
# CONFIG_VGA_CONSOLE is not set
CONFIG_DUMMY_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE=y
# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
CONFIG_FONTS=y
CONFIG_FONT_8x8=y
# CONFIG_FONT_8x16 is not set
# CONFIG_FONT_6x11 is not set
# CONFIG_FONT_7x14 is not set
# CONFIG_FONT_PEARL_8x8 is not set
# CONFIG_FONT_ACORN_8x8 is not set
# CONFIG_FONT_MINI_4x6 is not set
# CONFIG_FONT_SUN8x16 is not set
# CONFIG_FONT_SUN12x22 is not set
# CONFIG_FONT_10x18 is not set
# CONFIG_LOGO is not set
# CONFIG_SOUND is not set
# CONFIG_HID_SUPPORT is not set
# CONFIG_USB_SUPPORT is not set
CONFIG_MMC=y
CONFIG_MMC_DEBUG=y
# CONFIG_MMC_UNSAFE_RESUME is not set
#
# MMC/SD Card Drivers
#
CONFIG_MMC_BLOCK=y
CONFIG_MMC_BLOCK_BOUNCE=y
# CONFIG_SDIO_UART is not set
# CONFIG_MMC_TEST is not set
#
# MMC/SD Host Controller Drivers
#
CONFIG_MMC_PXA=y
# CONFIG_MMC_SDHCI is not set
# CONFIG_MMC_SPI is not set
# CONFIG_NEW_LEDS is not set
CONFIG_RTC_LIB=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_HCTOSYS=y
CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
# CONFIG_RTC_DEBUG is not set
#
# RTC interfaces
#
CONFIG_RTC_INTF_SYSFS=y
CONFIG_RTC_INTF_PROC=y
CONFIG_RTC_INTF_DEV=y
# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
# CONFIG_RTC_DRV_TEST is not set
#
# I2C RTC drivers
#
# CONFIG_RTC_DRV_DS1307 is not set
# CONFIG_RTC_DRV_DS1374 is not set
# CONFIG_RTC_DRV_DS1672 is not set
# CONFIG_RTC_DRV_MAX6900 is not set
# CONFIG_RTC_DRV_RS5C372 is not set
# CONFIG_RTC_DRV_ISL1208 is not set
# CONFIG_RTC_DRV_X1205 is not set
# CONFIG_RTC_DRV_PCF8563 is not set
# CONFIG_RTC_DRV_PCF8583 is not set
# CONFIG_RTC_DRV_M41T80 is not set
# CONFIG_RTC_DRV_S35390A is not set
# CONFIG_RTC_DRV_FM3130 is not set
#
# SPI RTC drivers
#
# CONFIG_RTC_DRV_M41T94 is not set
# CONFIG_RTC_DRV_DS1305 is not set
# CONFIG_RTC_DRV_MAX6902 is not set
# CONFIG_RTC_DRV_R9701 is not set
# CONFIG_RTC_DRV_RS5C348 is not set
#
# Platform RTC drivers
#
# CONFIG_RTC_DRV_CMOS is not set
# CONFIG_RTC_DRV_DS1511 is not set
# CONFIG_RTC_DRV_DS1553 is not set
# CONFIG_RTC_DRV_DS1742 is not set
# CONFIG_RTC_DRV_STK17TA8 is not set
# CONFIG_RTC_DRV_M48T86 is not set
# CONFIG_RTC_DRV_M48T59 is not set
# CONFIG_RTC_DRV_V3020 is not set
#
# on-CPU RTC drivers
#
CONFIG_RTC_DRV_SA1100=y
# CONFIG_DMADEVICES is not set
#
# Voltage and Current regulators
#
# CONFIG_REGULATOR is not set
# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
# CONFIG_REGULATOR_BQ24022 is not set
# CONFIG_UIO is not set
#
# File systems
#
CONFIG_EXT2_FS=y
# CONFIG_EXT2_FS_XATTR is not set
# CONFIG_EXT2_FS_XIP is not set
CONFIG_EXT3_FS=y
CONFIG_EXT3_FS_XATTR=y
# CONFIG_EXT3_FS_POSIX_ACL is not set
# CONFIG_EXT3_FS_SECURITY is not set
# CONFIG_EXT4DEV_FS is not set
CONFIG_JBD=y
CONFIG_FS_MBCACHE=y
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
# CONFIG_FS_POSIX_ACL is not set
# CONFIG_XFS_FS is not set
# CONFIG_OCFS2_FS is not set
# CONFIG_DNOTIFY is not set
# CONFIG_INOTIFY is not set
# CONFIG_QUOTA is not set
# CONFIG_AUTOFS_FS is not set
# CONFIG_AUTOFS4_FS is not set
# CONFIG_FUSE_FS is not set
#
# CD-ROM/DVD Filesystems
#
# CONFIG_ISO9660_FS is not set
# CONFIG_UDF_FS is not set
#
# DOS/FAT/NT Filesystems
#
CONFIG_FAT_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_FAT_DEFAULT_CODEPAGE=866
CONFIG_FAT_DEFAULT_IOCHARSET="utf8"
# CONFIG_NTFS_FS is not set
#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
CONFIG_PROC_SYSCTL=y
CONFIG_SYSFS=y
CONFIG_TMPFS=y
# CONFIG_TMPFS_POSIX_ACL is not set
# CONFIG_HUGETLB_PAGE is not set
# CONFIG_CONFIGFS_FS is not set
#
# Miscellaneous filesystems
#
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_HFSPLUS_FS is not set
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
# CONFIG_CRAMFS is not set
# CONFIG_VXFS_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_OMFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_ROMFS_FS is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
# CONFIG_NETWORK_FILESYSTEMS is not set
#
# Partition Types
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="utf8"
# CONFIG_NLS_CODEPAGE_437 is not set
# CONFIG_NLS_CODEPAGE_737 is not set
# CONFIG_NLS_CODEPAGE_775 is not set
# CONFIG_NLS_CODEPAGE_850 is not set
# CONFIG_NLS_CODEPAGE_852 is not set
# CONFIG_NLS_CODEPAGE_855 is not set
# CONFIG_NLS_CODEPAGE_857 is not set
# CONFIG_NLS_CODEPAGE_860 is not set
# CONFIG_NLS_CODEPAGE_861 is not set
# CONFIG_NLS_CODEPAGE_862 is not set
# CONFIG_NLS_CODEPAGE_863 is not set
# CONFIG_NLS_CODEPAGE_864 is not set
# CONFIG_NLS_CODEPAGE_865 is not set
CONFIG_NLS_CODEPAGE_866=y
# CONFIG_NLS_CODEPAGE_869 is not set
# CONFIG_NLS_CODEPAGE_936 is not set
# CONFIG_NLS_CODEPAGE_950 is not set
# CONFIG_NLS_CODEPAGE_932 is not set
# CONFIG_NLS_CODEPAGE_949 is not set
# CONFIG_NLS_CODEPAGE_874 is not set
# CONFIG_NLS_ISO8859_8 is not set
# CONFIG_NLS_CODEPAGE_1250 is not set
# CONFIG_NLS_CODEPAGE_1251 is not set
# CONFIG_NLS_ASCII is not set
# CONFIG_NLS_ISO8859_1 is not set
# CONFIG_NLS_ISO8859_2 is not set
# CONFIG_NLS_ISO8859_3 is not set
# CONFIG_NLS_ISO8859_4 is not set
# CONFIG_NLS_ISO8859_5 is not set
# CONFIG_NLS_ISO8859_6 is not set
# CONFIG_NLS_ISO8859_7 is not set
# CONFIG_NLS_ISO8859_9 is not set
# CONFIG_NLS_ISO8859_13 is not set
# CONFIG_NLS_ISO8859_14 is not set
# CONFIG_NLS_ISO8859_15 is not set
# CONFIG_NLS_KOI8_R is not set
# CONFIG_NLS_KOI8_U is not set
CONFIG_NLS_UTF8=y
# CONFIG_DLM is not set
#
# Kernel hacking
#
# CONFIG_PRINTK_TIME is not set
CONFIG_ENABLE_WARN_DEPRECATED=y
CONFIG_ENABLE_MUST_CHECK=y
CONFIG_FRAME_WARN=1024
# CONFIG_MAGIC_SYSRQ is not set
# CONFIG_UNUSED_SYMBOLS is not set
# CONFIG_DEBUG_FS is not set
# CONFIG_HEADERS_CHECK is not set
# CONFIG_DEBUG_KERNEL is not set
CONFIG_DEBUG_BUGVERBOSE=y
CONFIG_DEBUG_MEMORY_INIT=y
CONFIG_FRAME_POINTER=y
# CONFIG_LATENCYTOP is not set
CONFIG_SYSCTL_SYSCALL_CHECK=y
CONFIG_HAVE_FTRACE=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
# CONFIG_FTRACE is not set
# CONFIG_IRQSOFF_TRACER is not set
# CONFIG_PREEMPT_TRACER is not set
# CONFIG_SCHED_TRACER is not set
# CONFIG_CONTEXT_SWITCH_TRACER is not set
# CONFIG_SAMPLES is not set
CONFIG_HAVE_ARCH_KGDB=y
CONFIG_DEBUG_USER=y
#
# Security options
#
# CONFIG_KEYS is not set
# CONFIG_SECURITY is not set
# CONFIG_SECURITY_FILE_CAPABILITIES is not set
# CONFIG_CRYPTO is not set
#
# Library routines
#
CONFIG_BITREVERSE=y
# CONFIG_GENERIC_FIND_FIRST_BIT is not set
# CONFIG_GENERIC_FIND_NEXT_BIT is not set
# CONFIG_CRC_CCITT is not set
# CONFIG_CRC16 is not set
CONFIG_CRC_T10DIF=y
# CONFIG_CRC_ITU_T is not set
CONFIG_CRC32=y
# CONFIG_CRC7 is not set
# CONFIG_LIBCRC32C is not set
CONFIG_PLIST=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_DMA=y

1678
arch/arm/configs/viper_defconfig Normal file
View file

File diff suppressed because it is too large Load diff

237
arch/arm/configs/xm_x270_defconfig → arch/arm/configs/xm_x2xx_defconfig
View file

@ -1,7 +1,7 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.25
# Sun May 11 15:12:52 2008
# Linux kernel version: 2.6.27-rc8
# Sun Oct 5 11:05:36 2008
#
CONFIG_ARM=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
@ -12,6 +12,7 @@ CONFIG_MMU=y
# CONFIG_NO_IOPORT is not set
CONFIG_GENERIC_HARDIRQS=y
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_HAVE_LATENCYTOP_SUPPORT=y
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_HARDIRQS_SW_RESEND=y
@ -24,6 +25,7 @@ CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_ARCH_SUPPORTS_AOUT=y
CONFIG_ZONE_DMA=y
CONFIG_ARCH_MTD_XIP=y
CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
CONFIG_VECTORS_BASE=0xffff0000
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
@ -62,7 +64,6 @@ CONFIG_SYSCTL=y
CONFIG_EMBEDDED=y
CONFIG_UID16=y
CONFIG_SYSCTL_SYSCALL=y
CONFIG_SYSCTL_SYSCALL_CHECK=y
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_ALL is not set
# CONFIG_KALLSYMS_EXTRA_PASS is not set
@ -88,14 +89,21 @@ CONFIG_SLUB=y
# CONFIG_MARKERS is not set
CONFIG_HAVE_OPROFILE=y
# CONFIG_KPROBES is not set
# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
# CONFIG_HAVE_IOREMAP_PROT is not set
CONFIG_HAVE_KPROBES=y
CONFIG_HAVE_KRETPROBES=y
# CONFIG_HAVE_ARCH_TRACEHOOK is not set
# CONFIG_HAVE_DMA_ATTRS is not set
# CONFIG_USE_GENERIC_SMP_HELPERS is not set
CONFIG_HAVE_CLK=y
# CONFIG_PROC_PAGE_MONITOR is not set
CONFIG_HAVE_GENERIC_DMA_COHERENT=y
CONFIG_RT_MUTEXES=y
# CONFIG_TINY_SHMEM is not set
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
# CONFIG_MODULE_FORCE_LOAD is not set
CONFIG_MODULE_UNLOAD=y
# CONFIG_MODULE_FORCE_UNLOAD is not set
# CONFIG_MODVERSIONS is not set
@ -106,6 +114,7 @@ CONFIG_BLOCK=y
# CONFIG_BLK_DEV_IO_TRACE is not set
# CONFIG_LSF is not set
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_BLK_DEV_INTEGRITY is not set
#
# IO Schedulers
@ -131,7 +140,6 @@ CONFIG_CLASSIC_RCU=y
# CONFIG_ARCH_AT91 is not set
# CONFIG_ARCH_CLPS7500 is not set
# CONFIG_ARCH_CLPS711X is not set
# CONFIG_ARCH_CO285 is not set
# CONFIG_ARCH_EBSA110 is not set
# CONFIG_ARCH_EP93XX is not set
# CONFIG_ARCH_FOOTBRIDGE is not set
@ -145,8 +153,11 @@ CONFIG_CLASSIC_RCU=y
# CONFIG_ARCH_IXP2000 is not set
# CONFIG_ARCH_IXP4XX is not set
# CONFIG_ARCH_L7200 is not set
# CONFIG_ARCH_KIRKWOOD is not set
# CONFIG_ARCH_KS8695 is not set
# CONFIG_ARCH_NS9XXX is not set
# CONFIG_ARCH_LOKI is not set
# CONFIG_ARCH_MV78XX0 is not set
# CONFIG_ARCH_MXC is not set
# CONFIG_ARCH_ORION5X is not set
# CONFIG_ARCH_PNX4008 is not set
@ -164,26 +175,32 @@ CONFIG_DMABOUNCE=y
#
# Intel PXA2xx/PXA3xx Implementations
#
#
# Select target boards
#
# CONFIG_ARCH_GUMSTIX is not set
# CONFIG_ARCH_LUBBOCK is not set
# CONFIG_MACH_LOGICPD_PXA270 is not set
# CONFIG_MACH_MAINSTONE is not set
# CONFIG_MACH_MP900C is not set
# CONFIG_ARCH_PXA_IDP is not set
# CONFIG_PXA_SHARPSL is not set
# CONFIG_ARCH_VIPER is not set
# CONFIG_ARCH_PXA_ESERIES is not set
# CONFIG_MACH_TRIZEPS4 is not set
# CONFIG_TRIZEPS_PXA is not set
CONFIG_MACH_EM_X270=y
# CONFIG_MACH_COLIBRI is not set
# CONFIG_MACH_ZYLONITE is not set
# CONFIG_MACH_LITTLETON is not set
# CONFIG_MACH_TAVOREVB is not set
# CONFIG_MACH_SAAR is not set
CONFIG_MACH_ARMCORE=y
# CONFIG_MACH_CM_X300 is not set
# CONFIG_MACH_MAGICIAN is not set
# CONFIG_MACH_MIOA701 is not set
# CONFIG_MACH_PCM027 is not set
# CONFIG_ARCH_PXA_PALM is not set
# CONFIG_PXA_EZX is not set
CONFIG_PXA25x=y
CONFIG_PXA27x=y
CONFIG_PXA_SSP=y
# CONFIG_PXA_PWM is not set
#
@ -253,11 +270,17 @@ CONFIG_TICK_ONESHOT=y
CONFIG_NO_HZ=y
# CONFIG_HIGH_RES_TIMERS is not set
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
CONFIG_VMSPLIT_3G=y
# CONFIG_VMSPLIT_2G is not set
# CONFIG_VMSPLIT_1G is not set
CONFIG_PAGE_OFFSET=0xC0000000
# CONFIG_PREEMPT is not set
CONFIG_HZ=100
CONFIG_AEABI=y
CONFIG_OABI_COMPAT=y
# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
CONFIG_ARCH_FLATMEM_HAS_HOLES=y
# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
CONFIG_SELECT_MEMORY_MODEL=y
CONFIG_FLATMEM_MANUAL=y
# CONFIG_DISCONTIGMEM_MANUAL is not set
@ -284,9 +307,10 @@ CONFIG_CMDLINE="root=1f03 mem=32M"
# CONFIG_KEXEC is not set
#
# CPU Frequency scaling
# CPU Power Management
#
# CONFIG_CPU_FREQ is not set
# CONFIG_CPU_IDLE is not set
#
# Floating point emulation
@ -316,10 +340,6 @@ CONFIG_SUSPEND=y
CONFIG_SUSPEND_FREEZER=y
CONFIG_APM_EMULATION=m
CONFIG_ARCH_SUSPEND_POSSIBLE=y
#
# Networking
#
CONFIG_NET=y
#
@ -402,6 +422,7 @@ CONFIG_BT_HIDP=m
#
CONFIG_BT_HCIUSB=m
CONFIG_BT_HCIUSB_SCO=y
# CONFIG_BT_HCIBTUSB is not set
# CONFIG_BT_HCIBTSDIO is not set
# CONFIG_BT_HCIUART is not set
# CONFIG_BT_HCIBCM203X is not set
@ -419,6 +440,7 @@ CONFIG_BT_HCIUSB_SCO=y
#
# CONFIG_CFG80211 is not set
CONFIG_WIRELESS_EXT=y
CONFIG_WIRELESS_EXT_SYSFS=y
# CONFIG_MAC80211 is not set
# CONFIG_IEEE80211 is not set
# CONFIG_RFKILL is not set
@ -435,6 +457,8 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
CONFIG_FW_LOADER=m
CONFIG_FIRMWARE_IN_KERNEL=y
CONFIG_EXTRA_FIRMWARE=""
# CONFIG_DEBUG_DRIVER is not set
# CONFIG_DEBUG_DEVRES is not set
# CONFIG_SYS_HYPERVISOR is not set
@ -527,6 +551,7 @@ CONFIG_MTD_NAND=y
# CONFIG_MTD_NAND_ECC_SMC is not set
# CONFIG_MTD_NAND_MUSEUM_IDS is not set
# CONFIG_MTD_NAND_H1900 is not set
CONFIG_MTD_NAND_GPIO=m
CONFIG_MTD_NAND_IDS=y
# CONFIG_MTD_NAND_DISKONCHIP is not set
# CONFIG_MTD_NAND_SHARPSL is not set
@ -636,6 +661,7 @@ CONFIG_SCSI_LOWLEVEL=y
# CONFIG_SCSI_DEBUG is not set
# CONFIG_SCSI_SRP is not set
# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
# CONFIG_SCSI_DH is not set
CONFIG_ATA=m
# CONFIG_ATA_NONSTANDARD is not set
# CONFIG_SATA_PMP is not set
@ -696,17 +722,21 @@ CONFIG_PATA_PCMCIA=m
# CONFIG_PATA_VIA is not set
# CONFIG_PATA_WINBOND is not set
# CONFIG_PATA_PLATFORM is not set
# CONFIG_PATA_SCH is not set
# CONFIG_MD is not set
# CONFIG_FUSION is not set
#
# IEEE 1394 (FireWire) support
#
#
# Enable only one of the two stacks, unless you know what you are doing
#
# CONFIG_FIREWIRE is not set
# CONFIG_IEEE1394 is not set
# CONFIG_I2O is not set
CONFIG_NETDEVICES=y
# CONFIG_NETDEVICES_MULTIQUEUE is not set
# CONFIG_DUMMY is not set
# CONFIG_BONDING is not set
# CONFIG_MACVLAN is not set
@ -725,6 +755,7 @@ CONFIG_MII=y
# CONFIG_SMC91X is not set
CONFIG_DM9000=y
CONFIG_DM9000_DEBUGLEVEL=1
# CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL is not set
# CONFIG_SMC911X is not set
# CONFIG_NET_TULIP is not set
# CONFIG_HP100 is not set
@ -780,7 +811,6 @@ CONFIG_LIBERTAS_SDIO=m
# CONFIG_PRISM54 is not set
# CONFIG_USB_ZD1201 is not set
# CONFIG_USB_NET_RNDIS_WLAN is not set
# CONFIG_IWLWIFI is not set
# CONFIG_IWLWIFI_LEDS is not set
# CONFIG_HOSTAP is not set
@ -853,17 +883,18 @@ CONFIG_INPUT_TOUCHSCREEN=y
# CONFIG_TOUCHSCREEN_GUNZE is not set
# CONFIG_TOUCHSCREEN_ELO is not set
# CONFIG_TOUCHSCREEN_MTOUCH is not set
# CONFIG_TOUCHSCREEN_INEXIO is not set
# CONFIG_TOUCHSCREEN_MK712 is not set
# CONFIG_TOUCHSCREEN_PENMOUNT is not set
# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
CONFIG_TOUCHSCREEN_UCB1400=m
CONFIG_TOUCHSCREEN_WM97XX=m
# CONFIG_TOUCHSCREEN_WM9705 is not set
CONFIG_TOUCHSCREEN_WM9712=y
# CONFIG_TOUCHSCREEN_WM9713 is not set
# CONFIG_TOUCHSCREEN_WM97XX_MAINSTONE is not set
# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
# CONFIG_INPUT_MISC is not set
#
@ -880,6 +911,7 @@ CONFIG_SERIO_LIBPS2=y
# Character devices
#
CONFIG_VT=y
CONFIG_CONSOLE_TRANSLATIONS=y
CONFIG_VT_CONSOLE=y
CONFIG_HW_CONSOLE=y
# CONFIG_VT_HW_CONSOLE_BINDING is not set
@ -922,45 +954,66 @@ CONFIG_DEVPORT=y
CONFIG_I2C=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_CHARDEV=m
CONFIG_I2C_HELPER_AUTO=y
#
# I2C Hardware Bus support
#
#
# PC SMBus host controller drivers
#
# CONFIG_I2C_ALI1535 is not set
# CONFIG_I2C_ALI1563 is not set
# CONFIG_I2C_ALI15X3 is not set
# CONFIG_I2C_AMD756 is not set
# CONFIG_I2C_AMD8111 is not set
# CONFIG_I2C_GPIO is not set
# CONFIG_I2C_I801 is not set
# CONFIG_I2C_I810 is not set
CONFIG_I2C_PXA=y
# CONFIG_I2C_PXA_SLAVE is not set
# CONFIG_I2C_ISCH is not set
# CONFIG_I2C_PIIX4 is not set
# CONFIG_I2C_NFORCE2 is not set
# CONFIG_I2C_OCORES is not set
# CONFIG_I2C_PARPORT_LIGHT is not set
# CONFIG_I2C_PROSAVAGE is not set
# CONFIG_I2C_SAVAGE4 is not set
# CONFIG_I2C_SIMTEC is not set
# CONFIG_I2C_SIS5595 is not set
# CONFIG_I2C_SIS630 is not set
# CONFIG_I2C_SIS96X is not set
# CONFIG_I2C_TAOS_EVM is not set
# CONFIG_I2C_STUB is not set
# CONFIG_I2C_TINY_USB is not set
# CONFIG_I2C_VIA is not set
# CONFIG_I2C_VIAPRO is not set
#
# I2C system bus drivers (mostly embedded / system-on-chip)
#
# CONFIG_I2C_GPIO is not set
# CONFIG_I2C_OCORES is not set
CONFIG_I2C_PXA=y
# CONFIG_I2C_PXA_SLAVE is not set
# CONFIG_I2C_SIMTEC is not set
#
# External I2C/SMBus adapter drivers
#
# CONFIG_I2C_PARPORT_LIGHT is not set
# CONFIG_I2C_TAOS_EVM is not set
# CONFIG_I2C_TINY_USB is not set
#
# Graphics adapter I2C/DDC channel drivers
#
# CONFIG_I2C_VOODOO3 is not set
#
# Other I2C/SMBus bus drivers
#
# CONFIG_I2C_PCA_PLATFORM is not set
# CONFIG_I2C_STUB is not set
#
# Miscellaneous I2C Chip support
#
# CONFIG_DS1682 is not set
# CONFIG_AT24 is not set
# CONFIG_SENSORS_EEPROM is not set
# CONFIG_SENSORS_PCF8574 is not set
# CONFIG_PCF8575 is not set
# CONFIG_SENSORS_PCA9539 is not set
# CONFIG_SENSORS_PCF8591 is not set
# CONFIG_TPS65010 is not set
# CONFIG_SENSORS_MAX6875 is not set
@ -970,25 +1023,31 @@ CONFIG_I2C_PXA=y
# CONFIG_I2C_DEBUG_BUS is not set
# CONFIG_I2C_DEBUG_CHIP is not set
# CONFIG_SPI is not set
CONFIG_HAVE_GPIO_LIB=y
#
# GPIO Support
#
CONFIG_ARCH_REQUIRE_GPIOLIB=y
CONFIG_GPIOLIB=y
# CONFIG_DEBUG_GPIO is not set
# CONFIG_GPIO_SYSFS is not set
#
# I2C GPIO expanders:
#
# CONFIG_GPIO_MAX732X is not set
# CONFIG_GPIO_PCA953X is not set
# CONFIG_GPIO_PCF857X is not set
#
# PCI GPIO expanders:
#
# CONFIG_GPIO_BT8XX is not set
#
# SPI GPIO expanders:
#
# CONFIG_W1 is not set
# CONFIG_POWER_SUPPLY is not set
# CONFIG_HWMON is not set
# CONFIG_THERMAL is not set
# CONFIG_THERMAL_HWMON is not set
# CONFIG_WATCHDOG is not set
#
@ -1000,10 +1059,16 @@ CONFIG_SSB_POSSIBLE=y
#
# Multifunction device drivers
#
# CONFIG_MFD_CORE is not set
# CONFIG_MFD_SM501 is not set
# CONFIG_MFD_ASIC3 is not set
# CONFIG_HTC_EGPIO is not set
# CONFIG_HTC_PASIC3 is not set
# CONFIG_UCB1400_CORE is not set
# CONFIG_MFD_TMIO is not set
# CONFIG_MFD_T7L66XB is not set
# CONFIG_MFD_TC6387XB is not set
# CONFIG_MFD_TC6393XB is not set
#
# Multimedia devices
@ -1014,6 +1079,7 @@ CONFIG_SSB_POSSIBLE=y
#
# CONFIG_VIDEO_DEV is not set
# CONFIG_DVB_CORE is not set
# CONFIG_VIDEO_MEDIA is not set
#
# Multimedia drivers
@ -1038,7 +1104,6 @@ CONFIG_FB_CFB_IMAGEBLIT=y
# CONFIG_FB_SYS_IMAGEBLIT is not set
# CONFIG_FB_FOREIGN_ENDIAN is not set
# CONFIG_FB_SYS_FOPS is not set
CONFIG_FB_DEFERRED_IO=y
# CONFIG_FB_SVGALIB is not set
# CONFIG_FB_MACMODES is not set
# CONFIG_FB_BACKLIGHT is not set
@ -1071,12 +1136,14 @@ CONFIG_FB_DEFERRED_IO=y
# CONFIG_FB_TRIDENT is not set
# CONFIG_FB_ARK is not set
# CONFIG_FB_PM3 is not set
# CONFIG_FB_CARMINE is not set
CONFIG_FB_PXA=y
# CONFIG_FB_PXA_SMARTPANEL is not set
CONFIG_FB_PXA_PARAMETERS=y
CONFIG_FB_MBX=m
# CONFIG_FB_AM200EPD is not set
# CONFIG_FB_W100 is not set
# CONFIG_FB_VIRTUAL is not set
# CONFIG_FB_METRONOME is not set
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
#
@ -1099,15 +1166,7 @@ CONFIG_LOGO=y
CONFIG_LOGO_LINUX_MONO=y
CONFIG_LOGO_LINUX_VGA16=y
CONFIG_LOGO_LINUX_CLUT224=y
#
# Sound
#
CONFIG_SOUND=m
#
# Advanced Linux Sound Architecture
#
CONFIG_SND=m
CONFIG_SND_TIMER=m
CONFIG_SND_PCM=m
@ -1121,19 +1180,15 @@ CONFIG_SND_SUPPORT_OLD_API=y
CONFIG_SND_VERBOSE_PROCFS=y
# CONFIG_SND_VERBOSE_PRINTK is not set
# CONFIG_SND_DEBUG is not set
#
# Generic devices
#
CONFIG_SND_VMASTER=y
CONFIG_SND_AC97_CODEC=m
CONFIG_SND_DRIVERS=y
# CONFIG_SND_DUMMY is not set
# CONFIG_SND_MTPAV is not set
# CONFIG_SND_SERIAL_U16550 is not set
# CONFIG_SND_MPU401 is not set
#
# PCI devices
#
# CONFIG_SND_AC97_POWER_SAVE is not set
CONFIG_SND_PCI=y
# CONFIG_SND_AD1889 is not set
# CONFIG_SND_ALS300 is not set
# CONFIG_SND_ALI5451 is not set
@ -1193,42 +1248,16 @@ CONFIG_SND_AC97_CODEC=m
# CONFIG_SND_VIRTUOSO is not set
# CONFIG_SND_VX222 is not set
# CONFIG_SND_YMFPCI is not set
# CONFIG_SND_AC97_POWER_SAVE is not set
#
# ALSA ARM devices
#
CONFIG_SND_ARM=y
CONFIG_SND_PXA2XX_PCM=m
CONFIG_SND_PXA2XX_AC97=m
#
# USB devices
#
CONFIG_SND_USB=y
# CONFIG_SND_USB_AUDIO is not set
# CONFIG_SND_USB_CAIAQ is not set
#
# PCMCIA devices
#
CONFIG_SND_PCMCIA=y
# CONFIG_SND_VXPOCKET is not set
# CONFIG_SND_PDAUDIOCF is not set
#
# System on Chip audio support
#
# CONFIG_SND_SOC is not set
#
# ALSA SoC audio for Freescale SOCs
#
#
# SoC Audio for the Texas Instruments OMAP
#
#
# Open Sound System
#
# CONFIG_SOUND_PRIME is not set
CONFIG_AC97_BUS=m
CONFIG_HID_SUPPORT=y
@ -1261,12 +1290,15 @@ CONFIG_USB_DEVICEFS=y
# CONFIG_USB_OTG is not set
# CONFIG_USB_OTG_WHITELIST is not set
# CONFIG_USB_OTG_BLACKLIST_HUB is not set
CONFIG_USB_MON=y
#
# USB Host Controller Drivers
#
# CONFIG_USB_C67X00_HCD is not set
# CONFIG_USB_EHCI_HCD is not set
# CONFIG_USB_ISP116X_HCD is not set
# CONFIG_USB_ISP1760_HCD is not set
CONFIG_USB_OHCI_HCD=y
# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
@ -1274,12 +1306,14 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y
# CONFIG_USB_UHCI_HCD is not set
# CONFIG_USB_SL811_HCD is not set
# CONFIG_USB_R8A66597_HCD is not set
# CONFIG_USB_MUSB_HDRC is not set
#
# USB Device Class drivers
#
# CONFIG_USB_ACM is not set
# CONFIG_USB_PRINTER is not set
# CONFIG_USB_WDM is not set
#
# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
@ -1309,7 +1343,6 @@ CONFIG_USB_STORAGE=y
#
# CONFIG_USB_MDC800 is not set
# CONFIG_USB_MICROTEK is not set
CONFIG_USB_MON=y
#
# USB port drivers
@ -1322,7 +1355,6 @@ CONFIG_USB_MON=y
# CONFIG_USB_EMI62 is not set
# CONFIG_USB_EMI26 is not set
# CONFIG_USB_ADUTUX is not set
# CONFIG_USB_AUERSWALD is not set
# CONFIG_USB_RIO500 is not set
# CONFIG_USB_LEGOTOWER is not set
# CONFIG_USB_LCD is not set
@ -1338,6 +1370,7 @@ CONFIG_USB_MON=y
# CONFIG_USB_TRANCEVIBRATOR is not set
# CONFIG_USB_IOWARRIOR is not set
# CONFIG_USB_TEST is not set
# CONFIG_USB_ISIGHTFW is not set
# CONFIG_USB_GADGET is not set
CONFIG_MMC=m
# CONFIG_MMC_DEBUG is not set
@ -1349,6 +1382,7 @@ CONFIG_MMC=m
CONFIG_MMC_BLOCK=m
CONFIG_MMC_BLOCK_BOUNCE=y
# CONFIG_SDIO_UART is not set
# CONFIG_MMC_TEST is not set
#
# MMC/SD Host Controller Drivers
@ -1356,14 +1390,19 @@ CONFIG_MMC_BLOCK_BOUNCE=y
CONFIG_MMC_PXA=m
# CONFIG_MMC_SDHCI is not set
# CONFIG_MMC_TIFM_SD is not set
# CONFIG_MMC_SDRICOH_CS is not set
# CONFIG_MEMSTICK is not set
# CONFIG_ACCESSIBILITY is not set
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
#
# LED drivers
#
# CONFIG_LEDS_PCA9532 is not set
# CONFIG_LEDS_GPIO is not set
CONFIG_LEDS_CM_X270=y
# CONFIG_LEDS_PCA955X is not set
#
# LED Triggers
@ -1401,6 +1440,7 @@ CONFIG_RTC_INTF_DEV=y
# CONFIG_RTC_DRV_PCF8583 is not set
# CONFIG_RTC_DRV_M41T80 is not set
# CONFIG_RTC_DRV_S35390A is not set
# CONFIG_RTC_DRV_FM3130 is not set
#
# SPI RTC drivers
@ -1422,6 +1462,15 @@ CONFIG_RTC_DRV_V3020=y
# on-CPU RTC drivers
#
CONFIG_RTC_DRV_SA1100=y
# CONFIG_DMADEVICES is not set
#
# Voltage and Current regulators
#
# CONFIG_REGULATOR is not set
# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
# CONFIG_REGULATOR_BQ24022 is not set
# CONFIG_UIO is not set
#
@ -1501,6 +1550,7 @@ CONFIG_JFFS2_RTIME=y
# CONFIG_CRAMFS is not set
# CONFIG_VXFS_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_OMFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_ROMFS_FS is not set
@ -1511,13 +1561,12 @@ CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
# CONFIG_NFS_V3_ACL is not set
# CONFIG_NFS_V4 is not set
# CONFIG_NFSD is not set
CONFIG_ROOT_NFS=y
# CONFIG_NFSD is not set
CONFIG_LOCKD=y
CONFIG_LOCKD_V4=y
CONFIG_NFS_COMMON=y
CONFIG_SUNRPC=y
# CONFIG_SUNRPC_BIND34 is not set
# CONFIG_RPCSEC_GSS_KRB5 is not set
# CONFIG_RPCSEC_GSS_SPKM3 is not set
# CONFIG_SMB_FS is not set
@ -1626,6 +1675,7 @@ CONFIG_DEBUG_KERNEL=y
# CONFIG_DEBUG_INFO is not set
# CONFIG_DEBUG_VM is not set
# CONFIG_DEBUG_WRITECOUNT is not set
# CONFIG_DEBUG_MEMORY_INIT is not set
# CONFIG_DEBUG_LIST is not set
# CONFIG_DEBUG_SG is not set
CONFIG_FRAME_POINTER=y
@ -1633,7 +1683,17 @@ CONFIG_FRAME_POINTER=y
# CONFIG_RCU_TORTURE_TEST is not set
# CONFIG_BACKTRACE_SELF_TEST is not set
# CONFIG_FAULT_INJECTION is not set
# CONFIG_LATENCYTOP is not set
CONFIG_SYSCTL_SYSCALL_CHECK=y
CONFIG_HAVE_FTRACE=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
# CONFIG_FTRACE is not set
# CONFIG_IRQSOFF_TRACER is not set
# CONFIG_SCHED_TRACER is not set
# CONFIG_CONTEXT_SWITCH_TRACER is not set
# CONFIG_SAMPLES is not set
CONFIG_HAVE_ARCH_KGDB=y
# CONFIG_KGDB is not set
CONFIG_DEBUG_USER=y
CONFIG_DEBUG_ERRORS=y
# CONFIG_DEBUG_STACK_USAGE is not set
@ -1689,6 +1749,10 @@ CONFIG_CRYPTO=y
# CONFIG_CRYPTO_MD4 is not set
# CONFIG_CRYPTO_MD5 is not set
# CONFIG_CRYPTO_MICHAEL_MIC is not set
# CONFIG_CRYPTO_RMD128 is not set
# CONFIG_CRYPTO_RMD160 is not set
# CONFIG_CRYPTO_RMD256 is not set
# CONFIG_CRYPTO_RMD320 is not set
# CONFIG_CRYPTO_SHA1 is not set
# CONFIG_CRYPTO_SHA256 is not set
# CONFIG_CRYPTO_SHA512 is not set
@ -1729,6 +1793,7 @@ CONFIG_BITREVERSE=y
# CONFIG_GENERIC_FIND_NEXT_BIT is not set
CONFIG_CRC_CCITT=m
# CONFIG_CRC16 is not set
# CONFIG_CRC_T10DIF is not set
# CONFIG_CRC_ITU_T is not set
CONFIG_CRC32=y
# CONFIG_CRC7 is not set

3
arch/arm/include/asm/mach/udc_pxa2xx.h
View file

@ -18,8 +18,7 @@ struct pxa2xx_udc_mach_info {
/* Boards following the design guidelines in the developer's manual,
* with on-chip GPIOs not Lubbock's weird hardware, can have a sane
* VBUS IRQ and omit the methods above. Store the GPIO number
* here; for GPIO 0, also mask in one of the pxa_gpio_mode() bits.
* Note that sometimes the signals go through inverters...
* here. Note that sometimes the signals go through inverters...
*/
bool gpio_vbus_inverted;
u16 gpio_vbus; /* high == vbus present */

6
arch/arm/kernel/ecard.c
View file

@ -587,8 +587,7 @@ ecard_irq_handler(unsigned int irq, struct irq_desc *desc)
pending = ecard_default_ops.irqpending(ec);
if (pending) {
struct irq_desc *d = irq_desc + ec->irq;
desc_handle_irq(ec->irq, d);
generic_handle_irq(ec->irq);
called ++;
}
}
@ -622,7 +621,6 @@ ecard_irqexp_handler(unsigned int irq, struct irq_desc *desc)
ecard_t *ec = slot_to_ecard(slot);
if (ec->claimed) {
struct irq_desc *d = irq_desc + ec->irq;
/*
* this ugly code is so that we can operate a
* prioritorising system:
@ -635,7 +633,7 @@ ecard_irqexp_handler(unsigned int irq, struct irq_desc *desc)
* Serial cards should go in 0/1, ethernet/scsi in 2/3
* otherwise you will lose serial data at high speeds!
*/
desc_handle_irq(ec->irq, d);
generic_handle_irq(ec->irq);
} else {
printk(KERN_WARNING "card%d: interrupt from unclaimed "
"card???\n", slot);

11
arch/arm/kernel/irq.c
View file

@ -112,18 +112,17 @@ static struct irq_desc bad_irq_desc = {
asmlinkage void __exception asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
{
struct pt_regs *old_regs = set_irq_regs(regs);
struct irq_desc *desc = irq_desc + irq;
irq_enter();
/*
* Some hardware gives randomly wrong interrupts. Rather
* than crashing, do something sensible.
*/
if (irq >= NR_IRQS)
desc = &bad_irq_desc;
irq_enter();
desc_handle_irq(irq, desc);
handle_bad_irq(irq, &bad_irq_desc);
else
generic_handle_irq(irq);
/* AT91 specific workaround */
irq_finish(irq);

3
arch/arm/mach-at91/gpio.c
View file

@ -404,7 +404,6 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
}
pin = bank->chipbase;
gpio = &irq_desc[pin];
while (isr) {
if (isr & 1) {
@ -417,7 +416,7 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
gpio_irq_mask(pin);
}
else
desc_handle_irq(pin, gpio);
generic_handle_irq(pin);
}
pin++;
gpio++;

5
arch/arm/mach-davinci/gpio.c
View file

@ -201,7 +201,6 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc)
desc->chip->ack(irq);
while (1) {
u32 status;
struct irq_desc *gpio;
int n;
int res;
@ -215,12 +214,10 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc)
/* now demux them to the right lowlevel handler */
n = (int)get_irq_data(irq);
gpio = &irq_desc[n];
while (status) {
res = ffs(status);
n += res;
gpio += res;
desc_handle_irq(n - 1, gpio - 1);
generic_handle_irq(n - 1);
status >>= res;
}
}

7
arch/arm/mach-ep93xx/core.c
View file

@ -192,8 +192,7 @@ static void ep93xx_gpio_ab_irq_handler(unsigned int irq, struct irq_desc *desc)
for (i = 0; i < 8; i++) {
if (status & (1 << i)) {
int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_A(0)) + i;
desc = irq_desc + gpio_irq;
desc_handle_irq(gpio_irq, desc);
generic_handle_irq(gpio_irq);
}
}
@ -202,7 +201,7 @@ static void ep93xx_gpio_ab_irq_handler(unsigned int irq, struct irq_desc *desc)
if (status & (1 << i)) {
int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_B(0)) + i;
desc = irq_desc + gpio_irq;
desc_handle_irq(gpio_irq, desc);
generic_handle_irq(gpio_irq);
}
}
}
@ -217,7 +216,7 @@ static void ep93xx_gpio_f_irq_handler(unsigned int irq, struct irq_desc *desc)
int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */
int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_F(0)) + port_f_idx;
desc_handle_irq(gpio_irq, irq_desc + gpio_irq);
generic_handle_irq(gpio_irq);
}
static void ep93xx_gpio_irq_ack(unsigned int irq)

3
arch/arm/mach-footbridge/isa-irq.c
View file

@ -94,8 +94,7 @@ isa_irq_handler(unsigned int irq, struct irq_desc *desc)
return;
}
desc = irq_desc + isa_irq;
desc_handle_irq(isa_irq, desc);
generic_handle_irq(isa_irq);
}
static struct irqaction irq_cascade = {

4
arch/arm/mach-h720x/common.c
View file

@ -104,14 +104,12 @@ h720x_gpio_handler(unsigned int mask, unsigned int irq,
struct irq_desc *desc)
{
IRQDBG("%s irq: %d\n", __func__, irq);
desc = irq_desc + irq;
while (mask) {
if (mask & 1) {
IRQDBG("handling irq %d\n", irq);
desc_handle_irq(irq, desc);
generic_handle_irq(irq);
}
irq++;
desc++;
mask >>= 1;
}
}

4
arch/arm/mach-h720x/cpu-h7202.c
View file

@ -120,12 +120,10 @@ h7202_timerx_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
mask >>= 1;
irq = IRQ_TIMER1;
desc = irq_desc + irq;
while (mask) {
if (mask & 1)
desc_handle_irq(irq, desc);
generic_handle_irq(irq);
irq++;
desc++;
mask >>= 1;
}
}

4
arch/arm/mach-imx/irq.c
View file

@ -182,14 +182,12 @@ static void
imx_gpio_handler(unsigned int mask, unsigned int irq,
struct irq_desc *desc)
{
desc = irq_desc + irq;
while (mask) {
if (mask & 1) {
DEBUG_IRQ("handling irq %d\n", irq);
desc_handle_irq(irq, desc);
generic_handle_irq(irq);
}
irq++;
desc++;
mask >>= 1;
}
}

3
arch/arm/mach-integrator/integrator_cp.c
View file

@ -217,8 +217,7 @@ sic_handle_irq(unsigned int irq, struct irq_desc *desc)
irq += IRQ_SIC_START;
desc = irq_desc + irq;
desc_handle_irq(irq, desc);
generic_handle_irq(irq);
} while (status);
}

3
arch/arm/mach-iop13xx/msi.c
View file

@ -110,8 +110,7 @@ static void iop13xx_msi_handler(unsigned int irq, struct irq_desc *desc)
do {
j = find_first_bit(&status, 32);
(write_imipr[i])(1 << j); /* write back to clear bit */
desc = irq_desc + IRQ_IOP13XX_MSI_0 + j + (32*i);
desc_handle_irq(IRQ_IOP13XX_MSI_0 + j + (32*i), desc);
generic_handle_irq(IRQ_IOP13XX_MSI_0 + j + (32*i));
status = (read_imipr[i])();
} while (status);
}

6
arch/arm/mach-ixp2000/core.c
View file

@ -304,8 +304,7 @@ static void ixp2000_GPIO_irq_handler(unsigned int irq, struct irq_desc *desc)
for (i = 0; i <= 7; i++) {
if (status & (1<<i)) {
desc = irq_desc + i + IRQ_IXP2000_GPIO0;
desc_handle_irq(i + IRQ_IXP2000_GPIO0, desc);
generic_handle_irq(i + IRQ_IXP2000_GPIO0);
}
}
}
@ -397,8 +396,7 @@ static void ixp2000_err_irq_handler(unsigned int irq, struct irq_desc *desc)
for(i = 31; i >= 0; i--) {
if(status & (1 << i)) {
desc = irq_desc + IRQ_IXP2000_DRAM0_MIN_ERR + i;
desc_handle_irq(IRQ_IXP2000_DRAM0_MIN_ERR + i, desc);
generic_handle_irq(IRQ_IXP2000_DRAM0_MIN_ERR + i);
}
}
}

4
arch/arm/mach-ixp2000/ixdp2x00.c
View file

@ -129,10 +129,8 @@ static void ixdp2x00_irq_handler(unsigned int irq, struct irq_desc *desc)
for(i = 0; i < board_irq_count; i++) {
if(ex_interrupt & (1 << i)) {
struct irq_desc *cpld_desc;
int cpld_irq = IXP2000_BOARD_IRQ(0) + i;
cpld_desc = irq_desc + cpld_irq;
desc_handle_irq(cpld_irq, cpld_desc);
generic_handle_irq(cpld_irq);
}
}

4
arch/arm/mach-ixp2000/ixdp2x01.c
View file

@ -79,10 +79,8 @@ static void ixdp2x01_irq_handler(unsigned int irq, struct irq_desc *desc)
for (i = 0; i < IXP2000_BOARD_IRQS; i++) {
if (ex_interrupt & (1 << i)) {
struct irq_desc *cpld_desc;
int cpld_irq = IXP2000_BOARD_IRQ(0) + i;
cpld_desc = irq_desc + cpld_irq;
desc_handle_irq(cpld_irq, cpld_desc);
generic_handle_irq(cpld_irq);
}
}

4
arch/arm/mach-ixp23xx/core.c
View file

@ -253,7 +253,6 @@ static void pci_handler(unsigned int irq, struct irq_desc *desc)
{
u32 pci_interrupt;
unsigned int irqno;
struct irq_desc *int_desc;
pci_interrupt = *IXP23XX_PCI_XSCALE_INT_STATUS;
@ -268,8 +267,7 @@ static void pci_handler(unsigned int irq, struct irq_desc *desc)
BUG();
}
int_desc = irq_desc + irqno;
desc_handle_irq(irqno, int_desc);
generic_handle_irq(irqno);
desc->chip->unmask(irq);
}

8
arch/arm/mach-ixp23xx/ixdp2351.c
View file

@ -68,11 +68,9 @@ static void ixdp2351_inta_handler(unsigned int irq, struct irq_desc *desc)
for (i = 0; i < IXDP2351_INTA_IRQ_NUM; i++) {
if (ex_interrupt & (1 << i)) {
struct irq_desc *cpld_desc;
int cpld_irq =
IXP23XX_MACH_IRQ(IXDP2351_INTA_IRQ_BASE + i);
cpld_desc = irq_desc + cpld_irq;
desc_handle_irq(cpld_irq, cpld_desc);
generic_handle_irq(cpld_irq);
}
}
@ -105,11 +103,9 @@ static void ixdp2351_intb_handler(unsigned int irq, struct irq_desc *desc)
for (i = 0; i < IXDP2351_INTB_IRQ_NUM; i++) {
if (ex_interrupt & (1 << i)) {
struct irq_desc *cpld_desc;
int cpld_irq =
IXP23XX_MACH_IRQ(IXDP2351_INTB_IRQ_BASE + i);
cpld_desc = irq_desc + cpld_irq;
desc_handle_irq(cpld_irq, cpld_desc);
generic_handle_irq(cpld_irq);
}
}

2
arch/arm/mach-lh7a40x/arch-kev7a400.c
View file

@ -77,7 +77,7 @@ static void kev7a400_cpld_handler (unsigned int irq, struct irq_desc *desc)
irq = IRQ_KEV7A400_CPLD;
for (; mask; mask >>= 1, ++irq)
if (mask & 1)
desc_handle_irq(irq, desc);
generic_handle_irq(irq);
}
void __init lh7a40x_init_board_irq (void)

4
arch/arm/mach-lh7a40x/arch-lpd7a40x.c
View file

@ -214,11 +214,11 @@ static void lpd7a40x_cpld_handler (unsigned int irq, struct irq_desc *desc)
desc->chip->ack (irq);
if ((mask & (1<<0)) == 0) /* WLAN */
IRQ_DISPATCH (IRQ_LPD7A40X_ETH_INT);
generic_handle_irq(IRQ_LPD7A40X_ETH_INT);
#if defined (IRQ_TOUCH)
if ((mask & (1<<1)) == 0) /* Touch */
IRQ_DISPATCH (IRQ_TOUCH);
generic_handle_irq(IRQ_TOUCH);
#endif
desc->chip->unmask (irq); /* Level-triggered need this */

1
arch/arm/mach-lh7a40x/common.h
View file

@ -15,4 +15,3 @@ extern void lh7a404_init_irq (void);
extern void lh7a40x_clcd_init (void);
extern void lh7a40x_init_board_irq (void);
#define IRQ_DISPATCH(irq) desc_handle_irq((irq),(irq_desc + irq))

4
arch/arm/mach-lh7a40x/irq-lpd7a40x.c
View file

@ -63,10 +63,10 @@ static void lh7a40x_cpld_handler (unsigned int irq, struct irq_desc *desc)
desc->chip->ack (irq);
if ((mask & 0x1) == 0) /* WLAN */
IRQ_DISPATCH (IRQ_LPD7A40X_ETH_INT);
generic_handle_irq(IRQ_LPD7A40X_ETH_INT);
if ((mask & 0x2) == 0) /* Touch */
IRQ_DISPATCH (IRQ_LPD7A400_TS);
generic_handle_irq(IRQ_LPD7A400_TS);
desc->chip->unmask (irq); /* Level-triggered need this */
}

5
arch/arm/mach-netx/generic.c
View file

@ -77,15 +77,12 @@ netx_hif_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
stat = ((readl(NETX_DPMAS_INT_EN) &
readl(NETX_DPMAS_INT_STAT)) >> 24) & 0x1f;
desc = irq_desc + NETX_IRQ_HIF_CHAINED(0);
while (stat) {
if (stat & 1) {
DEBUG_IRQ("handling irq %d\n", irq);
desc_handle_irq(irq, desc);
generic_handle_irq(irq);
}
irq++;
desc++;
stat >>= 1;
}
}

5
arch/arm/mach-ns9xxx/board-a9m9750dev.c
View file

@ -86,13 +86,10 @@ static void a9m9750dev_fpga_demux_handler(unsigned int irq,
while (stat != 0) {
int irqno = fls(stat) - 1;
struct irq_desc *fpgadesc;
stat &= ~(1 << irqno);
fpgadesc = irq_desc + FPGA_IRQ(irqno);
desc_handle_irq(FPGA_IRQ(irqno), fpgadesc);
generic_handle_irq(FPGA_IRQ(irqno));
}
desc->chip->unmask(irq);

1
arch/arm/mach-omap1/board-voiceblue.c
View file

@ -21,6 +21,7 @@
#include <linux/reboot.h>
#include <linux/serial_8250.h>
#include <linux/serial_reg.h>
#include <linux/irq.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>

4
arch/arm/mach-omap1/fpga.c
View file

@ -86,7 +86,6 @@ static void fpga_mask_ack_irq(unsigned int irq)
void innovator_fpga_IRQ_demux(unsigned int irq, struct irq_desc *desc)
{
struct irq_desc *d;
u32 stat;
int fpga_irq;
@ -99,8 +98,7 @@ void innovator_fpga_IRQ_demux(unsigned int irq, struct irq_desc *desc)
(fpga_irq < OMAP_FPGA_IRQ_END) && stat;
fpga_irq++, stat >>= 1) {
if (stat & 1) {
d = irq_desc + fpga_irq;
desc_handle_irq(fpga_irq, d);
generic_handle_irq(fpga_irq);
}
}
}

2
arch/arm/mach-orion5x/irq.c
View file

@ -162,7 +162,7 @@ static void orion5x_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
polarity ^= 1 << pin;
writel(polarity, GPIO_IN_POL);
}
desc_handle_irq(irq, desc);
generic_handle_irq(irq);
}
}
}

93
arch/arm/mach-pxa/Kconfig
View file

@ -38,16 +38,23 @@ config ARCH_LUBBOCK
bool "Intel DBPXA250 Development Platform"
select PXA25x
select SA1111
select PXA_HAVE_BOARD_IRQS
config MACH_LOGICPD_PXA270
bool "LogicPD PXA270 Card Engine Development Platform"
select PXA27x
select HAVE_PWM
select PXA_HAVE_BOARD_IRQS
config MACH_MAINSTONE
bool "Intel HCDDBBVA0 Development Platform"
select PXA27x
select HAVE_PWM
select PXA_HAVE_BOARD_IRQS
config MACH_MP900C
bool "Nec Mobilepro 900/c"
select PXA25x
config ARCH_PXA_IDP
bool "Accelent Xscale IDP"
@ -114,10 +121,21 @@ config MACH_TOSA
bool "Enable Sharp SL-6000x (Tosa) Support"
depends on PXA_SHARPSL
select PXA25x
select PXA_HAVE_BOARD_IRQS
config ARCH_VIPER
bool "Arcom/Eurotech VIPER SBC"
select PXA25x
select ISA
select I2C_GPIO
select HAVE_PWM
select PXA_HAVE_BOARD_IRQS
select PXA_HAVE_ISA_IRQS
config ARCH_PXA_ESERIES
bool "PXA based Toshiba e-series PDAs"
select PXA25x
select PXA_HAVE_BOARD_IRQS
config MACH_E330
bool "Toshiba e330"
@ -170,13 +188,41 @@ config MACH_E800
Say Y here if you intend to run this kernel on a Toshiba
e800 family PDA.
config TRIZEPS_PXA
bool "PXA based Keith und Koep Trizeps DIMM-Modules"
config MACH_TRIZEPS4
bool "Keith und Koep Trizeps4 DIMM-Module"
depends on TRIZEPS_PXA
select TRIZEPS_PCMCIA
select PXA27x
config MACH_TRIZEPS4_CONXS
config MACH_TRIZEPS4WL
bool "Keith und Koep Trizeps4-WL DIMM-Module"
depends on TRIZEPS_PXA
select TRIZEPS_PCMCIA
select PXA27x
select PXA_SSP
choice
prompt "Select base board for Trizeps module"
depends on TRIZEPS_PXA
config MACH_TRIZEPS_CONXS
bool "ConXS Eval Board"
depends on MACH_TRIZEPS4
config MACH_TRIZEPS_UCONXS
bool "uConXS Eval Board"
config MACH_TRIZEPS_ANY
bool "another Board"
endchoice
config TRIZEPS_PCMCIA
bool
help
Enable PCMCIA support for Trizeps modules
config MACH_EM_X270
bool "CompuLab EM-x270 platform"
@ -189,6 +235,7 @@ config MACH_COLIBRI
config MACH_ZYLONITE
bool "PXA3xx Development Platform (aka Zylonite)"
select PXA3xx
select PXA_SSP
select HAVE_PWM
config MACH_LITTLETON
@ -207,21 +254,42 @@ config MACH_SAAR
select PXA930
config MACH_ARMCORE
bool "CompuLab CM-X270 modules"
bool "CompuLab CM-X255/CM-X270 modules"
select PXA27x
select IWMMXT
select ZONE_DMA if PCI
select PXA25x
select PXA_SSP
config MACH_CM_X300
bool "CompuLab CM-X300 modules"
select PXA3xx
select CPU_PXA300
config MACH_MAGICIAN
bool "Enable HTC Magician Support"
select PXA27x
select IWMMXT
select PXA_HAVE_BOARD_IRQS
config MACH_MIOA701
bool "Mitac Mio A701 Support"
select PXA27x
select IWMMXT
select LEDS_GPIO
select HAVE_PWM
select GPIO_SYSFS
help
Say Y here if you intend to run this kernel on a
MIO A701. Currently there is only basic support
for this PDA.
config MACH_PCM027
bool "Phytec phyCORE-PXA270 CPU module (PCM-027)"
select PXA27x
select IWMMXT
select PXA_SSP
select PXA_HAVE_BOARD_IRQS
config ARCH_PXA_PALM
bool "PXA based Palm PDAs"
@ -237,6 +305,16 @@ config MACH_PALMTX
Say Y here if you intend to run this kernel on a Palm T|X
handheld computer.
config MACH_PALMZ72
bool "Palm Zire 72"
default y
depends on ARCH_PXA_PALM
select PXA27x
select IWMMXT
help
Say Y here if you intend to run this kernel on Palm Zire 72
handheld computer.
config MACH_PCM990_BASEBOARD
bool "PHYTEC PCM-990 development board"
select HAVE_PWM
@ -257,6 +335,9 @@ config PCM990_DISPLAY_NONE
endchoice
config MACH_AM200EPD
depends on MACH_GUMSTIX_F
bool "Enable AM200EPD board support"
config PXA_EZX
bool "Motorola EZX Platform"
@ -344,4 +425,10 @@ config TOSA_BT
This is a simple driver that is able to control
the state of built in bluetooth chip on tosa.
config PXA_HAVE_BOARD_IRQS
bool
config PXA_HAVE_ISA_IRQS
bool
endif

37
arch/arm/mach-pxa/Makefile
View file

@ -6,7 +6,12 @@
obj-y += clock.o devices.o generic.o irq.o dma.o \
time.o gpio.o reset.o
obj-$(CONFIG_PM) += pm.o sleep.o standby.o
obj-$(CONFIG_CPU_FREQ) += cpu-pxa.o
ifeq ($(CONFIG_CPU_FREQ),y)
obj-$(CONFIG_PXA25x) += cpufreq-pxa2xx.o
obj-$(CONFIG_PXA27x) += cpufreq-pxa2xx.o
obj-$(CONFIG_PXA3xx) += cpufreq-pxa3xx.o
endif
# Generic drivers that other drivers may depend upon
obj-$(CONFIG_PXA_SSP) += ssp.o
@ -22,27 +27,33 @@ obj-$(CONFIG_CPU_PXA930) += pxa930.o
# Specific board support
obj-$(CONFIG_ARCH_GUMSTIX) += gumstix.o
obj-$(CONFIG_MACH_AM200EPD) += am200epd.o
obj-$(CONFIG_ARCH_LUBBOCK) += lubbock.o
obj-$(CONFIG_MACH_LOGICPD_PXA270) += lpd270.o
obj-$(CONFIG_MACH_MAINSTONE) += mainstone.o
obj-$(CONFIG_MACH_MP900C) += mp900.o
obj-$(CONFIG_ARCH_PXA_IDP) += idp.o
obj-$(CONFIG_MACH_TRIZEPS4) += trizeps4.o
obj-$(CONFIG_MACH_COLIBRI) += colibri.o
obj-$(CONFIG_PXA_SHARP_C7xx) += corgi.o corgi_ssp.o corgi_lcd.o sharpsl_pm.o corgi_pm.o
obj-$(CONFIG_PXA_SHARP_Cxx00) += spitz.o corgi_ssp.o corgi_lcd.o sharpsl_pm.o spitz_pm.o
obj-$(CONFIG_MACH_AKITA) += akita-ioexp.o
obj-$(CONFIG_MACH_POODLE) += poodle.o corgi_ssp.o
obj-$(CONFIG_PXA_SHARP_C7xx) += corgi.o sharpsl_pm.o corgi_pm.o
obj-$(CONFIG_PXA_SHARP_Cxx00) += spitz.o sharpsl_pm.o spitz_pm.o
obj-$(CONFIG_MACH_POODLE) += poodle.o
obj-$(CONFIG_MACH_PCM027) += pcm027.o
obj-$(CONFIG_MACH_PCM990_BASEBOARD) += pcm990-baseboard.o
obj-$(CONFIG_MACH_TOSA) += tosa.o
obj-$(CONFIG_MACH_EM_X270) += em-x270.o
obj-$(CONFIG_MACH_MAGICIAN) += magician.o
obj-$(CONFIG_ARCH_PXA_ESERIES) += eseries.o eseries_udc.o
obj-$(CONFIG_MACH_E740) += e740_lcd.o
obj-$(CONFIG_MACH_E750) += e750_lcd.o
obj-$(CONFIG_MACH_E400) += e400_lcd.o
obj-$(CONFIG_MACH_E800) += e800_lcd.o
obj-$(CONFIG_MACH_MIOA701) += mioa701.o mioa701_bootresume.o
obj-$(CONFIG_ARCH_PXA_ESERIES) += eseries.o
obj-$(CONFIG_MACH_E330) += e330.o
obj-$(CONFIG_MACH_E350) += e350.o
obj-$(CONFIG_MACH_E740) += e740.o
obj-$(CONFIG_MACH_E750) += e750.o
obj-$(CONFIG_MACH_E400) += e400.o
obj-$(CONFIG_MACH_E800) += e800.o
obj-$(CONFIG_MACH_PALMTX) += palmtx.o
obj-$(CONFIG_MACH_PALMZ72) += palmz72.o
obj-$(CONFIG_ARCH_VIPER) += viper.o
ifeq ($(CONFIG_MACH_ZYLONITE),y)
obj-y += zylonite.o
@ -53,7 +64,8 @@ obj-$(CONFIG_MACH_LITTLETON) += littleton.o
obj-$(CONFIG_MACH_TAVOREVB) += tavorevb.o
obj-$(CONFIG_MACH_SAAR) += saar.o
obj-$(CONFIG_MACH_ARMCORE) += cm-x270.o
obj-$(CONFIG_MACH_ARMCORE) += cm-x2xx.o cm-x255.o cm-x270.o
obj-$(CONFIG_MACH_CM_X300) += cm-x300.o
obj-$(CONFIG_PXA_EZX) += ezx.o
# Support for blinky lights
@ -61,12 +73,11 @@ led-y := leds.o
led-$(CONFIG_ARCH_LUBBOCK) += leds-lubbock.o
led-$(CONFIG_MACH_MAINSTONE) += leds-mainstone.o
led-$(CONFIG_ARCH_PXA_IDP) += leds-idp.o
led-$(CONFIG_MACH_TRIZEPS4) += leds-trizeps4.o
obj-$(CONFIG_LEDS) += $(led-y)
ifeq ($(CONFIG_PCI),y)
obj-$(CONFIG_MACH_ARMCORE) += cm-x270-pci.o
obj-$(CONFIG_MACH_ARMCORE) += cm-x2xx-pci.o
endif
obj-$(CONFIG_TOSA_BT) += tosa-bt.o

222
arch/arm/mach-pxa/akita-ioexp.c
View file

@ -1,222 +0,0 @@
/*
* Support for the Extra GPIOs on the Sharp SL-C1000 (Akita)
* (uses a Maxim MAX7310 8 Port IO Expander)
*
* Copyright 2005 Openedhand Ltd.
*
* Author: Richard Purdie <richard@openedhand.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/slab.h>
#include <linux/workqueue.h>
#include <mach/akita.h>
/* MAX7310 Regiser Map */
#define MAX7310_INPUT 0x00
#define MAX7310_OUTPUT 0x01
#define MAX7310_POLINV 0x02
#define MAX7310_IODIR 0x03 /* 1 = Input, 0 = Output */
#define MAX7310_TIMEOUT 0x04
/* Addresses to scan */
static const unsigned short normal_i2c[] = { 0x18, I2C_CLIENT_END };
/* I2C Magic */
I2C_CLIENT_INSMOD;
static int max7310_write(struct i2c_client *client, int address, int data);
static struct i2c_client max7310_template;
static void akita_ioexp_work(struct work_struct *private_);
static struct device *akita_ioexp_device;
static unsigned char ioexp_output_value = AKITA_IOEXP_IO_OUT;
DECLARE_WORK(akita_ioexp, akita_ioexp_work);
/*
* MAX7310 Access
*/
static int max7310_config(struct device *dev, int iomode, int polarity)
{
int ret;
struct i2c_client *client = to_i2c_client(dev);
ret = max7310_write(client, MAX7310_POLINV, polarity);
if (ret < 0)
return ret;
ret = max7310_write(client, MAX7310_IODIR, iomode);
return ret;
}
static int max7310_set_ouputs(struct device *dev, int outputs)
{
struct i2c_client *client = to_i2c_client(dev);
return max7310_write(client, MAX7310_OUTPUT, outputs);
}
/*
* I2C Functions
*/
static int max7310_write(struct i2c_client *client, int address, int value)
{
u8 data[2];
data[0] = address & 0xff;
data[1] = value & 0xff;
if (i2c_master_send(client, data, 2) == 2)
return 0;
return -1;
}
static int max7310_detect(struct i2c_adapter *adapter, int address, int kind)
{
struct i2c_client *new_client;
int err;
if (!(new_client = kmalloc(sizeof(struct i2c_client), GFP_KERNEL)))
return -ENOMEM;
max7310_template.adapter = adapter;
max7310_template.addr = address;
memcpy(new_client, &max7310_template, sizeof(struct i2c_client));
if ((err = i2c_attach_client(new_client))) {
kfree(new_client);
return err;
}
max7310_config(&new_client->dev, AKITA_IOEXP_IO_DIR, 0);
akita_ioexp_device = &new_client->dev;
schedule_work(&akita_ioexp);
return 0;
}
static int max7310_attach_adapter(struct i2c_adapter *adapter)
{
return i2c_probe(adapter, &addr_data, max7310_detect);
}
static int max7310_detach_client(struct i2c_client *client)
{
int err;
akita_ioexp_device = NULL;
if ((err = i2c_detach_client(client)))
return err;
kfree(client);
return 0;
}
static struct i2c_driver max7310_i2c_driver = {
.driver = {
.name = "akita-max7310",
},
.id = I2C_DRIVERID_AKITAIOEXP,
.attach_adapter = max7310_attach_adapter,
.detach_client = max7310_detach_client,
};
static struct i2c_client max7310_template = {
name: "akita-max7310",
driver: &max7310_i2c_driver,
};
void akita_set_ioexp(struct device *dev, unsigned char bit)
{
ioexp_output_value |= bit;
if (akita_ioexp_device)
schedule_work(&akita_ioexp);
return;
}
void akita_reset_ioexp(struct device *dev, unsigned char bit)
{
ioexp_output_value &= ~bit;
if (akita_ioexp_device)
schedule_work(&akita_ioexp);
return;
}
EXPORT_SYMBOL(akita_set_ioexp);
EXPORT_SYMBOL(akita_reset_ioexp);
static void akita_ioexp_work(struct work_struct *private_)
{
if (akita_ioexp_device)
max7310_set_ouputs(akita_ioexp_device, ioexp_output_value);
}
#ifdef CONFIG_PM
static int akita_ioexp_suspend(struct platform_device *pdev, pm_message_t state)
{
flush_scheduled_work();
return 0;
}
static int akita_ioexp_resume(struct platform_device *pdev)
{
schedule_work(&akita_ioexp);
return 0;
}
#else
#define akita_ioexp_suspend NULL
#define akita_ioexp_resume NULL
#endif
static int __init akita_ioexp_probe(struct platform_device *pdev)
{
return i2c_add_driver(&max7310_i2c_driver);
}
static int akita_ioexp_remove(struct platform_device *pdev)
{
i2c_del_driver(&max7310_i2c_driver);
return 0;
}
static struct platform_driver akita_ioexp_driver = {
.probe = akita_ioexp_probe,
.remove = akita_ioexp_remove,
.suspend = akita_ioexp_suspend,
.resume = akita_ioexp_resume,
.driver = {
.name = "akita-ioexp",
},
};
static int __init akita_ioexp_init(void)
{
return platform_driver_register(&akita_ioexp_driver);
}
static void __exit akita_ioexp_exit(void)
{
platform_driver_unregister(&akita_ioexp_driver);
}
MODULE_AUTHOR("Richard Purdie <rpurdie@openedhand.com>");
MODULE_DESCRIPTION("Akita IO-Expander driver");
MODULE_LICENSE("GPL");
fs_initcall(akita_ioexp_init);
module_exit(akita_ioexp_exit);

374
arch/arm/mach-pxa/am200epd.c Normal file
View file

@ -0,0 +1,374 @@
/*
* am200epd.c -- Platform device for AM200 EPD kit
*
* Copyright (C) 2008, Jaya Kumar
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*
* Layout is based on skeletonfb.c by James Simmons and Geert Uytterhoeven.
*
* This work was made possible by help and equipment support from E-Ink
* Corporation. http://support.eink.com/community
*
* This driver is written to be used with the Metronome display controller.
* on the AM200 EPD prototype kit/development kit with an E-Ink 800x600
* Vizplex EPD on a Gumstix board using the Lyre interface board.
*
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/irq.h>
#include <linux/gpio.h>
#include <mach/pxafb.h>
#include <video/metronomefb.h>
static unsigned int panel_type = 6;
static struct platform_device *am200_device;
static struct metronome_board am200_board;
static struct pxafb_mode_info am200_fb_mode_9inch7 = {
.pixclock = 40000,
.xres = 1200,
.yres = 842,
.bpp = 16,
.hsync_len = 2,
.left_margin = 2,
.right_margin = 2,
.vsync_len = 1,
.upper_margin = 2,
.lower_margin = 25,
.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
};
static struct pxafb_mode_info am200_fb_mode_8inch = {
.pixclock = 40000,
.xres = 1088,
.yres = 791,
.bpp = 16,
.hsync_len = 28,
.left_margin = 8,
.right_margin = 30,
.vsync_len = 8,
.upper_margin = 10,
.lower_margin = 8,
.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
};
static struct pxafb_mode_info am200_fb_mode_6inch = {
.pixclock = 40189,
.xres = 832,
.yres = 622,
.bpp = 16,
.hsync_len = 28,
.left_margin = 34,
.right_margin = 34,
.vsync_len = 25,
.upper_margin = 0,
.lower_margin = 2,
.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
};
static struct pxafb_mach_info am200_fb_info = {
.modes = &am200_fb_mode_6inch,
.num_modes = 1,
.lcd_conn = LCD_TYPE_COLOR_TFT | LCD_PCLK_EDGE_FALL |
LCD_AC_BIAS_FREQ(24),
};
/* register offsets for gpio control */
#define LED_GPIO_PIN 51
#define STDBY_GPIO_PIN 48
#define RST_GPIO_PIN 49
#define RDY_GPIO_PIN 32
#define ERR_GPIO_PIN 17
#define PCBPWR_GPIO_PIN 16
static int gpios[] = { LED_GPIO_PIN , STDBY_GPIO_PIN , RST_GPIO_PIN,
RDY_GPIO_PIN, ERR_GPIO_PIN, PCBPWR_GPIO_PIN };
static char *gpio_names[] = { "LED" , "STDBY" , "RST", "RDY", "ERR", "PCBPWR" };
static int am200_init_gpio_regs(struct metronomefb_par *par)
{
int i;
int err;
for (i = 0; i < ARRAY_SIZE(gpios); i++) {
err = gpio_request(gpios[i], gpio_names[i]);
if (err) {
dev_err(&am200_device->dev, "failed requesting "
"gpio %s, err=%d\n", gpio_names[i], err);
goto err_req_gpio;
}
}
gpio_direction_output(LED_GPIO_PIN, 0);
gpio_direction_output(STDBY_GPIO_PIN, 0);
gpio_direction_output(RST_GPIO_PIN, 0);
gpio_direction_input(RDY_GPIO_PIN);
gpio_direction_input(ERR_GPIO_PIN);
gpio_direction_output(PCBPWR_GPIO_PIN, 0);
return 0;
err_req_gpio:
while (i > 0)
gpio_free(gpios[i--]);
return err;
}
static void am200_cleanup(struct metronomefb_par *par)
{
int i;
free_irq(IRQ_GPIO(RDY_GPIO_PIN), par);
for (i = 0; i < ARRAY_SIZE(gpios); i++)
gpio_free(gpios[i]);
}
static int am200_share_video_mem(struct fb_info *info)
{
/* rough check if this is our desired fb and not something else */
if ((info->var.xres != am200_fb_info.modes->xres)
|| (info->var.yres != am200_fb_info.modes->yres))
return 0;
/* we've now been notified that we have our new fb */
am200_board.metromem = info->screen_base;
am200_board.host_fbinfo = info;
/* try to refcount host drv since we are the consumer after this */
if (!try_module_get(info->fbops->owner))
return -ENODEV;
return 0;
}
static int am200_unshare_video_mem(struct fb_info *info)
{
dev_dbg(&am200_device->dev, "ENTER %s\n", __func__);
if (info != am200_board.host_fbinfo)
return 0;
module_put(am200_board.host_fbinfo->fbops->owner);
return 0;
}
static int am200_fb_notifier_callback(struct notifier_block *self,
unsigned long event, void *data)
{
struct fb_event *evdata = data;
struct fb_info *info = evdata->info;
dev_dbg(&am200_device->dev, "ENTER %s\n", __func__);
if (event == FB_EVENT_FB_REGISTERED)
return am200_share_video_mem(info);
else if (event == FB_EVENT_FB_UNREGISTERED)
return am200_unshare_video_mem(info);
return 0;
}
static struct notifier_block am200_fb_notif = {
.notifier_call = am200_fb_notifier_callback,
};
/* this gets called as part of our init. these steps must be done now so
* that we can use set_pxa_fb_info */
static void __init am200_presetup_fb(void)
{
int fw;
int fh;
int padding_size;
int totalsize;
switch (panel_type) {
case 6:
am200_fb_info.modes = &am200_fb_mode_6inch;
break;
case 8:
am200_fb_info.modes = &am200_fb_mode_8inch;
break;
case 97:
am200_fb_info.modes = &am200_fb_mode_9inch7;
break;
default:
dev_err(&am200_device->dev, "invalid panel_type selection,"
" setting to 6\n");
am200_fb_info.modes = &am200_fb_mode_6inch;
break;
}
/* the frame buffer is divided as follows:
command | CRC | padding
16kb waveform data | CRC | padding
image data | CRC
*/
fw = am200_fb_info.modes->xres;
fh = am200_fb_info.modes->yres;
/* waveform must be 16k + 2 for checksum */
am200_board.wfm_size = roundup(16*1024 + 2, fw);
padding_size = PAGE_SIZE + (4 * fw);
/* total is 1 cmd , 1 wfm, padding and image */
totalsize = fw + am200_board.wfm_size + padding_size + (fw*fh);
/* save this off because we're manipulating fw after this and
* we'll need it when we're ready to setup the framebuffer */
am200_board.fw = fw;
am200_board.fh = fh;
/* the reason we do this adjustment is because we want to acquire
* more framebuffer memory without imposing custom awareness on the
* underlying pxafb driver */
am200_fb_info.modes->yres = DIV_ROUND_UP(totalsize, fw);
/* we divide since we told the LCD controller we're 16bpp */
am200_fb_info.modes->xres /= 2;
set_pxa_fb_info(&am200_fb_info);
}
/* this gets called by metronomefb as part of its init, in our case, we
* have already completed initial framebuffer init in presetup_fb so we
* can just setup the fb access pointers */
static int am200_setup_fb(struct metronomefb_par *par)
{
int fw;
int fh;
fw = am200_board.fw;
fh = am200_board.fh;
/* metromem was set up by the notifier in share_video_mem so now
* we can use its value to calculate the other entries */
par->metromem_cmd = (struct metromem_cmd *) am200_board.metromem;
par->metromem_wfm = am200_board.metromem + fw;
par->metromem_img = par->metromem_wfm + am200_board.wfm_size;
par->metromem_img_csum = (u16 *) (par->metromem_img + (fw * fh));
par->metromem_dma = am200_board.host_fbinfo->fix.smem_start;
return 0;
}
static int am200_get_panel_type(void)
{
return panel_type;
}
static irqreturn_t am200_handle_irq(int irq, void *dev_id)
{
struct metronomefb_par *par = dev_id;
wake_up_interruptible(&par->waitq);
return IRQ_HANDLED;
}
static int am200_setup_irq(struct fb_info *info)
{
int ret;
ret = request_irq(IRQ_GPIO(RDY_GPIO_PIN), am200_handle_irq,
IRQF_DISABLED|IRQF_TRIGGER_FALLING,
"AM200", info->par);
if (ret)
dev_err(&am200_device->dev, "request_irq failed: %d\n", ret);
return ret;
}
static void am200_set_rst(struct metronomefb_par *par, int state)
{
gpio_set_value(RST_GPIO_PIN, state);
}
static void am200_set_stdby(struct metronomefb_par *par, int state)
{
gpio_set_value(STDBY_GPIO_PIN, state);
}
static int am200_wait_event(struct metronomefb_par *par)
{
return wait_event_timeout(par->waitq, gpio_get_value(RDY_GPIO_PIN), HZ);
}
static int am200_wait_event_intr(struct metronomefb_par *par)
{
return wait_event_interruptible_timeout(par->waitq,
gpio_get_value(RDY_GPIO_PIN), HZ);
}
static struct metronome_board am200_board = {
.owner = THIS_MODULE,
.setup_irq = am200_setup_irq,
.setup_io = am200_init_gpio_regs,
.setup_fb = am200_setup_fb,
.set_rst = am200_set_rst,
.set_stdby = am200_set_stdby,
.met_wait_event = am200_wait_event,
.met_wait_event_intr = am200_wait_event_intr,
.get_panel_type = am200_get_panel_type,
.cleanup = am200_cleanup,
};
static int __init am200_init(void)
{
int ret;
/* before anything else, we request notification for any fb
* creation events */
fb_register_client(&am200_fb_notif);
/* request our platform independent driver */
request_module("metronomefb");
am200_device = platform_device_alloc("metronomefb", -1);
if (!am200_device)
return -ENOMEM;
/* the am200_board that will be seen by metronomefb is a copy */
platform_device_add_data(am200_device, &am200_board,
sizeof(am200_board));
/* this _add binds metronomefb to am200. metronomefb refcounts am200 */
ret = platform_device_add(am200_device);
if (ret) {
platform_device_put(am200_device);
fb_unregister_client(&am200_fb_notif);
return ret;
}
am200_presetup_fb();
return 0;
}
module_param(panel_type, uint, 0);
MODULE_PARM_DESC(panel_type, "Select the panel type: 6, 8, 97");
module_init(am200_init);
MODULE_DESCRIPTION("board driver for am200 metronome epd kit");
MODULE_AUTHOR("Jaya Kumar");
MODULE_LICENSE("GPL");

258
arch/arm/mach-pxa/cm-x255.c Normal file
View file

@ -0,0 +1,258 @@
/*
* linux/arch/arm/mach-pxa/cm-x255.c
*
* Copyright (C) 2007, 2008 CompuLab, Ltd.
* Mike Rapoport <mike@compulab.co.il>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/platform_device.h>
#include <linux/irq.h>
#include <linux/gpio.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/physmap.h>
#include <linux/mtd/nand-gpio.h>
#include <linux/spi/spi.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
#include <asm/mach/map.h>
#include <mach/pxa2xx-regs.h>
#include <mach/mfp-pxa25x.h>
#include <mach/pxa2xx_spi.h>
#include <mach/bitfield.h>
#include "generic.h"
#define GPIO_NAND_CS (5)
#define GPIO_NAND_ALE (4)
#define GPIO_NAND_CLE (3)
#define GPIO_NAND_RB (10)
static unsigned long cmx255_pin_config[] = {
/* AC'97 */
GPIO28_AC97_BITCLK,
GPIO29_AC97_SDATA_IN_0,
GPIO30_AC97_SDATA_OUT,
GPIO31_AC97_SYNC,
/* BTUART */
GPIO42_BTUART_RXD,
GPIO43_BTUART_TXD,
GPIO44_BTUART_CTS,
GPIO45_BTUART_RTS,
/* STUART */
GPIO46_STUART_RXD,
GPIO47_STUART_TXD,
/* LCD */
GPIO58_LCD_LDD_0,
GPIO59_LCD_LDD_1,
GPIO60_LCD_LDD_2,
GPIO61_LCD_LDD_3,
GPIO62_LCD_LDD_4,
GPIO63_LCD_LDD_5,
GPIO64_LCD_LDD_6,
GPIO65_LCD_LDD_7,
GPIO66_LCD_LDD_8,
GPIO67_LCD_LDD_9,
GPIO68_LCD_LDD_10,
GPIO69_LCD_LDD_11,
GPIO70_LCD_LDD_12,
GPIO71_LCD_LDD_13,
GPIO72_LCD_LDD_14,
GPIO73_LCD_LDD_15,
GPIO74_LCD_FCLK,
GPIO75_LCD_LCLK,
GPIO76_LCD_PCLK,
GPIO77_LCD_BIAS,
/* SSP1 */
GPIO23_SSP1_SCLK,
GPIO24_SSP1_SFRM,
GPIO25_SSP1_TXD,
GPIO26_SSP1_RXD,
/* SSP2 */
GPIO81_SSP2_CLK_OUT,
GPIO82_SSP2_FRM_OUT,
GPIO83_SSP2_TXD,
GPIO84_SSP2_RXD,
/* PC Card */
GPIO48_nPOE,
GPIO49_nPWE,
GPIO50_nPIOR,
GPIO51_nPIOW,
GPIO52_nPCE_1,
GPIO53_nPCE_2,
GPIO54_nPSKTSEL,
GPIO55_nPREG,
GPIO56_nPWAIT,
GPIO57_nIOIS16,
/* SDRAM and local bus */
GPIO15_nCS_1,
GPIO78_nCS_2,
GPIO79_nCS_3,
GPIO80_nCS_4,
GPIO33_nCS_5,
GPIO18_RDY,
/* GPIO */
GPIO0_GPIO | WAKEUP_ON_EDGE_BOTH,
GPIO9_GPIO, /* PC card reset */
/* NAND controls */
GPIO5_GPIO | MFP_LPM_DRIVE_HIGH, /* NAND CE# */
GPIO4_GPIO | MFP_LPM_DRIVE_LOW, /* NAND ALE */
GPIO3_GPIO | MFP_LPM_DRIVE_LOW, /* NAND CLE */
GPIO10_GPIO, /* NAND Ready/Busy */
/* interrupts */
GPIO22_GPIO, /* DM9000 interrupt */
};
#if defined(CONFIG_SPI_PXA2XX)
static struct pxa2xx_spi_master pxa_ssp_master_info = {
.num_chipselect = 1,
};
static struct spi_board_info spi_board_info[] __initdata = {
[0] = {
.modalias = "rtc-max6902",
.max_speed_hz = 1000000,
.bus_num = 1,
.chip_select = 0,
},
};
static void __init cmx255_init_rtc(void)
{
pxa2xx_set_spi_info(1, &pxa_ssp_master_info);
spi_register_board_info(ARRAY_AND_SIZE(spi_board_info));
}
#else
static inline void cmx255_init_rtc(void) {}
#endif
#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
static struct mtd_partition cmx255_nor_partitions[] = {
{
.name = "ARMmon",
.size = 0x00030000,
.offset = 0,
.mask_flags = MTD_WRITEABLE /* force read-only */
} , {
.name = "ARMmon setup block",
.size = 0x00010000,
.offset = MTDPART_OFS_APPEND,
.mask_flags = MTD_WRITEABLE /* force read-only */
} , {
.name = "kernel",
.size = 0x00160000,
.offset = MTDPART_OFS_APPEND,
} , {
.name = "ramdisk",
.size = MTDPART_SIZ_FULL,
.offset = MTDPART_OFS_APPEND
}
};
static struct physmap_flash_data cmx255_nor_flash_data[] = {
{
.width = 2, /* bankwidth in bytes */
.parts = cmx255_nor_partitions,
.nr_parts = ARRAY_SIZE(cmx255_nor_partitions)
}
};
static struct resource cmx255_nor_resource = {
.start = PXA_CS0_PHYS,
.end = PXA_CS0_PHYS + SZ_8M - 1,
.flags = IORESOURCE_MEM,
};
static struct platform_device cmx255_nor = {
.name = "physmap-flash",
.id = -1,
.dev = {
.platform_data = cmx255_nor_flash_data,
},
.resource = &cmx255_nor_resource,
.num_resources = 1,
};
static void __init cmx255_init_nor(void)
{
platform_device_register(&cmx255_nor);
}
#else
static inline void cmx255_init_nor(void) {}
#endif
#if defined(CONFIG_MTD_NAND_GPIO) || defined(CONFIG_MTD_NAND_GPIO_MODULE)
static struct resource cmx255_nand_resource[] = {
[0] = {
.start = PXA_CS1_PHYS,
.end = PXA_CS1_PHYS + 11,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = PXA_CS5_PHYS,
.end = PXA_CS5_PHYS + 3,
.flags = IORESOURCE_MEM,
},
};
static struct mtd_partition cmx255_nand_parts[] = {
[0] = {
.name = "cmx255-nand",
.size = MTDPART_SIZ_FULL,
.offset = 0,
},
};
static struct gpio_nand_platdata cmx255_nand_platdata = {
.gpio_nce = GPIO_NAND_CS,
.gpio_cle = GPIO_NAND_CLE,
.gpio_ale = GPIO_NAND_ALE,
.gpio_rdy = GPIO_NAND_RB,
.gpio_nwp = -1,
.parts = cmx255_nand_parts,
.num_parts = ARRAY_SIZE(cmx255_nand_parts),
.chip_delay = 25,
};
static struct platform_device cmx255_nand = {
.name = "gpio-nand",
.num_resources = ARRAY_SIZE(cmx255_nand_resource),
.resource = cmx255_nand_resource,
.id = -1,
.dev = {
.platform_data = &cmx255_nand_platdata,
}
};
static void __init cmx255_init_nand(void)
{
platform_device_register(&cmx255_nand);
}
#else
static inline void cmx255_init_nand(void) {}
#endif
void __init cmx255_init(void)
{
pxa2xx_mfp_config(ARRAY_AND_SIZE(cmx255_pin_config));
cmx255_init_rtc();
cmx255_init_nor();
cmx255_init_nand();
}

13
arch/arm/mach-pxa/cm-x270-pci.h
View file

@ -1,13 +0,0 @@
extern void __cmx270_pci_init_irq(int irq_gpio);
extern void __cmx270_pci_suspend(void);
extern void __cmx270_pci_resume(void);
#ifdef CONFIG_PCI
#define cmx270_pci_init_irq(x) __cmx270_pci_init_irq(x)
#define cmx270_pci_suspend(x) __cmx270_pci_suspend(x)
#define cmx270_pci_resume(x) __cmx270_pci_resume(x)
#else
#define cmx270_pci_init_irq(x) do {} while (0)
#define cmx270_pci_suspend(x) do {} while (0)
#define cmx270_pci_resume(x) do {} while (0)
#endif

472
arch/arm/mach-pxa/cm-x270.c
View file

@ -14,46 +14,22 @@
#include <linux/irq.h>
#include <linux/gpio.h>
#include <linux/dm9000.h>
#include <linux/rtc-v3020.h>
#include <video/mbxfb.h>
#include <linux/leds.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
#include <asm/mach/map.h>
#include <mach/pxa2xx-regs.h>
#include <mach/mfp-pxa27x.h>
#include <mach/pxa-regs.h>
#include <mach/audio.h>
#include <mach/pxafb.h>
#include <mach/ohci.h>
#include <mach/mmc.h>
#include <mach/bitfield.h>
#include <asm/hardware/it8152.h>
#include "generic.h"
#include "cm-x270-pci.h"
/* virtual addresses for statically mapped regions */
#define CMX270_VIRT_BASE (0xe8000000)
#define CMX270_IT8152_VIRT (CMX270_VIRT_BASE)
/* physical address if local-bus attached devices */
#define RTC_PHYS_BASE (PXA_CS1_PHYS + (5 << 22))
#define DM9000_PHYS_BASE (PXA_CS1_PHYS + (6 << 22))
/* GPIO IRQ usage */
#define GPIO10_ETHIRQ (10)
#define GPIO22_IT8152_IRQ (22)
#define GPIO83_MMC_IRQ (83)
#define GPIO95_GFXIRQ (95)
#define CMX270_ETHIRQ IRQ_GPIO(GPIO10_ETHIRQ)
#define CMX270_IT8152_IRQ IRQ_GPIO(GPIO22_IT8152_IRQ)
#define CMX270_MMC_IRQ IRQ_GPIO(GPIO83_MMC_IRQ)
#define CMX270_GFXIRQ IRQ_GPIO(GPIO95_GFXIRQ)
/* MMC power enable */
#define GPIO105_MMC_POWER (105)
@ -157,62 +133,6 @@ static unsigned long cmx270_pin_config[] = {
GPIO83_GPIO, /* MMC card detect */
};
#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
static struct resource cmx270_dm9000_resource[] = {
[0] = {
.start = DM9000_PHYS_BASE,
.end = DM9000_PHYS_BASE + 4,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = DM9000_PHYS_BASE + 8,
.end = DM9000_PHYS_BASE + 8 + 500,
.flags = IORESOURCE_MEM,
},
[2] = {
.start = CMX270_ETHIRQ,
.end = CMX270_ETHIRQ,
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
}
};
static struct dm9000_plat_data cmx270_dm9000_platdata = {
.flags = DM9000_PLATF_32BITONLY,
};
static struct platform_device cmx270_dm9000_device = {
.name = "dm9000",
.id = 0,
.num_resources = ARRAY_SIZE(cmx270_dm9000_resource),
.resource = cmx270_dm9000_resource,
.dev = {
.platform_data = &cmx270_dm9000_platdata,
}
};
static void __init cmx270_init_dm9000(void)
{
platform_device_register(&cmx270_dm9000_device);
}
#else
static inline void cmx270_init_dm9000(void) {}
#endif
/* UCB1400 touchscreen controller */
#if defined(CONFIG_TOUCHSCREEN_UCB1400) || defined(CONFIG_TOUCHSCREEN_UCB1400_MODULE)
static struct platform_device cmx270_ts_device = {
.name = "ucb1400_ts",
.id = -1,
};
static void __init cmx270_init_touchscreen(void)
{
platform_device_register(&cmx270_ts_device);
}
#else
static inline void cmx270_init_touchscreen(void) {}
#endif
/* V3020 RTC */
#if defined(CONFIG_RTC_DRV_V3020) || defined(CONFIG_RTC_DRV_V3020_MODULE)
static struct resource cmx270_v3020_resource[] = {
@ -242,45 +162,7 @@ static void __init cmx270_init_rtc(void)
platform_device_register(&cmx270_rtc_device);
}
#else
static inline void cmx270_init_rtc(void) {}
#endif
/* CM-X270 LEDs */
#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
static struct gpio_led cmx270_leds[] = {
[0] = {
.name = "cm-x270:red",
.default_trigger = "nand-disk",
.gpio = 93,
.active_low = 1,
},
[1] = {
.name = "cm-x270:green",
.default_trigger = "heartbeat",
.gpio = 94,
.active_low = 1,
},
};
static struct gpio_led_platform_data cmx270_gpio_led_pdata = {
.num_leds = ARRAY_SIZE(cmx270_leds),
.leds = cmx270_leds,
};
static struct platform_device cmx270_led_device = {
.name = "leds-gpio",
.id = -1,
.dev = {
.platform_data = &cmx270_gpio_led_pdata,
},
};
static void __init cmx270_init_leds(void)
{
platform_device_register(&cmx270_led_device);
}
#else
static inline void cmx270_init_leds(void) {}
static inline void cmx2xx_init_rtc(void) {}
#endif
/* 2700G graphics */
@ -373,238 +255,11 @@ static void __init cmx270_init_2700G(void)
static inline void cmx270_init_2700G(void) {}
#endif
#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
/*
Display definitions
keep these for backwards compatibility, although symbolic names (as
e.g. in lpd270.c) looks better
*/
#define MTYPE_STN320x240 0
#define MTYPE_TFT640x480 1
#define MTYPE_CRT640x480 2
#define MTYPE_CRT800x600 3
#define MTYPE_TFT320x240 6
#define MTYPE_STN640x480 7
static struct pxafb_mode_info generic_stn_320x240_mode = {
.pixclock = 76923,
.bpp = 8,
.xres = 320,
.yres = 240,
.hsync_len = 3,
.vsync_len = 2,
.left_margin = 3,
.upper_margin = 0,
.right_margin = 3,
.lower_margin = 0,
.sync = (FB_SYNC_HOR_HIGH_ACT |
FB_SYNC_VERT_HIGH_ACT),
.cmap_greyscale = 0,
};
static struct pxafb_mach_info generic_stn_320x240 = {
.modes = &generic_stn_320x240_mode,
.num_modes = 1,
.lccr0 = 0,
.lccr3 = (LCCR3_PixClkDiv(0x03) |
LCCR3_Acb(0xff) |
LCCR3_PCP),
.cmap_inverse = 0,
.cmap_static = 0,
};
static struct pxafb_mode_info generic_tft_640x480_mode = {
.pixclock = 38461,
.bpp = 8,
.xres = 640,
.yres = 480,
.hsync_len = 60,
.vsync_len = 2,
.left_margin = 70,
.upper_margin = 10,
.right_margin = 70,
.lower_margin = 5,
.sync = 0,
.cmap_greyscale = 0,
};
static struct pxafb_mach_info generic_tft_640x480 = {
.modes = &generic_tft_640x480_mode,
.num_modes = 1,
.lccr0 = (LCCR0_PAS),
.lccr3 = (LCCR3_PixClkDiv(0x01) |
LCCR3_Acb(0xff) |
LCCR3_PCP),
.cmap_inverse = 0,
.cmap_static = 0,
};
static struct pxafb_mode_info generic_crt_640x480_mode = {
.pixclock = 38461,
.bpp = 8,
.xres = 640,
.yres = 480,
.hsync_len = 63,
.vsync_len = 2,
.left_margin = 81,
.upper_margin = 33,
.right_margin = 16,
.lower_margin = 10,
.sync = (FB_SYNC_HOR_HIGH_ACT |
FB_SYNC_VERT_HIGH_ACT),
.cmap_greyscale = 0,
};
static struct pxafb_mach_info generic_crt_640x480 = {
.modes = &generic_crt_640x480_mode,
.num_modes = 1,
.lccr0 = (LCCR0_PAS),
.lccr3 = (LCCR3_PixClkDiv(0x01) |
LCCR3_Acb(0xff)),
.cmap_inverse = 0,
.cmap_static = 0,
};
static struct pxafb_mode_info generic_crt_800x600_mode = {
.pixclock = 28846,
.bpp = 8,
.xres = 800,
.yres = 600,
.hsync_len = 63,
.vsync_len = 2,
.left_margin = 26,
.upper_margin = 21,
.right_margin = 26,
.lower_margin = 11,
.sync = (FB_SYNC_HOR_HIGH_ACT |
FB_SYNC_VERT_HIGH_ACT),
.cmap_greyscale = 0,
};
static struct pxafb_mach_info generic_crt_800x600 = {
.modes = &generic_crt_800x600_mode,
.num_modes = 1,
.lccr0 = (LCCR0_PAS),
.lccr3 = (LCCR3_PixClkDiv(0x02) |
LCCR3_Acb(0xff)),
.cmap_inverse = 0,
.cmap_static = 0,
};
static struct pxafb_mode_info generic_tft_320x240_mode = {
.pixclock = 134615,
.bpp = 16,
.xres = 320,
.yres = 240,
.hsync_len = 63,
.vsync_len = 7,
.left_margin = 75,
.upper_margin = 0,
.right_margin = 15,
.lower_margin = 15,
.sync = 0,
.cmap_greyscale = 0,
};
static struct pxafb_mach_info generic_tft_320x240 = {
.modes = &generic_tft_320x240_mode,
.num_modes = 1,
.lccr0 = (LCCR0_PAS),
.lccr3 = (LCCR3_PixClkDiv(0x06) |
LCCR3_Acb(0xff) |
LCCR3_PCP),
.cmap_inverse = 0,
.cmap_static = 0,
};
static struct pxafb_mode_info generic_stn_640x480_mode = {
.pixclock = 57692,
.bpp = 8,
.xres = 640,
.yres = 480,
.hsync_len = 4,
.vsync_len = 2,
.left_margin = 10,
.upper_margin = 5,
.right_margin = 10,
.lower_margin = 5,
.sync = (FB_SYNC_HOR_HIGH_ACT |
FB_SYNC_VERT_HIGH_ACT),
.cmap_greyscale = 0,
};
static struct pxafb_mach_info generic_stn_640x480 = {
.modes = &generic_stn_640x480_mode,
.num_modes = 1,
.lccr0 = 0,
.lccr3 = (LCCR3_PixClkDiv(0x02) |
LCCR3_Acb(0xff)),
.cmap_inverse = 0,
.cmap_static = 0,
};
static struct pxafb_mach_info *cmx270_display = &generic_crt_640x480;
static int __init cmx270_set_display(char *str)
{
int disp_type = simple_strtol(str, NULL, 0);
switch (disp_type) {
case MTYPE_STN320x240:
cmx270_display = &generic_stn_320x240;
break;
case MTYPE_TFT640x480:
cmx270_display = &generic_tft_640x480;
break;
case MTYPE_CRT640x480:
cmx270_display = &generic_crt_640x480;
break;
case MTYPE_CRT800x600:
cmx270_display = &generic_crt_800x600;
break;
case MTYPE_TFT320x240:
cmx270_display = &generic_tft_320x240;
break;
case MTYPE_STN640x480:
cmx270_display = &generic_stn_640x480;
break;
default: /* fallback to CRT 640x480 */
cmx270_display = &generic_crt_640x480;
break;
}
return 1;
}
/*
This should be done really early to get proper configuration for
frame buffer.
Indeed, pxafb parameters can be used istead, but CM-X270 bootloader
has limitied line length for kernel command line, and also it will
break compatibitlty with proprietary releases already in field.
*/
__setup("monitor=", cmx270_set_display);
static void __init cmx270_init_display(void)
{
set_pxa_fb_info(cmx270_display);
}
#else
static inline void cmx270_init_display(void) {}
#endif
/* PXA27x OHCI controller setup */
#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
static int cmx270_ohci_init(struct device *dev)
{
/* Set the Power Control Polarity Low */
UHCHR = (UHCHR | UHCHR_PCPL) &
~(UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE);
return 0;
}
static struct pxaohci_platform_data cmx270_ohci_platform_data = {
.port_mode = PMM_PERPORT_MODE,
.init = cmx270_ohci_init,
.flags = ENABLE_PORT1 | ENABLE_PORT2 | POWER_CONTROL_LOW,
};
static void __init cmx270_init_ohci(void)
@ -676,131 +331,12 @@ static void __init cmx270_init_mmc(void)
static inline void cmx270_init_mmc(void) {}
#endif
#ifdef CONFIG_PM
static unsigned long sleep_save_msc[10];
static int cmx270_suspend(struct sys_device *dev, pm_message_t state)
void __init cmx270_init(void)
{
cmx270_pci_suspend();
/* save MSC registers */
sleep_save_msc[0] = MSC0;
sleep_save_msc[1] = MSC1;
sleep_save_msc[2] = MSC2;
/* setup power saving mode registers */
PCFR = 0x0;
PSLR = 0xff400000;
PMCR = 0x00000005;
PWER = 0x80000000;
PFER = 0x00000000;
PRER = 0x00000000;
PGSR0 = 0xC0018800;
PGSR1 = 0x004F0002;
PGSR2 = 0x6021C000;
PGSR3 = 0x00020000;
return 0;
}
static int cmx270_resume(struct sys_device *dev)
{
cmx270_pci_resume();
/* restore MSC registers */
MSC0 = sleep_save_msc[0];
MSC1 = sleep_save_msc[1];
MSC2 = sleep_save_msc[2];
return 0;
}
static struct sysdev_class cmx270_pm_sysclass = {
.name = "pm",
.resume = cmx270_resume,
.suspend = cmx270_suspend,
};
static struct sys_device cmx270_pm_device = {
.cls = &cmx270_pm_sysclass,
};
static int __init cmx270_pm_init(void)
{
int error;
error = sysdev_class_register(&cmx270_pm_sysclass);
if (error == 0)
error = sysdev_register(&cmx270_pm_device);
return error;
}
#else
static int __init cmx270_pm_init(void) { return 0; }
#endif
#if defined(CONFIG_SND_PXA2XX_AC97) || defined(CONFIG_SND_PXA2XX_AC97_MODULE)
static void __init cmx270_init_ac97(void)
{
pxa_set_ac97_info(NULL);
}
#else
static inline void cmx270_init_ac97(void) {}
#endif
static void __init cmx270_init(void)
{
cmx270_pm_init();
pxa2xx_mfp_config(ARRAY_AND_SIZE(cmx270_pin_config));
cmx270_init_dm9000();
cmx270_init_rtc();
cmx270_init_display();
cmx270_init_mmc();
cmx270_init_ohci();
cmx270_init_ac97();
cmx270_init_touchscreen();
cmx270_init_leds();
cmx270_init_2700G();
}
static void __init cmx270_init_irq(void)
{
pxa27x_init_irq();
cmx270_pci_init_irq(GPIO22_IT8152_IRQ);
}
#ifdef CONFIG_PCI
/* Map PCI companion statically */
static struct map_desc cmx270_io_desc[] __initdata = {
[0] = { /* PCI bridge */
.virtual = CMX270_IT8152_VIRT,
.pfn = __phys_to_pfn(PXA_CS4_PHYS),
.length = SZ_64M,
.type = MT_DEVICE
},
};
static void __init cmx270_map_io(void)
{
pxa_map_io();
iotable_init(cmx270_io_desc, ARRAY_SIZE(cmx270_io_desc));
it8152_base_address = CMX270_IT8152_VIRT;
}
#else
static void __init cmx270_map_io(void)
{
pxa_map_io();
}
#endif
MACHINE_START(ARMCORE, "Compulab CM-x270")
.boot_params = 0xa0000100,
.phys_io = 0x40000000,
.io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
.map_io = cmx270_map_io,
.init_irq = cmx270_init_irq,
.timer = &pxa_timer,
.init_machine = cmx270_init,
MACHINE_END

56
arch/arm/mach-pxa/cm-x270-pci.c → arch/arm/mach-pxa/cm-x2xx-pci.c
View file

@ -1,5 +1,5 @@
/*
* linux/arch/arm/mach-pxa/cm-x270-pci.c
* linux/arch/arm/mach-pxa/cm-x2xx-pci.c
*
* PCI bios-type initialisation for PCI machines
*
@ -28,7 +28,7 @@
#include <asm/hardware/it8152.h>
unsigned long it8152_base_address;
static int cmx270_it8152_irq_gpio;
static int cmx2xx_it8152_irq_gpio;
/*
* Only first 64MB of memory can be accessed via PCI.
@ -36,13 +36,13 @@ static int cmx270_it8152_irq_gpio;
* This is really ugly and we need a better way of specifying
* DMA-capable regions of memory.
*/
void __init cmx270_pci_adjust_zones(int node, unsigned long *zone_size,
void __init cmx2xx_pci_adjust_zones(int node, unsigned long *zone_size,
unsigned long *zhole_size)
{
unsigned int sz = SZ_64M >> PAGE_SHIFT;
if (machine_is_armcore()) {
pr_info("Adjusting zones for CM-X270\n");
pr_info("Adjusting zones for CM-X2XX\n");
/*
* Only adjust if > 64M on current system
@ -57,29 +57,29 @@ void __init cmx270_pci_adjust_zones(int node, unsigned long *zone_size,
}
}
static void cmx270_it8152_irq_demux(unsigned int irq, struct irq_desc *desc)
static void cmx2xx_it8152_irq_demux(unsigned int irq, struct irq_desc *desc)
{
/* clear our parent irq */
GEDR(cmx270_it8152_irq_gpio) = GPIO_bit(cmx270_it8152_irq_gpio);
GEDR(cmx2xx_it8152_irq_gpio) = GPIO_bit(cmx2xx_it8152_irq_gpio);
it8152_irq_demux(irq, desc);
}
void __cmx270_pci_init_irq(int irq_gpio)
void __cmx2xx_pci_init_irq(int irq_gpio)
{
it8152_init_irq();
cmx270_it8152_irq_gpio = irq_gpio;
cmx2xx_it8152_irq_gpio = irq_gpio;
set_irq_type(gpio_to_irq(irq_gpio), IRQ_TYPE_EDGE_RISING);
set_irq_chained_handler(gpio_to_irq(irq_gpio), cmx270_it8152_irq_demux);
set_irq_chained_handler(gpio_to_irq(irq_gpio), cmx2xx_it8152_irq_demux);
}
#ifdef CONFIG_PM
static unsigned long sleep_save_ite[10];
void __cmx270_pci_suspend(void)
void __cmx2xx_pci_suspend(void)
{
/* save ITE state */
sleep_save_ite[0] = __raw_readl(IT8152_INTC_PDCNIMR);
@ -91,7 +91,7 @@ void __cmx270_pci_suspend(void)
__raw_writel((0), IT8152_INTC_LPCNIRR);
}
void __cmx270_pci_resume(void)
void __cmx2xx_pci_resume(void)
{
/* restore IT8152 state */
__raw_writel((sleep_save_ite[0]), IT8152_INTC_PDCNIMR);
@ -99,12 +99,12 @@ void __cmx270_pci_resume(void)
__raw_writel((sleep_save_ite[2]), IT8152_INTC_LPNIAR);
}
#else
void cmx270_pci_suspend(void) {}
void cmx270_pci_resume(void) {}
void cmx2xx_pci_suspend(void) {}
void cmx2xx_pci_resume(void) {}
#endif
/* PCI IRQ mapping*/
static int __init cmx270_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
static int __init cmx2xx_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
int irq;
@ -116,14 +116,14 @@ static int __init cmx270_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
/*
Here comes the ugly part. The routing is baseboard specific,
but defining a platform for each possible base of CM-X270 is
unrealistic. Here we keep mapping for ATXBase and SB-X270.
but defining a platform for each possible base of CM-X2XX is
unrealistic. Here we keep mapping for ATXBase and SB-X2XX.
*/
/* ATXBASE PCI slot */
if (slot == 7)
return IT8152_PCI_INTA;
/* ATXBase/SB-x270 CardBus */
/* ATXBase/SB-X2XX CardBus */
if (slot == 8 || slot == 0)
return IT8152_PCI_INTB;
@ -131,7 +131,11 @@ static int __init cmx270_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
if (slot == 9)
return IT8152_PCI_INTA;
/* SB-x270 Ethernet */
/* CM-x255 Onboard Ethernet */
if (slot == 15)
return IT8152_PCI_INTC;
/* SB-x2xx Ethernet */
if (slot == 16)
return IT8152_PCI_INTA;
@ -144,9 +148,9 @@ static int __init cmx270_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
return(0);
}
static void cmx270_pci_preinit(void)
static void cmx2xx_pci_preinit(void)
{
pr_info("Initializing CM-X270 PCI subsystem\n");
pr_info("Initializing CM-X2XX PCI subsystem\n");
__raw_writel(0x800, IT8152_PCI_CFG_ADDR);
if (__raw_readl(IT8152_PCI_CFG_DATA) == 0x81521283) {
@ -200,21 +204,21 @@ static void cmx270_pci_preinit(void)
}
}
static struct hw_pci cmx270_pci __initdata = {
static struct hw_pci cmx2xx_pci __initdata = {
.swizzle = pci_std_swizzle,
.map_irq = cmx270_pci_map_irq,
.map_irq = cmx2xx_pci_map_irq,
.nr_controllers = 1,
.setup = it8152_pci_setup,
.scan = it8152_pci_scan_bus,
.preinit = cmx270_pci_preinit,
.preinit = cmx2xx_pci_preinit,
};
static int __init cmx270_init_pci(void)
static int __init cmx2xx_init_pci(void)
{
if (machine_is_armcore())
pci_common_init(&cmx270_pci);
pci_common_init(&cmx2xx_pci);
return 0;
}
subsys_initcall(cmx270_init_pci);
subsys_initcall(cmx2xx_init_pci);

13
arch/arm/mach-pxa/cm-x2xx-pci.h Normal file
View file

@ -0,0 +1,13 @@
extern void __cmx2xx_pci_init_irq(int irq_gpio);
extern void __cmx2xx_pci_suspend(void);
extern void __cmx2xx_pci_resume(void);
#ifdef CONFIG_PCI
#define cmx2xx_pci_init_irq(x) __cmx2xx_pci_init_irq(x)
#define cmx2xx_pci_suspend(x) __cmx2xx_pci_suspend(x)
#define cmx2xx_pci_resume(x) __cmx2xx_pci_resume(x)
#else
#define cmx2xx_pci_init_irq(x) do {} while (0)
#define cmx2xx_pci_suspend(x) do {} while (0)
#define cmx2xx_pci_resume(x) do {} while (0)
#endif

531
arch/arm/mach-pxa/cm-x2xx.c Normal file
View file

@ -0,0 +1,531 @@
/*
* linux/arch/arm/mach-pxa/cm-x2xx.c
*
* Copyright (C) 2008 CompuLab, Ltd.
* Mike Rapoport <mike@compulab.co.il>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/platform_device.h>
#include <linux/sysdev.h>
#include <linux/irq.h>
#include <linux/gpio.h>
#include <linux/dm9000.h>
#include <linux/leds.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
#include <asm/mach/map.h>
#include <mach/pxa2xx-regs.h>
#include <mach/mfp-pxa27x.h>
#include <mach/pxa-regs.h>
#include <mach/audio.h>
#include <mach/pxafb.h>
#include <asm/hardware/it8152.h>
#include "generic.h"
#include "cm-x2xx-pci.h"
extern void cmx255_init(void);
extern void cmx270_init(void);
/* virtual addresses for statically mapped regions */
#define CMX2XX_VIRT_BASE (0xe8000000)
#define CMX2XX_IT8152_VIRT (CMX2XX_VIRT_BASE)
/* physical address if local-bus attached devices */
#define CMX255_DM9000_PHYS_BASE (PXA_CS1_PHYS + (8 << 22))
#define CMX270_DM9000_PHYS_BASE (PXA_CS1_PHYS + (6 << 22))
/* leds */
#define CMX255_GPIO_RED (27)
#define CMX255_GPIO_GREEN (32)
#define CMX270_GPIO_RED (93)
#define CMX270_GPIO_GREEN (94)
/* GPIO IRQ usage */
#define GPIO22_ETHIRQ (22)
#define GPIO10_ETHIRQ (10)
#define CMX255_GPIO_IT8152_IRQ (0)
#define CMX270_GPIO_IT8152_IRQ (22)
#define CMX255_ETHIRQ IRQ_GPIO(GPIO22_ETHIRQ)
#define CMX270_ETHIRQ IRQ_GPIO(GPIO10_ETHIRQ)
#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
static struct resource cmx255_dm9000_resource[] = {
[0] = {
.start = CMX255_DM9000_PHYS_BASE,
.end = CMX255_DM9000_PHYS_BASE + 3,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = CMX255_DM9000_PHYS_BASE + 4,
.end = CMX255_DM9000_PHYS_BASE + 4 + 500,
.flags = IORESOURCE_MEM,
},
[2] = {
.start = CMX255_ETHIRQ,
.end = CMX255_ETHIRQ,
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
}
};
static struct resource cmx270_dm9000_resource[] = {
[0] = {
.start = CMX270_DM9000_PHYS_BASE,
.end = CMX270_DM9000_PHYS_BASE + 3,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = CMX270_DM9000_PHYS_BASE + 8,
.end = CMX270_DM9000_PHYS_BASE + 8 + 500,
.flags = IORESOURCE_MEM,
},
[2] = {
.start = CMX270_ETHIRQ,
.end = CMX270_ETHIRQ,
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
}
};
static struct dm9000_plat_data cmx270_dm9000_platdata = {
.flags = DM9000_PLATF_32BITONLY,
};
static struct platform_device cmx2xx_dm9000_device = {
.name = "dm9000",
.id = 0,
.num_resources = ARRAY_SIZE(cmx270_dm9000_resource),
.dev = {
.platform_data = &cmx270_dm9000_platdata,
}
};
static void __init cmx2xx_init_dm9000(void)
{
if (cpu_is_pxa25x())
cmx2xx_dm9000_device.resource = cmx255_dm9000_resource;
else
cmx2xx_dm9000_device.resource = cmx270_dm9000_resource;
platform_device_register(&cmx2xx_dm9000_device);
}
#else
static inline void cmx2xx_init_dm9000(void) {}
#endif
/* UCB1400 touchscreen controller */
#if defined(CONFIG_TOUCHSCREEN_UCB1400) || defined(CONFIG_TOUCHSCREEN_UCB1400_MODULE)
static struct platform_device cmx2xx_ts_device = {
.name = "ucb1400_ts",
.id = -1,
};
static void __init cmx2xx_init_touchscreen(void)
{
platform_device_register(&cmx2xx_ts_device);
}
#else
static inline void cmx2xx_init_touchscreen(void) {}
#endif
/* CM-X270 LEDs */
#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
static struct gpio_led cmx2xx_leds[] = {
[0] = {
.name = "cm-x2xx:red",
.default_trigger = "nand-disk",
.active_low = 1,
},
[1] = {
.name = "cm-x2xx:green",
.default_trigger = "heartbeat",
.active_low = 1,
},
};
static struct gpio_led_platform_data cmx2xx_gpio_led_pdata = {
.num_leds = ARRAY_SIZE(cmx2xx_leds),
.leds = cmx2xx_leds,
};
static struct platform_device cmx2xx_led_device = {
.name = "leds-gpio",
.id = -1,
.dev = {
.platform_data = &cmx2xx_gpio_led_pdata,
},
};
static void __init cmx2xx_init_leds(void)
{
if (cpu_is_pxa25x()) {
cmx2xx_leds[0].gpio = CMX255_GPIO_RED;
cmx2xx_leds[1].gpio = CMX255_GPIO_GREEN;
} else {
cmx2xx_leds[0].gpio = CMX270_GPIO_RED;
cmx2xx_leds[1].gpio = CMX270_GPIO_GREEN;
}
platform_device_register(&cmx2xx_led_device);
}
#else
static inline void cmx2xx_init_leds(void) {}
#endif
#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
/*
Display definitions
keep these for backwards compatibility, although symbolic names (as
e.g. in lpd270.c) looks better
*/
#define MTYPE_STN320x240 0
#define MTYPE_TFT640x480 1
#define MTYPE_CRT640x480 2
#define MTYPE_CRT800x600 3
#define MTYPE_TFT320x240 6
#define MTYPE_STN640x480 7
static struct pxafb_mode_info generic_stn_320x240_mode = {
.pixclock = 76923,
.bpp = 8,
.xres = 320,
.yres = 240,
.hsync_len = 3,
.vsync_len = 2,
.left_margin = 3,
.upper_margin = 0,
.right_margin = 3,
.lower_margin = 0,
.sync = (FB_SYNC_HOR_HIGH_ACT |
FB_SYNC_VERT_HIGH_ACT),
.cmap_greyscale = 0,
};
static struct pxafb_mach_info generic_stn_320x240 = {
.modes = &generic_stn_320x240_mode,
.num_modes = 1,
.lccr0 = 0,
.lccr3 = (LCCR3_PixClkDiv(0x03) |
LCCR3_Acb(0xff) |
LCCR3_PCP),
.cmap_inverse = 0,
.cmap_static = 0,
};
static struct pxafb_mode_info generic_tft_640x480_mode = {
.pixclock = 38461,
.bpp = 8,
.xres = 640,
.yres = 480,
.hsync_len = 60,
.vsync_len = 2,
.left_margin = 70,
.upper_margin = 10,
.right_margin = 70,
.lower_margin = 5,
.sync = 0,
.cmap_greyscale = 0,
};
static struct pxafb_mach_info generic_tft_640x480 = {
.modes = &generic_tft_640x480_mode,
.num_modes = 1,
.lccr0 = (LCCR0_PAS),
.lccr3 = (LCCR3_PixClkDiv(0x01) |
LCCR3_Acb(0xff) |
LCCR3_PCP),
.cmap_inverse = 0,
.cmap_static = 0,
};
static struct pxafb_mode_info generic_crt_640x480_mode = {
.pixclock = 38461,
.bpp = 8,
.xres = 640,
.yres = 480,
.hsync_len = 63,
.vsync_len = 2,
.left_margin = 81,
.upper_margin = 33,
.right_margin = 16,
.lower_margin = 10,
.sync = (FB_SYNC_HOR_HIGH_ACT |
FB_SYNC_VERT_HIGH_ACT),
.cmap_greyscale = 0,
};
static struct pxafb_mach_info generic_crt_640x480 = {
.modes = &generic_crt_640x480_mode,
.num_modes = 1,
.lccr0 = (LCCR0_PAS),
.lccr3 = (LCCR3_PixClkDiv(0x01) |
LCCR3_Acb(0xff)),
.cmap_inverse = 0,
.cmap_static = 0,
};
static struct pxafb_mode_info generic_crt_800x600_mode = {
.pixclock = 28846,
.bpp = 8,
.xres = 800,
.yres = 600,
.hsync_len = 63,
.vsync_len = 2,
.left_margin = 26,
.upper_margin = 21,
.right_margin = 26,
.lower_margin = 11,
.sync = (FB_SYNC_HOR_HIGH_ACT |
FB_SYNC_VERT_HIGH_ACT),
.cmap_greyscale = 0,
};
static struct pxafb_mach_info generic_crt_800x600 = {
.modes = &generic_crt_800x600_mode,
.num_modes = 1,
.lccr0 = (LCCR0_PAS),
.lccr3 = (LCCR3_PixClkDiv(0x02) |
LCCR3_Acb(0xff)),
.cmap_inverse = 0,
.cmap_static = 0,
};
static struct pxafb_mode_info generic_tft_320x240_mode = {
.pixclock = 134615,
.bpp = 16,
.xres = 320,
.yres = 240,
.hsync_len = 63,
.vsync_len = 7,
.left_margin = 75,
.upper_margin = 0,
.right_margin = 15,
.lower_margin = 15,
.sync = 0,
.cmap_greyscale = 0,
};
static struct pxafb_mach_info generic_tft_320x240 = {
.modes = &generic_tft_320x240_mode,
.num_modes = 1,
.lccr0 = (LCCR0_PAS),
.lccr3 = (LCCR3_PixClkDiv(0x06) |
LCCR3_Acb(0xff) |
LCCR3_PCP),
.cmap_inverse = 0,
.cmap_static = 0,
};
static struct pxafb_mode_info generic_stn_640x480_mode = {
.pixclock = 57692,
.bpp = 8,
.xres = 640,
.yres = 480,
.hsync_len = 4,
.vsync_len = 2,
.left_margin = 10,
.upper_margin = 5,
.right_margin = 10,
.lower_margin = 5,
.sync = (FB_SYNC_HOR_HIGH_ACT |
FB_SYNC_VERT_HIGH_ACT),
.cmap_greyscale = 0,
};
static struct pxafb_mach_info generic_stn_640x480 = {
.modes = &generic_stn_640x480_mode,
.num_modes = 1,
.lccr0 = 0,
.lccr3 = (LCCR3_PixClkDiv(0x02) |
LCCR3_Acb(0xff)),
.cmap_inverse = 0,
.cmap_static = 0,
};
static struct pxafb_mach_info *cmx2xx_display = &generic_crt_640x480;
static int __init cmx2xx_set_display(char *str)
{
int disp_type = simple_strtol(str, NULL, 0);
switch (disp_type) {
case MTYPE_STN320x240:
cmx2xx_display = &generic_stn_320x240;
break;
case MTYPE_TFT640x480:
cmx2xx_display = &generic_tft_640x480;
break;
case MTYPE_CRT640x480:
cmx2xx_display = &generic_crt_640x480;
break;
case MTYPE_CRT800x600:
cmx2xx_display = &generic_crt_800x600;
break;
case MTYPE_TFT320x240:
cmx2xx_display = &generic_tft_320x240;
break;
case MTYPE_STN640x480:
cmx2xx_display = &generic_stn_640x480;
break;
default: /* fallback to CRT 640x480 */
cmx2xx_display = &generic_crt_640x480;
break;
}
return 1;
}
/*
This should be done really early to get proper configuration for
frame buffer.
Indeed, pxafb parameters can be used istead, but CM-X2XX bootloader
has limitied line length for kernel command line, and also it will
break compatibitlty with proprietary releases already in field.
*/
__setup("monitor=", cmx2xx_set_display);
static void __init cmx2xx_init_display(void)
{
set_pxa_fb_info(cmx2xx_display);
}
#else
static inline void cmx2xx_init_display(void) {}
#endif
#ifdef CONFIG_PM
static unsigned long sleep_save_msc[10];
static int cmx2xx_suspend(struct sys_device *dev, pm_message_t state)
{
cmx2xx_pci_suspend();
/* save MSC registers */
sleep_save_msc[0] = MSC0;
sleep_save_msc[1] = MSC1;
sleep_save_msc[2] = MSC2;
/* setup power saving mode registers */
PCFR = 0x0;
PSLR = 0xff400000;
PMCR = 0x00000005;
PWER = 0x80000000;
PFER = 0x00000000;
PRER = 0x00000000;
PGSR0 = 0xC0018800;
PGSR1 = 0x004F0002;
PGSR2 = 0x6021C000;
PGSR3 = 0x00020000;
return 0;
}
static int cmx2xx_resume(struct sys_device *dev)
{
cmx2xx_pci_resume();
/* restore MSC registers */
MSC0 = sleep_save_msc[0];
MSC1 = sleep_save_msc[1];
MSC2 = sleep_save_msc[2];
return 0;
}
static struct sysdev_class cmx2xx_pm_sysclass = {
.name = "pm",
.resume = cmx2xx_resume,
.suspend = cmx2xx_suspend,
};
static struct sys_device cmx2xx_pm_device = {
.cls = &cmx2xx_pm_sysclass,
};
static int __init cmx2xx_pm_init(void)
{
int error;
error = sysdev_class_register(&cmx2xx_pm_sysclass);
if (error == 0)
error = sysdev_register(&cmx2xx_pm_device);
return error;
}
#else
static int __init cmx2xx_pm_init(void) { return 0; }
#endif
#if defined(CONFIG_SND_PXA2XX_AC97) || defined(CONFIG_SND_PXA2XX_AC97_MODULE)
static void __init cmx2xx_init_ac97(void)
{
pxa_set_ac97_info(NULL);
}
#else
static inline void cmx2xx_init_ac97(void) {}
#endif
static void __init cmx2xx_init(void)
{
cmx2xx_pm_init();
if (cpu_is_pxa25x())
cmx255_init();
else
cmx270_init();
cmx2xx_init_dm9000();
cmx2xx_init_display();
cmx2xx_init_ac97();
cmx2xx_init_touchscreen();
cmx2xx_init_leds();
}
static void __init cmx2xx_init_irq(void)
{
pxa27x_init_irq();
if (cpu_is_pxa25x()) {
pxa25x_init_irq();
cmx2xx_pci_init_irq(CMX255_GPIO_IT8152_IRQ);
} else {
pxa27x_init_irq();
cmx2xx_pci_init_irq(CMX270_GPIO_IT8152_IRQ);
}
}
#ifdef CONFIG_PCI
/* Map PCI companion statically */
static struct map_desc cmx2xx_io_desc[] __initdata = {
[0] = { /* PCI bridge */
.virtual = CMX2XX_IT8152_VIRT,
.pfn = __phys_to_pfn(PXA_CS4_PHYS),
.length = SZ_64M,
.type = MT_DEVICE
},
};
static void __init cmx2xx_map_io(void)
{
pxa_map_io();
iotable_init(cmx2xx_io_desc, ARRAY_SIZE(cmx2xx_io_desc));
it8152_base_address = CMX2XX_IT8152_VIRT;
}
#else
static void __init cmx2xx_map_io(void)
{
pxa_map_io();
}
#endif
MACHINE_START(ARMCORE, "Compulab CM-X2XX")
.boot_params = 0xa0000100,
.phys_io = 0x40000000,
.io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
.map_io = cmx2xx_map_io,
.init_irq = cmx2xx_init_irq,
.timer = &pxa_timer,
.init_machine = cmx2xx_init,
MACHINE_END

465
arch/arm/mach-pxa/cm-x300.c Normal file
View file

@ -0,0 +1,465 @@
/*
* linux/arch/arm/mach-pxa/cm-x300.c
*
* Support for the CompuLab CM-X300 modules
*
* Copyright (C) 2008 CompuLab Ltd.
*
* Mike Rapoport <mike@compulab.co.il>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/dm9000.h>
#include <linux/leds.h>
#include <linux/i2c.h>
#include <linux/i2c/pca953x.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <mach/mfp-pxa300.h>
#include <mach/hardware.h>
#include <mach/gpio.h>
#include <mach/pxafb.h>
#include <mach/mmc.h>
#include <mach/ohci.h>
#include <mach/i2c.h>
#include <mach/pxa3xx_nand.h>
#include <asm/mach/map.h>
#include "generic.h"
#define CM_X300_ETH_PHYS 0x08000010
#define GPIO82_MMC2_IRQ (82)
#define GPIO85_MMC2_WP (85)
#define CM_X300_MMC2_IRQ IRQ_GPIO(GPIO82_MMC2_IRQ)
static mfp_cfg_t cm_x300_mfp_cfg[] __initdata = {
/* LCD */
GPIO54_LCD_LDD_0,
GPIO55_LCD_LDD_1,
GPIO56_LCD_LDD_2,
GPIO57_LCD_LDD_3,
GPIO58_LCD_LDD_4,
GPIO59_LCD_LDD_5,
GPIO60_LCD_LDD_6,
GPIO61_LCD_LDD_7,
GPIO62_LCD_LDD_8,
GPIO63_LCD_LDD_9,
GPIO64_LCD_LDD_10,
GPIO65_LCD_LDD_11,
GPIO66_LCD_LDD_12,
GPIO67_LCD_LDD_13,
GPIO68_LCD_LDD_14,
GPIO69_LCD_LDD_15,
GPIO72_LCD_FCLK,
GPIO73_LCD_LCLK,
GPIO74_LCD_PCLK,
GPIO75_LCD_BIAS,
/* BTUART */
GPIO111_UART2_RTS,
GPIO112_UART2_RXD | MFP_LPM_EDGE_FALL,
GPIO113_UART2_TXD,
GPIO114_UART2_CTS | MFP_LPM_EDGE_BOTH,
/* STUART */
GPIO109_UART3_TXD,
GPIO110_UART3_RXD | MFP_LPM_EDGE_FALL,
/* AC97 */
GPIO23_AC97_nACRESET,
GPIO24_AC97_SYSCLK,
GPIO29_AC97_BITCLK,
GPIO25_AC97_SDATA_IN_0,
GPIO27_AC97_SDATA_OUT,
GPIO28_AC97_SYNC,
/* Keypad */
GPIO115_KP_MKIN_0 | MFP_LPM_EDGE_BOTH,
GPIO116_KP_MKIN_1 | MFP_LPM_EDGE_BOTH,
GPIO117_KP_MKIN_2 | MFP_LPM_EDGE_BOTH,
GPIO118_KP_MKIN_3 | MFP_LPM_EDGE_BOTH,
GPIO119_KP_MKIN_4 | MFP_LPM_EDGE_BOTH,
GPIO120_KP_MKIN_5 | MFP_LPM_EDGE_BOTH,
GPIO2_2_KP_MKIN_6 | MFP_LPM_EDGE_BOTH,
GPIO3_2_KP_MKIN_7 | MFP_LPM_EDGE_BOTH,
GPIO121_KP_MKOUT_0,
GPIO122_KP_MKOUT_1,
GPIO123_KP_MKOUT_2,
GPIO124_KP_MKOUT_3,
GPIO125_KP_MKOUT_4,
GPIO4_2_KP_MKOUT_5,
/* MMC1 */
GPIO3_MMC1_DAT0,
GPIO4_MMC1_DAT1 | MFP_LPM_EDGE_BOTH,
GPIO5_MMC1_DAT2,
GPIO6_MMC1_DAT3,
GPIO7_MMC1_CLK,
GPIO8_MMC1_CMD, /* CMD0 for slot 0 */
/* MMC2 */
GPIO9_MMC2_DAT0,
GPIO10_MMC2_DAT1 | MFP_LPM_EDGE_BOTH,
GPIO11_MMC2_DAT2,
GPIO12_MMC2_DAT3,
GPIO13_MMC2_CLK,
GPIO14_MMC2_CMD,
/* FFUART */
GPIO30_UART1_RXD | MFP_LPM_EDGE_FALL,
GPIO31_UART1_TXD,
GPIO32_UART1_CTS,
GPIO37_UART1_RTS,
GPIO33_UART1_DCD,
GPIO34_UART1_DSR | MFP_LPM_EDGE_FALL,
GPIO35_UART1_RI,
GPIO36_UART1_DTR,
/* GPIOs */
GPIO79_GPIO, /* LED */
GPIO82_GPIO | MFP_PULL_HIGH, /* MMC CD */
GPIO85_GPIO, /* MMC WP */
GPIO99_GPIO, /* Ethernet IRQ */
};
#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
static struct resource dm9000_resources[] = {
[0] = {
.start = CM_X300_ETH_PHYS,
.end = CM_X300_ETH_PHYS + 0x3,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = CM_X300_ETH_PHYS + 0x4,
.end = CM_X300_ETH_PHYS + 0x4 + 500,
.flags = IORESOURCE_MEM,
},
[2] = {
.start = IRQ_GPIO(mfp_to_gpio(MFP_PIN_GPIO99)),
.end = IRQ_GPIO(mfp_to_gpio(MFP_PIN_GPIO99)),
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
}
};
static struct dm9000_plat_data cm_x300_dm9000_platdata = {
.flags = DM9000_PLATF_16BITONLY,
};
static struct platform_device dm9000_device = {
.name = "dm9000",
.id = 0,
.num_resources = ARRAY_SIZE(dm9000_resources),
.resource = dm9000_resources,
.dev = {
.platform_data = &cm_x300_dm9000_platdata,
}
};
static void __init cm_x300_init_dm9000(void)
{
platform_device_register(&dm9000_device);
}
#else
static inline void cm_x300_init_dm9000(void) {}
#endif
#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
static struct pxafb_mode_info cm_x300_lcd_modes[] = {
[0] = {
.pixclock = 38000,
.bpp = 16,
.xres = 480,
.yres = 640,
.hsync_len = 8,
.vsync_len = 2,
.left_margin = 8,
.upper_margin = 0,
.right_margin = 24,
.lower_margin = 4,
.cmap_greyscale = 0,
},
[1] = {
.pixclock = 153800,
.bpp = 16,
.xres = 240,
.yres = 320,
.hsync_len = 8,
.vsync_len = 2,
.left_margin = 8,
.upper_margin = 2,
.right_margin = 88,
.lower_margin = 2,
.cmap_greyscale = 0,
},
};
static struct pxafb_mach_info cm_x300_lcd = {
.modes = cm_x300_lcd_modes,
.num_modes = 2,
.lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
};
static void __init cm_x300_init_lcd(void)
{
set_pxa_fb_info(&cm_x300_lcd);
}
#else
static inline void cm_x300_init_lcd(void) {}
#endif
#if defined(CONFIG_MTD_NAND_PXA3xx) || defined(CONFIG_MTD_NAND_PXA3xx_MODULE)
static struct mtd_partition cm_x300_nand_partitions[] = {
[0] = {
.name = "OBM",
.offset = 0,
.size = SZ_256K,
.mask_flags = MTD_WRITEABLE, /* force read-only */
},
[1] = {
.name = "U-Boot",
.offset = MTDPART_OFS_APPEND,
.size = SZ_256K,
.mask_flags = MTD_WRITEABLE, /* force read-only */
},
[2] = {
.name = "Environment",
.offset = MTDPART_OFS_APPEND,
.size = SZ_256K,
},
[3] = {
.name = "reserved",
.offset = MTDPART_OFS_APPEND,
.size = SZ_256K + SZ_1M,
.mask_flags = MTD_WRITEABLE, /* force read-only */
},
[4] = {
.name = "kernel",
.offset = MTDPART_OFS_APPEND,
.size = SZ_4M,
},
[5] = {
.name = "fs",
.offset = MTDPART_OFS_APPEND,
.size = MTDPART_SIZ_FULL,
},
};
static struct pxa3xx_nand_platform_data cm_x300_nand_info = {
.enable_arbiter = 1,
.parts = cm_x300_nand_partitions,
.nr_parts = ARRAY_SIZE(cm_x300_nand_partitions),
};
static void __init cm_x300_init_nand(void)
{
pxa3xx_set_nand_info(&cm_x300_nand_info);
}
#else
static inline void cm_x300_init_nand(void) {}
#endif
#if defined(CONFIG_MMC) || defined(CONFIG_MMC_MODULE)
/* The first MMC slot of CM-X300 is hardwired to Libertas card and has
no detection/ro pins */
static int cm_x300_mci_init(struct device *dev,
irq_handler_t cm_x300_detect_int,
void *data)
{
return 0;
}
static void cm_x300_mci_exit(struct device *dev, void *data)
{
}
static struct pxamci_platform_data cm_x300_mci_platform_data = {
.detect_delay = 20,
.ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
.init = cm_x300_mci_init,
.exit = cm_x300_mci_exit,
};
static int cm_x300_mci2_ro(struct device *dev)
{
return gpio_get_value(GPIO85_MMC2_WP);
}
static int cm_x300_mci2_init(struct device *dev,
irq_handler_t cm_x300_detect_int,
void *data)
{
int err;
/*
* setup GPIO for CM-X300 MMC controller
*/
err = gpio_request(GPIO82_MMC2_IRQ, "mmc card detect");
if (err)
goto err_request_cd;
gpio_direction_input(GPIO82_MMC2_IRQ);
err = gpio_request(GPIO85_MMC2_WP, "mmc write protect");
if (err)
goto err_request_wp;
gpio_direction_input(GPIO85_MMC2_WP);
err = request_irq(CM_X300_MMC2_IRQ, cm_x300_detect_int,
IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
"MMC card detect", data);
if (err) {
printk(KERN_ERR "%s: MMC/SD/SDIO: "
"can't request card detect IRQ\n", __func__);
goto err_request_irq;
}
return 0;
err_request_irq:
gpio_free(GPIO85_MMC2_WP);
err_request_wp:
gpio_free(GPIO82_MMC2_IRQ);
err_request_cd:
return err;
}
static void cm_x300_mci2_exit(struct device *dev, void *data)
{
free_irq(CM_X300_MMC2_IRQ, data);
gpio_free(GPIO82_MMC2_IRQ);
gpio_free(GPIO85_MMC2_WP);
}
static struct pxamci_platform_data cm_x300_mci2_platform_data = {
.detect_delay = 20,
.ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
.init = cm_x300_mci2_init,
.exit = cm_x300_mci2_exit,
.get_ro = cm_x300_mci2_ro,
};
static void __init cm_x300_init_mmc(void)
{
pxa_set_mci_info(&cm_x300_mci_platform_data);
pxa3xx_set_mci2_info(&cm_x300_mci2_platform_data);
}
#else
static inline void cm_x300_init_mmc(void) {}
#endif
#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
static struct pxaohci_platform_data cm_x300_ohci_platform_data = {
.port_mode = PMM_PERPORT_MODE,
.flags = ENABLE_PORT1 | ENABLE_PORT2 | POWER_CONTROL_LOW,
};
static void __init cm_x300_init_ohci(void)
{
pxa_set_ohci_info(&cm_x300_ohci_platform_data);
}
#else
static inline void cm_x300_init_ohci(void) {}
#endif
#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
static struct gpio_led cm_x300_leds[] = {
[0] = {
.name = "cm-x300:green",
.default_trigger = "heartbeat",
.gpio = 79,
.active_low = 1,
},
};
static struct gpio_led_platform_data cm_x300_gpio_led_pdata = {
.num_leds = ARRAY_SIZE(cm_x300_leds),
.leds = cm_x300_leds,
};
static struct platform_device cm_x300_led_device = {
.name = "leds-gpio",
.id = -1,
.dev = {
.platform_data = &cm_x300_gpio_led_pdata,
},
};
static void __init cm_x300_init_leds(void)
{
platform_device_register(&cm_x300_led_device);
}
#else
static inline void cm_x300_init_leds(void) {}
#endif
#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
/* PCA9555 */
static struct pca953x_platform_data cm_x300_gpio_ext_pdata_0 = {
.gpio_base = 128,
};
static struct pca953x_platform_data cm_x300_gpio_ext_pdata_1 = {
.gpio_base = 144,
};
static struct i2c_board_info cm_x300_gpio_ext_info[] = {
[0] = {
I2C_BOARD_INFO("pca9555", 0x24),
.platform_data = &cm_x300_gpio_ext_pdata_0,
},
[1] = {
I2C_BOARD_INFO("pca9555", 0x25),
.platform_data = &cm_x300_gpio_ext_pdata_1,
},
};
static void __init cm_x300_init_i2c(void)
{
pxa_set_i2c_info(NULL);
i2c_register_board_info(0, cm_x300_gpio_ext_info,
ARRAY_SIZE(cm_x300_gpio_ext_info));
}
#else
static inline void cm_x300_init_i2c(void) {}
#endif
static void __init cm_x300_init(void)
{
/* board-processor specific GPIO initialization */
pxa3xx_mfp_config(ARRAY_AND_SIZE(cm_x300_mfp_cfg));
cm_x300_init_dm9000();
cm_x300_init_lcd();
cm_x300_init_ohci();
cm_x300_init_mmc();
cm_x300_init_nand();
cm_x300_init_leds();
cm_x300_init_i2c();
}
MACHINE_START(CM_X300, "CM-X300 module")
.phys_io = 0x40000000,
.boot_params = 0xa0000100,
.io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
.map_io = pxa_map_io,
.init_irq = pxa3xx_init_irq,
.timer = &pxa_timer,
.init_machine = cm_x300_init,
MACHINE_END

11
arch/arm/mach-pxa/colibri.c
View file

@ -29,12 +29,17 @@
#include <asm/mach/irq.h>
#include <asm/mach/flash.h>
#include <mach/pxa-regs.h>
#include <mach/pxa2xx-gpio.h>
#include <mach/mfp-pxa27x.h>
#include <mach/colibri.h>
#include "generic.h"
#include "devices.h"
static unsigned long colibri_pin_config[] __initdata = {
GPIO78_nCS_2, /* Ethernet CS */
GPIO114_GPIO, /* Ethernet IRQ */
};
/*
* Flash
*/
@ -116,9 +121,7 @@ static struct platform_device *colibri_devices[] __initdata = {
static void __init colibri_init(void)
{
/* DM9000 LAN */
pxa_gpio_mode(GPIO78_nCS_2_MD);
pxa_gpio_mode(GPIO_DM9000 | GPIO_IN);
pxa2xx_mfp_config(ARRAY_AND_SIZE(colibri_pin_config));
platform_add_devices(colibri_devices, ARRAY_SIZE(colibri_devices));
}

480
arch/arm/mach-pxa/corgi.c
View file

@ -20,8 +20,12 @@
#include <linux/interrupt.h>
#include <linux/mmc/host.h>
#include <linux/pm.h>
#include <linux/gpio.h>
#include <linux/backlight.h>
#include <linux/io.h>
#include <linux/spi/spi.h>
#include <linux/spi/ads7846.h>
#include <linux/spi/corgi_lcd.h>
#include <video/w100fb.h>
#include <asm/setup.h>
@ -37,11 +41,12 @@
#include <mach/pxa-regs.h>
#include <mach/pxa2xx-regs.h>
#include <mach/pxa2xx-gpio.h>
#include <mach/mfp-pxa25x.h>
#include <mach/i2c.h>
#include <mach/irda.h>
#include <mach/mmc.h>
#include <mach/udc.h>
#include <mach/pxa2xx_spi.h>
#include <mach/corgi.h>
#include <mach/sharpsl.h>
@ -52,6 +57,61 @@
#include "devices.h"
#include "sharpsl.h"
static unsigned long corgi_pin_config[] __initdata = {
/* Static Memory I/O */
GPIO78_nCS_2, /* w100fb */
GPIO80_nCS_4, /* scoop */
/* SSP1 */
GPIO23_SSP1_SCLK,
GPIO25_SSP1_TXD,
GPIO26_SSP1_RXD,
GPIO24_GPIO, /* CORGI_GPIO_ADS7846_CS - SFRM as chip select */
/* I2S */
GPIO28_I2S_BITCLK_OUT,
GPIO29_I2S_SDATA_IN,
GPIO30_I2S_SDATA_OUT,
GPIO31_I2S_SYNC,
GPIO32_I2S_SYSCLK,
/* Infra-Red */
GPIO47_FICP_TXD,
GPIO46_FICP_RXD,
/* FFUART */
GPIO40_FFUART_DTR,
GPIO41_FFUART_RTS,
GPIO39_FFUART_TXD,
GPIO37_FFUART_DSR,
GPIO34_FFUART_RXD,
GPIO35_FFUART_CTS,
/* PC Card */
GPIO48_nPOE,
GPIO49_nPWE,
GPIO50_nPIOR,
GPIO51_nPIOW,
GPIO52_nPCE_1,
GPIO53_nPCE_2,
GPIO54_nPSKTSEL,
GPIO55_nPREG,
GPIO56_nPWAIT,
GPIO57_nIOIS16,
/* MMC */
GPIO6_MMC_CLK,
GPIO8_MMC_CS0,
/* GPIO */
GPIO9_GPIO, /* CORGI_GPIO_nSD_DETECT */
GPIO7_GPIO, /* CORGI_GPIO_nSD_WP */
GPIO33_GPIO, /* CORGI_GPIO_SD_PWR */
GPIO22_GPIO, /* CORGI_GPIO_IR_ON */
GPIO44_GPIO, /* CORGI_GPIO_HSYNC */
GPIO1_GPIO | WAKEUP_ON_EDGE_RISE,
};
/*
* Corgi SCOOP Device
@ -67,6 +127,7 @@ static struct resource corgi_scoop_resources[] = {
static struct scoop_config corgi_scoop_setup = {
.io_dir = CORGI_SCOOP_IO_DIR,
.io_out = CORGI_SCOOP_IO_OUT,
.gpio_base = CORGI_SCOOP_GPIO_BASE,
};
struct platform_device corgiscoop_device = {
@ -79,27 +140,6 @@ struct platform_device corgiscoop_device = {
.resource = corgi_scoop_resources,
};
static void corgi_pcmcia_init(void)
{
/* Setup default state of GPIO outputs
before we enable them as outputs. */
GPSR(GPIO48_nPOE) = GPIO_bit(GPIO48_nPOE) |
GPIO_bit(GPIO49_nPWE) | GPIO_bit(GPIO50_nPIOR) |
GPIO_bit(GPIO51_nPIOW) | GPIO_bit(GPIO52_nPCE_1) |
GPIO_bit(GPIO53_nPCE_2);
pxa_gpio_mode(GPIO48_nPOE_MD);
pxa_gpio_mode(GPIO49_nPWE_MD);
pxa_gpio_mode(GPIO50_nPIOR_MD);
pxa_gpio_mode(GPIO51_nPIOW_MD);
pxa_gpio_mode(GPIO55_nPREG_MD);
pxa_gpio_mode(GPIO56_nPWAIT_MD);
pxa_gpio_mode(GPIO57_nIOIS16_MD);
pxa_gpio_mode(GPIO52_nPCE_1_MD);
pxa_gpio_mode(GPIO53_nPCE_2_MD);
pxa_gpio_mode(GPIO54_pSKTSEL_MD);
}
static struct scoop_pcmcia_dev corgi_pcmcia_scoop[] = {
{
.dev = &corgiscoop_device.dev,
@ -112,58 +152,10 @@ static struct scoop_pcmcia_dev corgi_pcmcia_scoop[] = {
static struct scoop_pcmcia_config corgi_pcmcia_config = {
.devs = &corgi_pcmcia_scoop[0],
.num_devs = 1,
.pcmcia_init = corgi_pcmcia_init,
};
EXPORT_SYMBOL(corgiscoop_device);
/*
* Corgi SSP Device
*
* Set the parent as the scoop device because a lot of SSP devices
* also use scoop functions and this makes the power up/down order
* work correctly.
*/
struct platform_device corgissp_device = {
.name = "corgi-ssp",
.dev = {
.parent = &corgiscoop_device.dev,
},
.id = -1,
};
struct corgissp_machinfo corgi_ssp_machinfo = {
.port = 1,
.cs_lcdcon = CORGI_GPIO_LCDCON_CS,
.cs_ads7846 = CORGI_GPIO_ADS7846_CS,
.cs_max1111 = CORGI_GPIO_MAX1111_CS,
.clk_lcdcon = 76,
.clk_ads7846 = 2,
.clk_max1111 = 8,
};
/*
* LCD/Framebuffer
*/
static void w100_lcdtg_suspend(struct w100fb_par *par)
{
corgi_lcdtg_suspend();
}
static void w100_lcdtg_init(struct w100fb_par *par)
{
corgi_lcdtg_hw_init(par->xres);
}
static struct w100_tg_info corgi_lcdtg_info = {
.change = w100_lcdtg_init,
.suspend = w100_lcdtg_suspend,
.resume = w100_lcdtg_init,
};
static struct w100_mem_info corgi_fb_mem = {
.ext_cntl = 0x00040003,
.sdram_mode_reg = 0x00650021,
@ -242,7 +234,6 @@ static struct w100_mode corgi_fb_modes[] = {
};
static struct w100fb_mach_info corgi_fb_info = {
.tg = &corgi_lcdtg_info,
.init_mode = INIT_MODE_ROTATED,
.mem = &corgi_fb_mem,
.regs = &corgi_fb_regs,
@ -268,60 +259,10 @@ static struct platform_device corgifb_device = {
.resource = corgi_fb_resources,
.dev = {
.platform_data = &corgi_fb_info,
.parent = &corgissp_device.dev,
},
};
/*
* Corgi Backlight Device
*/
static void corgi_bl_kick_battery(void)
{
void (*kick_batt)(void);
kick_batt = symbol_get(sharpsl_battery_kick);
if (kick_batt) {
kick_batt();
symbol_put(sharpsl_battery_kick);
}
}
static void corgi_bl_set_intensity(int intensity)
{
if (intensity > 0x10)
intensity += 0x10;
/* Bits 0-4 are accessed via the SSP interface */
corgi_ssp_blduty_set(intensity & 0x1f);
/* Bit 5 is via SCOOP */
if (intensity & 0x0020)
set_scoop_gpio(&corgiscoop_device.dev, CORGI_SCP_BACKLIGHT_CONT);
else
reset_scoop_gpio(&corgiscoop_device.dev, CORGI_SCP_BACKLIGHT_CONT);
}
static struct generic_bl_info corgi_bl_machinfo = {
.name = "corgi-bl",
.max_intensity = 0x2f,
.default_intensity = 0x1f,
.limit_mask = 0x0b,
.set_bl_intensity = corgi_bl_set_intensity,
.kick_battery = corgi_bl_kick_battery,
};
static struct platform_device corgibl_device = {
.name = "generic-bl",
.dev = {
.parent = &corgifb_device.dev,
.platform_data = &corgi_bl_machinfo,
},
.id = -1,
};
/*
* Corgi Keyboard Device
*/
@ -330,75 +271,35 @@ static struct platform_device corgikbd_device = {
.id = -1,
};
/*
* Corgi LEDs
*/
static struct gpio_led corgi_gpio_leds[] = {
{
.name = "corgi:amber:charge",
.default_trigger = "sharpsl-charge",
.gpio = CORGI_GPIO_LED_ORANGE,
},
{
.name = "corgi:green:mail",
.default_trigger = "nand-disk",
.gpio = CORGI_GPIO_LED_GREEN,
},
};
static struct gpio_led_platform_data corgi_gpio_leds_info = {
.leds = corgi_gpio_leds,
.num_leds = ARRAY_SIZE(corgi_gpio_leds),
};
static struct platform_device corgiled_device = {
.name = "corgi-led",
.name = "leds-gpio",
.id = -1,
};
/*
* Corgi Touch Screen Device
*/
static unsigned long (*get_hsync_invperiod)(struct device *dev);
static void inline sharpsl_wait_sync(int gpio)
{
while((GPLR(gpio) & GPIO_bit(gpio)) == 0);
while((GPLR(gpio) & GPIO_bit(gpio)) != 0);
}
static unsigned long corgi_get_hsync_invperiod(void)
{
if (!get_hsync_invperiod)
get_hsync_invperiod = symbol_get(w100fb_get_hsynclen);
if (!get_hsync_invperiod)
return 0;
return get_hsync_invperiod(&corgifb_device.dev);
}
static void corgi_put_hsync(void)
{
if (get_hsync_invperiod)
symbol_put(w100fb_get_hsynclen);
get_hsync_invperiod = NULL;
}
static void corgi_wait_hsync(void)
{
sharpsl_wait_sync(CORGI_GPIO_HSYNC);
}
static struct resource corgits_resources[] = {
[0] = {
.start = CORGI_IRQ_GPIO_TP_INT,
.end = CORGI_IRQ_GPIO_TP_INT,
.flags = IORESOURCE_IRQ,
},
};
static struct corgits_machinfo corgi_ts_machinfo = {
.get_hsync_invperiod = corgi_get_hsync_invperiod,
.put_hsync = corgi_put_hsync,
.wait_hsync = corgi_wait_hsync,
};
static struct platform_device corgits_device = {
.name = "corgi-ts",
.dev = {
.parent = &corgissp_device.dev,
.platform_data = &corgi_ts_machinfo,
.platform_data = &corgi_gpio_leds_info,
},
.id = -1,
.num_resources = ARRAY_SIZE(corgits_resources),
.resource = corgits_resources,
};
/*
* MMC/SD Device
*
@ -411,20 +312,42 @@ static int corgi_mci_init(struct device *dev, irq_handler_t corgi_detect_int, vo
{
int err;
/* setup GPIO for PXA25x MMC controller */
pxa_gpio_mode(GPIO6_MMCCLK_MD);
pxa_gpio_mode(GPIO8_MMCCS0_MD);
pxa_gpio_mode(CORGI_GPIO_nSD_DETECT | GPIO_IN);
pxa_gpio_mode(CORGI_GPIO_SD_PWR | GPIO_OUT);
err = gpio_request(CORGI_GPIO_nSD_DETECT, "nSD_DETECT");
if (err)
goto err_out;
err = gpio_request(CORGI_GPIO_nSD_WP, "nSD_WP");
if (err)
goto err_free_1;
err = gpio_request(CORGI_GPIO_SD_PWR, "SD_PWR");
if (err)
goto err_free_2;
gpio_direction_input(CORGI_GPIO_nSD_DETECT);
gpio_direction_input(CORGI_GPIO_nSD_WP);
gpio_direction_output(CORGI_GPIO_SD_PWR, 0);
corgi_mci_platform_data.detect_delay = msecs_to_jiffies(250);
err = request_irq(CORGI_IRQ_GPIO_nSD_DETECT, corgi_detect_int,
IRQF_DISABLED | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
"MMC card detect", data);
if (err)
printk(KERN_ERR "corgi_mci_init: MMC/SD: can't request MMC card detect IRQ\n");
IRQF_DISABLED | IRQF_TRIGGER_RISING |
IRQF_TRIGGER_FALLING,
"MMC card detect", data);
if (err) {
pr_err("%s: MMC/SD: can't request MMC card detect IRQ\n",
__func__);
goto err_free_3;
}
return 0;
err_free_3:
gpio_free(CORGI_GPIO_SD_PWR);
err_free_2:
gpio_free(CORGI_GPIO_nSD_WP);
err_free_1:
gpio_free(CORGI_GPIO_nSD_DETECT);
err_out:
return err;
}
@ -432,20 +355,20 @@ static void corgi_mci_setpower(struct device *dev, unsigned int vdd)
{
struct pxamci_platform_data* p_d = dev->platform_data;
if (( 1 << vdd) & p_d->ocr_mask)
GPSR1 = GPIO_bit(CORGI_GPIO_SD_PWR);
else
GPCR1 = GPIO_bit(CORGI_GPIO_SD_PWR);
gpio_set_value(CORGI_GPIO_SD_PWR, ((1 << vdd) & p_d->ocr_mask));
}
static int corgi_mci_get_ro(struct device *dev)
{
return GPLR(CORGI_GPIO_nSD_WP) & GPIO_bit(CORGI_GPIO_nSD_WP);
return gpio_get_value(CORGI_GPIO_nSD_WP);
}
static void corgi_mci_exit(struct device *dev, void *data)
{
free_irq(CORGI_IRQ_GPIO_nSD_DETECT, data);
gpio_free(CORGI_GPIO_SD_PWR);
gpio_free(CORGI_GPIO_nSD_WP);
gpio_free(CORGI_GPIO_nSD_DETECT);
}
static struct pxamci_platform_data corgi_mci_platform_data = {
@ -462,16 +385,32 @@ static struct pxamci_platform_data corgi_mci_platform_data = {
*/
static void corgi_irda_transceiver_mode(struct device *dev, int mode)
{
if (mode & IR_OFF)
GPSR(CORGI_GPIO_IR_ON) = GPIO_bit(CORGI_GPIO_IR_ON);
else
GPCR(CORGI_GPIO_IR_ON) = GPIO_bit(CORGI_GPIO_IR_ON);
gpio_set_value(CORGI_GPIO_IR_ON, mode & IR_OFF);
pxa2xx_transceiver_mode(dev, mode);
}
static int corgi_irda_startup(struct device *dev)
{
int err;
err = gpio_request(CORGI_GPIO_IR_ON, "IR_ON");
if (err)
return err;
gpio_direction_output(CORGI_GPIO_IR_ON, 1);
return 0;
}
static void corgi_irda_shutdown(struct device *dev)
{
gpio_free(CORGI_GPIO_IR_ON);
}
static struct pxaficp_platform_data corgi_ficp_platform_data = {
.transceiver_cap = IR_SIRMODE | IR_OFF,
.transceiver_mode = corgi_irda_transceiver_mode,
.transceiver_cap = IR_SIRMODE | IR_OFF,
.transceiver_mode = corgi_irda_transceiver_mode,
.startup = corgi_irda_startup,
.shutdown = corgi_irda_shutdown,
};
@ -483,14 +422,129 @@ static struct pxa2xx_udc_mach_info udc_info __initdata = {
.gpio_pullup = CORGI_GPIO_USB_PULLUP,
};
#if defined(CONFIG_SPI_PXA2XX) || defined(CONFIG_SPI_PXA2XX_MASTER)
static struct pxa2xx_spi_master corgi_spi_info = {
.num_chipselect = 3,
};
static struct ads7846_platform_data corgi_ads7846_info = {
.model = 7846,
.vref_delay_usecs = 100,
.x_plate_ohms = 419,
.y_plate_ohms = 486,
.gpio_pendown = CORGI_GPIO_TP_INT,
};
static void corgi_ads7846_cs(u32 command)
{
gpio_set_value(CORGI_GPIO_ADS7846_CS, !(command == PXA2XX_CS_ASSERT));
}
static struct pxa2xx_spi_chip corgi_ads7846_chip = {
.cs_control = corgi_ads7846_cs,
};
static void corgi_bl_kick_battery(void)
{
void (*kick_batt)(void);
kick_batt = symbol_get(sharpsl_battery_kick);
if (kick_batt) {
kick_batt();
symbol_put(sharpsl_battery_kick);
}
}
static struct corgi_lcd_platform_data corgi_lcdcon_info = {
.init_mode = CORGI_LCD_MODE_VGA,
.max_intensity = 0x2f,
.default_intensity = 0x1f,
.limit_mask = 0x0b,
.gpio_backlight_cont = CORGI_GPIO_BACKLIGHT_CONT,
.gpio_backlight_on = -1,
.kick_battery = corgi_bl_kick_battery,
};
static void corgi_lcdcon_cs(u32 command)
{
gpio_set_value(CORGI_GPIO_LCDCON_CS, !(command == PXA2XX_CS_ASSERT));
}
static struct pxa2xx_spi_chip corgi_lcdcon_chip = {
.cs_control = corgi_lcdcon_cs,
};
static void corgi_max1111_cs(u32 command)
{
gpio_set_value(CORGI_GPIO_MAX1111_CS, !(command == PXA2XX_CS_ASSERT));
}
static struct pxa2xx_spi_chip corgi_max1111_chip = {
.cs_control = corgi_max1111_cs,
};
static struct spi_board_info corgi_spi_devices[] = {
{
.modalias = "ads7846",
.max_speed_hz = 1200000,
.bus_num = 1,
.chip_select = 0,
.platform_data = &corgi_ads7846_info,
.controller_data= &corgi_ads7846_chip,
.irq = gpio_to_irq(CORGI_GPIO_TP_INT),
}, {
.modalias = "corgi-lcd",
.max_speed_hz = 50000,
.bus_num = 1,
.chip_select = 1,
.platform_data = &corgi_lcdcon_info,
.controller_data= &corgi_lcdcon_chip,
}, {
.modalias = "max1111",
.max_speed_hz = 450000,
.bus_num = 1,
.chip_select = 2,
.controller_data= &corgi_max1111_chip,
},
};
static void __init corgi_init_spi(void)
{
int err;
err = gpio_request(CORGI_GPIO_ADS7846_CS, "ADS7846_CS");
if (err)
return;
err = gpio_request(CORGI_GPIO_LCDCON_CS, "LCDCON_CS");
if (err)
goto err_free_1;
err = gpio_request(CORGI_GPIO_MAX1111_CS, "MAX1111_CS");
if (err)
goto err_free_2;
gpio_direction_output(CORGI_GPIO_ADS7846_CS, 1);
gpio_direction_output(CORGI_GPIO_LCDCON_CS, 1);
gpio_direction_output(CORGI_GPIO_MAX1111_CS, 1);
pxa2xx_set_spi_info(1, &corgi_spi_info);
spi_register_board_info(ARRAY_AND_SIZE(corgi_spi_devices));
return;
err_free_2:
gpio_free(CORGI_GPIO_LCDCON_CS);
err_free_1:
gpio_free(CORGI_GPIO_ADS7846_CS);
}
#else
static inline void corgi_init_spi(void) {}
#endif
static struct platform_device *devices[] __initdata = {
&corgiscoop_device,
&corgissp_device,
&corgifb_device,
&corgikbd_device,
&corgibl_device,
&corgits_device,
&corgiled_device,
};
@ -498,7 +552,8 @@ static void corgi_poweroff(void)
{
if (!machine_is_corgi())
/* Green LED off tells the bootloader to halt */
reset_scoop_gpio(&corgiscoop_device.dev, CORGI_SCP_LED_GREEN);
gpio_set_value(CORGI_GPIO_LED_GREEN, 0);
arm_machine_restart('h');
}
@ -506,7 +561,8 @@ static void corgi_restart(char mode)
{
if (!machine_is_corgi())
/* Green LED on tells the bootloader to reboot */
set_scoop_gpio(&corgiscoop_device.dev, CORGI_SCP_LED_GREEN);
gpio_set_value(CORGI_GPIO_LED_GREEN, 1);
arm_machine_restart('h');
}
@ -515,20 +571,12 @@ static void __init corgi_init(void)
pm_power_off = corgi_poweroff;
arm_pm_restart = corgi_restart;
/* setup sleep mode values */
PWER = 0x00000002;
PFER = 0x00000000;
PRER = 0x00000002;
PGSR0 = 0x0158C000;
PGSR1 = 0x00FF0080;
PGSR2 = 0x0001C004;
/* Stop 3.6MHz and drive HIGH to PCMCIA and CS */
PCFR |= PCFR_OPDE;
corgi_ssp_set_machinfo(&corgi_ssp_machinfo);
pxa2xx_mfp_config(ARRAY_AND_SIZE(corgi_pin_config));
pxa_gpio_mode(CORGI_GPIO_IR_ON | GPIO_OUT);
pxa_gpio_mode(CORGI_GPIO_HSYNC | GPIO_IN);
corgi_init_spi();
pxa_set_udc_info(&udc_info);
pxa_set_mci_info(&corgi_mci_platform_data);

290
arch/arm/mach-pxa/corgi_lcd.c
View file

@ -1,290 +0,0 @@
/*
* linux/arch/arm/mach-pxa/corgi_lcd.c
*
* Corgi/Spitz LCD Specific Code
*
* Copyright (C) 2005 Richard Purdie
*
* Connectivity:
* Corgi - LCD to ATI Imageon w100 (Wallaby)
* Spitz - LCD to PXA Framebuffer
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/delay.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/string.h>
#include <mach/akita.h>
#include <mach/corgi.h>
#include <mach/hardware.h>
#include <mach/pxa-regs.h>
#include <mach/sharpsl.h>
#include <mach/spitz.h>
#include <asm/hardware/scoop.h>
#include <asm/mach/sharpsl_param.h>
#include "generic.h"
/* Register Addresses */
#define RESCTL_ADRS 0x00
#define PHACTRL_ADRS 0x01
#define DUTYCTRL_ADRS 0x02
#define POWERREG0_ADRS 0x03
#define POWERREG1_ADRS 0x04
#define GPOR3_ADRS 0x05
#define PICTRL_ADRS 0x06
#define POLCTRL_ADRS 0x07
/* Register Bit Definitions */
#define RESCTL_QVGA 0x01
#define RESCTL_VGA 0x00
#define POWER1_VW_ON 0x01 /* VW Supply FET ON */
#define POWER1_GVSS_ON 0x02 /* GVSS(-8V) Power Supply ON */
#define POWER1_VDD_ON 0x04 /* VDD(8V),SVSS(-4V) Power Supply ON */
#define POWER1_VW_OFF 0x00 /* VW Supply FET OFF */
#define POWER1_GVSS_OFF 0x00 /* GVSS(-8V) Power Supply OFF */
#define POWER1_VDD_OFF 0x00 /* VDD(8V),SVSS(-4V) Power Supply OFF */
#define POWER0_COM_DCLK 0x01 /* COM Voltage DC Bias DAC Serial Data Clock */
#define POWER0_COM_DOUT 0x02 /* COM Voltage DC Bias DAC Serial Data Out */
#define POWER0_DAC_ON 0x04 /* DAC Power Supply ON */
#define POWER0_COM_ON 0x08 /* COM Power Supply ON */
#define POWER0_VCC5_ON 0x10 /* VCC5 Power Supply ON */
#define POWER0_DAC_OFF 0x00 /* DAC Power Supply OFF */
#define POWER0_COM_OFF 0x00 /* COM Power Supply OFF */
#define POWER0_VCC5_OFF 0x00 /* VCC5 Power Supply OFF */
#define PICTRL_INIT_STATE 0x01
#define PICTRL_INIOFF 0x02
#define PICTRL_POWER_DOWN 0x04
#define PICTRL_COM_SIGNAL_OFF 0x08
#define PICTRL_DAC_SIGNAL_OFF 0x10
#define POLCTRL_SYNC_POL_FALL 0x01
#define POLCTRL_EN_POL_FALL 0x02
#define POLCTRL_DATA_POL_FALL 0x04
#define POLCTRL_SYNC_ACT_H 0x08
#define POLCTRL_EN_ACT_L 0x10
#define POLCTRL_SYNC_POL_RISE 0x00
#define POLCTRL_EN_POL_RISE 0x00
#define POLCTRL_DATA_POL_RISE 0x00
#define POLCTRL_SYNC_ACT_L 0x00
#define POLCTRL_EN_ACT_H 0x00
#define PHACTRL_PHASE_MANUAL 0x01
#define DEFAULT_PHAD_QVGA (9)
#define DEFAULT_COMADJ (125)
/*
* This is only a psuedo I2C interface. We can't use the standard kernel
* routines as the interface is write only. We just assume the data is acked...
*/
static void lcdtg_ssp_i2c_send(u8 data)
{
corgi_ssp_lcdtg_send(POWERREG0_ADRS, data);
udelay(10);
}
static void lcdtg_i2c_send_bit(u8 data)
{
lcdtg_ssp_i2c_send(data);
lcdtg_ssp_i2c_send(data | POWER0_COM_DCLK);
lcdtg_ssp_i2c_send(data);
}
static void lcdtg_i2c_send_start(u8 base)
{
lcdtg_ssp_i2c_send(base | POWER0_COM_DCLK | POWER0_COM_DOUT);
lcdtg_ssp_i2c_send(base | POWER0_COM_DCLK);
lcdtg_ssp_i2c_send(base);
}
static void lcdtg_i2c_send_stop(u8 base)
{
lcdtg_ssp_i2c_send(base);
lcdtg_ssp_i2c_send(base | POWER0_COM_DCLK);
lcdtg_ssp_i2c_send(base | POWER0_COM_DCLK | POWER0_COM_DOUT);
}
static void lcdtg_i2c_send_byte(u8 base, u8 data)
{
int i;
for (i = 0; i < 8; i++) {
if (data & 0x80)
lcdtg_i2c_send_bit(base | POWER0_COM_DOUT);
else
lcdtg_i2c_send_bit(base);
data <<= 1;
}
}
static void lcdtg_i2c_wait_ack(u8 base)
{
lcdtg_i2c_send_bit(base);
}
static void lcdtg_set_common_voltage(u8 base_data, u8 data)
{
/* Set Common Voltage to M62332FP via I2C */
lcdtg_i2c_send_start(base_data);
lcdtg_i2c_send_byte(base_data, 0x9c);
lcdtg_i2c_wait_ack(base_data);
lcdtg_i2c_send_byte(base_data, 0x00);
lcdtg_i2c_wait_ack(base_data);
lcdtg_i2c_send_byte(base_data, data);
lcdtg_i2c_wait_ack(base_data);
lcdtg_i2c_send_stop(base_data);
}
/* Set Phase Adjust */
static void lcdtg_set_phadadj(int mode)
{
int adj;
switch(mode) {
case 480:
case 640:
/* Setting for VGA */
adj = sharpsl_param.phadadj;
if (adj < 0) {
adj = PHACTRL_PHASE_MANUAL;
} else {
adj = ((adj & 0x0f) << 1) | PHACTRL_PHASE_MANUAL;
}
break;
case 240:
case 320:
default:
/* Setting for QVGA */
adj = (DEFAULT_PHAD_QVGA << 1) | PHACTRL_PHASE_MANUAL;
break;
}
corgi_ssp_lcdtg_send(PHACTRL_ADRS, adj);
}
static int lcd_inited;
void corgi_lcdtg_hw_init(int mode)
{
if (!lcd_inited) {
int comadj;
/* Initialize Internal Logic & Port */
corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_POWER_DOWN | PICTRL_INIOFF | PICTRL_INIT_STATE
| PICTRL_COM_SIGNAL_OFF | PICTRL_DAC_SIGNAL_OFF);
corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_COM_DCLK | POWER0_COM_DOUT | POWER0_DAC_OFF
| POWER0_COM_OFF | POWER0_VCC5_OFF);
corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_OFF | POWER1_VDD_OFF);
/* VDD(+8V), SVSS(-4V) ON */
corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_OFF | POWER1_VDD_ON);
mdelay(3);
/* DAC ON */
corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_COM_DCLK | POWER0_COM_DOUT | POWER0_DAC_ON
| POWER0_COM_OFF | POWER0_VCC5_OFF);
/* INIB = H, INI = L */
/* PICTL[0] = H , PICTL[1] = PICTL[2] = PICTL[4] = L */
corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_INIT_STATE | PICTRL_COM_SIGNAL_OFF);
/* Set Common Voltage */
comadj = sharpsl_param.comadj;
if (comadj < 0)
comadj = DEFAULT_COMADJ;
lcdtg_set_common_voltage((POWER0_DAC_ON | POWER0_COM_OFF | POWER0_VCC5_OFF), comadj);
/* VCC5 ON, DAC ON */
corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_COM_DCLK | POWER0_COM_DOUT | POWER0_DAC_ON |
POWER0_COM_OFF | POWER0_VCC5_ON);
/* GVSS(-8V) ON, VDD ON */
corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_ON | POWER1_VDD_ON);
mdelay(2);
/* COM SIGNAL ON (PICTL[3] = L) */
corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_INIT_STATE);
/* COM ON, DAC ON, VCC5_ON */
corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_COM_DCLK | POWER0_COM_DOUT | POWER0_DAC_ON
| POWER0_COM_ON | POWER0_VCC5_ON);
/* VW ON, GVSS ON, VDD ON */
corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_ON | POWER1_GVSS_ON | POWER1_VDD_ON);
/* Signals output enable */
corgi_ssp_lcdtg_send(PICTRL_ADRS, 0);
/* Set Phase Adjust */
lcdtg_set_phadadj(mode);
/* Initialize for Input Signals from ATI */
corgi_ssp_lcdtg_send(POLCTRL_ADRS, POLCTRL_SYNC_POL_RISE | POLCTRL_EN_POL_RISE
| POLCTRL_DATA_POL_RISE | POLCTRL_SYNC_ACT_L | POLCTRL_EN_ACT_H);
udelay(1000);
lcd_inited=1;
} else {
lcdtg_set_phadadj(mode);
}
switch(mode) {
case 480:
case 640:
/* Set Lcd Resolution (VGA) */
corgi_ssp_lcdtg_send(RESCTL_ADRS, RESCTL_VGA);
break;
case 240:
case 320:
default:
/* Set Lcd Resolution (QVGA) */
corgi_ssp_lcdtg_send(RESCTL_ADRS, RESCTL_QVGA);
break;
}
}
void corgi_lcdtg_suspend(void)
{
/* 60Hz x 2 frame = 16.7msec x 2 = 33.4 msec */
mdelay(34);
/* (1)VW OFF */
corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_ON | POWER1_VDD_ON);
/* (2)COM OFF */
corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_COM_SIGNAL_OFF);
corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_DAC_ON | POWER0_COM_OFF | POWER0_VCC5_ON);
/* (3)Set Common Voltage Bias 0V */
lcdtg_set_common_voltage(POWER0_DAC_ON | POWER0_COM_OFF | POWER0_VCC5_ON, 0);
/* (4)GVSS OFF */
corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_OFF | POWER1_VDD_ON);
/* (5)VCC5 OFF */
corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_DAC_ON | POWER0_COM_OFF | POWER0_VCC5_OFF);
/* (6)Set PDWN, INIOFF, DACOFF */
corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_INIOFF | PICTRL_DAC_SIGNAL_OFF |
PICTRL_POWER_DOWN | PICTRL_COM_SIGNAL_OFF);
/* (7)DAC OFF */
corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_DAC_OFF | POWER0_COM_OFF | POWER0_VCC5_OFF);
/* (8)VDD OFF */
corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_OFF | POWER1_VDD_OFF);
lcd_inited = 0;
}

1
arch/arm/mach-pxa/corgi_pm.c
View file

@ -21,7 +21,6 @@
#include <asm/irq.h>
#include <asm/mach-types.h>
#include <mach/hardware.h>
#include <asm/hardware/scoop.h>
#include <mach/sharpsl.h>
#include <mach/corgi.h>

276
arch/arm/mach-pxa/corgi_ssp.c
View file

@ -1,276 +0,0 @@
/*
* SSP control code for Sharp Corgi devices
*
* Copyright (c) 2004-2005 Richard Purdie
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <mach/ssp.h>
#include <mach/pxa-regs.h>
#include <mach/pxa2xx-gpio.h>
#include <mach/regs-ssp.h>
#include "sharpsl.h"
static DEFINE_SPINLOCK(corgi_ssp_lock);
static struct ssp_dev corgi_ssp_dev;
static struct ssp_state corgi_ssp_state;
static struct corgissp_machinfo *ssp_machinfo;
/*
* There are three devices connected to the SSP interface:
* 1. A touchscreen controller (TI ADS7846 compatible)
* 2. An LCD controller (with some Backlight functionality)
* 3. A battery monitoring IC (Maxim MAX1111)
*
* Each device uses a different speed/mode of communication.
*
* The touchscreen is very sensitive and the most frequently used
* so the port is left configured for this.
*
* Devices are selected using Chip Selects on GPIOs.
*/
/*
* ADS7846 Routines
*/
unsigned long corgi_ssp_ads7846_putget(ulong data)
{
unsigned long flag;
u32 ret = 0;
spin_lock_irqsave(&corgi_ssp_lock, flag);
if (ssp_machinfo->cs_ads7846 >= 0)
GPCR(ssp_machinfo->cs_ads7846) = GPIO_bit(ssp_machinfo->cs_ads7846);
ssp_write_word(&corgi_ssp_dev,data);
ssp_read_word(&corgi_ssp_dev, &ret);
if (ssp_machinfo->cs_ads7846 >= 0)
GPSR(ssp_machinfo->cs_ads7846) = GPIO_bit(ssp_machinfo->cs_ads7846);
spin_unlock_irqrestore(&corgi_ssp_lock, flag);
return ret;
}
/*
* NOTE: These functions should always be called in interrupt context
* and use the _lock and _unlock functions. They are very time sensitive.
*/
void corgi_ssp_ads7846_lock(void)
{
spin_lock(&corgi_ssp_lock);
if (ssp_machinfo->cs_ads7846 >= 0)
GPCR(ssp_machinfo->cs_ads7846) = GPIO_bit(ssp_machinfo->cs_ads7846);
}
void corgi_ssp_ads7846_unlock(void)
{
if (ssp_machinfo->cs_ads7846 >= 0)
GPSR(ssp_machinfo->cs_ads7846) = GPIO_bit(ssp_machinfo->cs_ads7846);
spin_unlock(&corgi_ssp_lock);
}
void corgi_ssp_ads7846_put(ulong data)
{
ssp_write_word(&corgi_ssp_dev,data);
}
unsigned long corgi_ssp_ads7846_get(void)
{
u32 ret = 0;
ssp_read_word(&corgi_ssp_dev, &ret);
return ret;
}
EXPORT_SYMBOL(corgi_ssp_ads7846_putget);
EXPORT_SYMBOL(corgi_ssp_ads7846_lock);
EXPORT_SYMBOL(corgi_ssp_ads7846_unlock);
EXPORT_SYMBOL(corgi_ssp_ads7846_put);
EXPORT_SYMBOL(corgi_ssp_ads7846_get);
/*
* LCD/Backlight Routines
*/
unsigned long corgi_ssp_dac_put(ulong data)
{
unsigned long flag, sscr1 = SSCR1_SPH;
u32 tmp;
spin_lock_irqsave(&corgi_ssp_lock, flag);
if (machine_is_spitz() || machine_is_akita() || machine_is_borzoi())
sscr1 = 0;
ssp_disable(&corgi_ssp_dev);
ssp_config(&corgi_ssp_dev, (SSCR0_Motorola | (SSCR0_DSS & 0x07 )), sscr1, 0, SSCR0_SerClkDiv(ssp_machinfo->clk_lcdcon));
ssp_enable(&corgi_ssp_dev);
if (ssp_machinfo->cs_lcdcon >= 0)
GPCR(ssp_machinfo->cs_lcdcon) = GPIO_bit(ssp_machinfo->cs_lcdcon);
ssp_write_word(&corgi_ssp_dev,data);
/* Read null data back from device to prevent SSP overflow */
ssp_read_word(&corgi_ssp_dev, &tmp);
if (ssp_machinfo->cs_lcdcon >= 0)
GPSR(ssp_machinfo->cs_lcdcon) = GPIO_bit(ssp_machinfo->cs_lcdcon);
ssp_disable(&corgi_ssp_dev);
ssp_config(&corgi_ssp_dev, (SSCR0_National | (SSCR0_DSS & 0x0b )), 0, 0, SSCR0_SerClkDiv(ssp_machinfo->clk_ads7846));
ssp_enable(&corgi_ssp_dev);
spin_unlock_irqrestore(&corgi_ssp_lock, flag);
return 0;
}
void corgi_ssp_lcdtg_send(u8 adrs, u8 data)
{
corgi_ssp_dac_put(((adrs & 0x07) << 5) | (data & 0x1f));
}
void corgi_ssp_blduty_set(int duty)
{
corgi_ssp_lcdtg_send(0x02,duty);
}
EXPORT_SYMBOL(corgi_ssp_lcdtg_send);
EXPORT_SYMBOL(corgi_ssp_blduty_set);
/*
* Max1111 Routines
*/
int corgi_ssp_max1111_get(ulong data)
{
unsigned long flag;
long voltage = 0, voltage1 = 0, voltage2 = 0;
spin_lock_irqsave(&corgi_ssp_lock, flag);
if (ssp_machinfo->cs_max1111 >= 0)
GPCR(ssp_machinfo->cs_max1111) = GPIO_bit(ssp_machinfo->cs_max1111);
ssp_disable(&corgi_ssp_dev);
ssp_config(&corgi_ssp_dev, (SSCR0_Motorola | (SSCR0_DSS & 0x07 )), 0, 0, SSCR0_SerClkDiv(ssp_machinfo->clk_max1111));
ssp_enable(&corgi_ssp_dev);
udelay(1);
/* TB1/RB1 */
ssp_write_word(&corgi_ssp_dev,data);
ssp_read_word(&corgi_ssp_dev, (u32*)&voltage1); /* null read */
/* TB12/RB2 */
ssp_write_word(&corgi_ssp_dev,0);
ssp_read_word(&corgi_ssp_dev, (u32*)&voltage1);
/* TB13/RB3*/
ssp_write_word(&corgi_ssp_dev,0);
ssp_read_word(&corgi_ssp_dev, (u32*)&voltage2);
ssp_disable(&corgi_ssp_dev);
ssp_config(&corgi_ssp_dev, (SSCR0_National | (SSCR0_DSS & 0x0b )), 0, 0, SSCR0_SerClkDiv(ssp_machinfo->clk_ads7846));
ssp_enable(&corgi_ssp_dev);
if (ssp_machinfo->cs_max1111 >= 0)
GPSR(ssp_machinfo->cs_max1111) = GPIO_bit(ssp_machinfo->cs_max1111);
spin_unlock_irqrestore(&corgi_ssp_lock, flag);
if (voltage1 & 0xc0 || voltage2 & 0x3f)
voltage = -1;
else
voltage = ((voltage1 << 2) & 0xfc) | ((voltage2 >> 6) & 0x03);
return voltage;
}
EXPORT_SYMBOL(corgi_ssp_max1111_get);
/*
* Support Routines
*/
void __init corgi_ssp_set_machinfo(struct corgissp_machinfo *machinfo)
{
ssp_machinfo = machinfo;
}
static int __init corgi_ssp_probe(struct platform_device *dev)
{
int ret;
/* Chip Select - Disable All */
if (ssp_machinfo->cs_lcdcon >= 0)
pxa_gpio_mode(ssp_machinfo->cs_lcdcon | GPIO_OUT | GPIO_DFLT_HIGH);
if (ssp_machinfo->cs_max1111 >= 0)
pxa_gpio_mode(ssp_machinfo->cs_max1111 | GPIO_OUT | GPIO_DFLT_HIGH);
if (ssp_machinfo->cs_ads7846 >= 0)
pxa_gpio_mode(ssp_machinfo->cs_ads7846 | GPIO_OUT | GPIO_DFLT_HIGH);
ret = ssp_init(&corgi_ssp_dev, ssp_machinfo->port, 0);
if (ret)
printk(KERN_ERR "Unable to register SSP handler!\n");
else {
ssp_disable(&corgi_ssp_dev);
ssp_config(&corgi_ssp_dev, (SSCR0_National | (SSCR0_DSS & 0x0b )), 0, 0, SSCR0_SerClkDiv(ssp_machinfo->clk_ads7846));
ssp_enable(&corgi_ssp_dev);
}
return ret;
}
static int corgi_ssp_remove(struct platform_device *dev)
{
ssp_exit(&corgi_ssp_dev);
return 0;
}
static int corgi_ssp_suspend(struct platform_device *dev, pm_message_t state)
{
ssp_flush(&corgi_ssp_dev);
ssp_save_state(&corgi_ssp_dev,&corgi_ssp_state);
return 0;
}
static int corgi_ssp_resume(struct platform_device *dev)
{
if (ssp_machinfo->cs_lcdcon >= 0)
GPSR(ssp_machinfo->cs_lcdcon) = GPIO_bit(ssp_machinfo->cs_lcdcon); /* High - Disable LCD Control/Timing Gen */
if (ssp_machinfo->cs_max1111 >= 0)
GPSR(ssp_machinfo->cs_max1111) = GPIO_bit(ssp_machinfo->cs_max1111); /* High - Disable MAX1111*/
if (ssp_machinfo->cs_ads7846 >= 0)
GPSR(ssp_machinfo->cs_ads7846) = GPIO_bit(ssp_machinfo->cs_ads7846); /* High - Disable ADS7846*/
ssp_restore_state(&corgi_ssp_dev,&corgi_ssp_state);
ssp_enable(&corgi_ssp_dev);
return 0;
}
static struct platform_driver corgissp_driver = {
.probe = corgi_ssp_probe,
.remove = corgi_ssp_remove,
.suspend = corgi_ssp_suspend,
.resume = corgi_ssp_resume,
.driver = {
.name = "corgi-ssp",
},
};
int __init corgi_ssp_init(void)
{
return platform_driver_register(&corgissp_driver);
}
arch_initcall(corgi_ssp_init);

2
arch/arm/mach-pxa/cpu-pxa.c → arch/arm/mach-pxa/cpufreq-pxa2xx.c
View file

@ -1,5 +1,5 @@
/*
* linux/arch/arm/mach-pxa/cpu-pxa.c
* linux/arch/arm/mach-pxa/cpufreq-pxa2xx.c
*
* Copyright (C) 2002,2003 Intrinsyc Software
*

258
arch/arm/mach-pxa/cpufreq-pxa3xx.c Normal file
View file

@ -0,0 +1,258 @@
/*
* linux/arch/arm/mach-pxa/cpufreq-pxa3xx.c
*
* Copyright (C) 2008 Marvell International Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/sched.h>
#include <linux/init.h>
#include <linux/cpufreq.h>
#include <mach/hardware.h>
#include <mach/pxa-regs.h>
#include <mach/pxa3xx-regs.h>
#include "generic.h"
#define HSS_104M (0)
#define HSS_156M (1)
#define HSS_208M (2)
#define HSS_312M (3)
#define SMCFS_78M (0)
#define SMCFS_104M (2)
#define SMCFS_208M (5)
#define SFLFS_104M (0)
#define SFLFS_156M (1)
#define SFLFS_208M (2)
#define SFLFS_312M (3)
#define XSPCLK_156M (0)
#define XSPCLK_NONE (3)
#define DMCFS_26M (0)
#define DMCFS_260M (3)
struct pxa3xx_freq_info {
unsigned int cpufreq_mhz;
unsigned int core_xl : 5;
unsigned int core_xn : 3;
unsigned int hss : 2;
unsigned int dmcfs : 2;
unsigned int smcfs : 3;
unsigned int sflfs : 2;
unsigned int df_clkdiv : 3;
int vcc_core; /* in mV */
int vcc_sram; /* in mV */
};
#define OP(cpufreq, _xl, _xn, _hss, _dmc, _smc, _sfl, _dfi, vcore, vsram) \
{ \
.cpufreq_mhz = cpufreq, \
.core_xl = _xl, \
.core_xn = _xn, \
.hss = HSS_##_hss##M, \
.dmcfs = DMCFS_##_dmc##M, \
.smcfs = SMCFS_##_smc##M, \
.sflfs = SFLFS_##_sfl##M, \
.df_clkdiv = _dfi, \
.vcc_core = vcore, \
.vcc_sram = vsram, \
}
static struct pxa3xx_freq_info pxa300_freqs[] = {
/* CPU XL XN HSS DMEM SMEM SRAM DFI VCC_CORE VCC_SRAM */
OP(104, 8, 1, 104, 260, 78, 104, 3, 1000, 1100), /* 104MHz */
OP(208, 16, 1, 104, 260, 104, 156, 2, 1000, 1100), /* 208MHz */
OP(416, 16, 2, 156, 260, 104, 208, 2, 1100, 1200), /* 416MHz */
OP(624, 24, 2, 208, 260, 208, 312, 3, 1375, 1400), /* 624MHz */
};
static struct pxa3xx_freq_info pxa320_freqs[] = {
/* CPU XL XN HSS DMEM SMEM SRAM DFI VCC_CORE VCC_SRAM */
OP(104, 8, 1, 104, 260, 78, 104, 3, 1000, 1100), /* 104MHz */
OP(208, 16, 1, 104, 260, 104, 156, 2, 1000, 1100), /* 208MHz */
OP(416, 16, 2, 156, 260, 104, 208, 2, 1100, 1200), /* 416MHz */
OP(624, 24, 2, 208, 260, 208, 312, 3, 1375, 1400), /* 624MHz */
OP(806, 31, 2, 208, 260, 208, 312, 3, 1400, 1400), /* 806MHz */
};
static unsigned int pxa3xx_freqs_num;
static struct pxa3xx_freq_info *pxa3xx_freqs;
static struct cpufreq_frequency_table *pxa3xx_freqs_table;
static int setup_freqs_table(struct cpufreq_policy *policy,
struct pxa3xx_freq_info *freqs, int num)
{
struct cpufreq_frequency_table *table;
int i;
table = kzalloc((num + 1) * sizeof(*table), GFP_KERNEL);
if (table == NULL)
return -ENOMEM;
for (i = 0; i < num; i++) {
table[i].index = i;
table[i].frequency = freqs[i].cpufreq_mhz * 1000;
}
table[num].frequency = i;
table[num].frequency = CPUFREQ_TABLE_END;
pxa3xx_freqs = freqs;
pxa3xx_freqs_num = num;
pxa3xx_freqs_table = table;
return cpufreq_frequency_table_cpuinfo(policy, table);
}
static void __update_core_freq(struct pxa3xx_freq_info *info)
{
uint32_t mask = ACCR_XN_MASK | ACCR_XL_MASK;
uint32_t accr = ACCR;
uint32_t xclkcfg;
accr &= ~(ACCR_XN_MASK | ACCR_XL_MASK | ACCR_XSPCLK_MASK);
accr |= ACCR_XN(info->core_xn) | ACCR_XL(info->core_xl);
/* No clock until core PLL is re-locked */
accr |= ACCR_XSPCLK(XSPCLK_NONE);
xclkcfg = (info->core_xn == 2) ? 0x3 : 0x2; /* turbo bit */
ACCR = accr;
__asm__("mcr p14, 0, %0, c6, c0, 0\n" : : "r"(xclkcfg));
while ((ACSR & mask) != (accr & mask))
cpu_relax();
}
static void __update_bus_freq(struct pxa3xx_freq_info *info)
{
uint32_t mask;
uint32_t accr = ACCR;
mask = ACCR_SMCFS_MASK | ACCR_SFLFS_MASK | ACCR_HSS_MASK |
ACCR_DMCFS_MASK;
accr &= ~mask;
accr |= ACCR_SMCFS(info->smcfs) | ACCR_SFLFS(info->sflfs) |
ACCR_HSS(info->hss) | ACCR_DMCFS(info->dmcfs);
ACCR = accr;
while ((ACSR & mask) != (accr & mask))
cpu_relax();
}
static int pxa3xx_cpufreq_verify(struct cpufreq_policy *policy)
{
return cpufreq_frequency_table_verify(policy, pxa3xx_freqs_table);
}
static unsigned int pxa3xx_cpufreq_get(unsigned int cpu)
{
return get_clk_frequency_khz(0);
}
static int pxa3xx_cpufreq_set(struct cpufreq_policy *policy,
unsigned int target_freq,
unsigned int relation)
{
struct pxa3xx_freq_info *next;
struct cpufreq_freqs freqs;
unsigned long flags;
int idx;
if (policy->cpu != 0)
return -EINVAL;
/* Lookup the next frequency */
if (cpufreq_frequency_table_target(policy, pxa3xx_freqs_table,
target_freq, relation, &idx))
return -EINVAL;
next = &pxa3xx_freqs[idx];
freqs.old = policy->cur;
freqs.new = next->cpufreq_mhz * 1000;
freqs.cpu = policy->cpu;
pr_debug("CPU frequency from %d MHz to %d MHz%s\n",
freqs.old / 1000, freqs.new / 1000,
(freqs.old == freqs.new) ? " (skipped)" : "");
if (freqs.old == target_freq)
return 0;
cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
local_irq_save(flags);
__update_core_freq(next);
__update_bus_freq(next);
local_irq_restore(flags);
cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
return 0;
}
static __init int pxa3xx_cpufreq_init(struct cpufreq_policy *policy)
{
int ret = -EINVAL;
/* set default policy and cpuinfo */
policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
policy->cpuinfo.min_freq = 104000;
policy->cpuinfo.max_freq = (cpu_is_pxa320()) ? 806000 : 624000;
policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */
policy->cur = policy->min = policy->max = get_clk_frequency_khz(0);
if (cpu_is_pxa300() || cpu_is_pxa310())
ret = setup_freqs_table(policy, ARRAY_AND_SIZE(pxa300_freqs));
if (cpu_is_pxa320())
ret = setup_freqs_table(policy, ARRAY_AND_SIZE(pxa320_freqs));
if (ret) {
pr_err("failed to setup frequency table\n");
return ret;
}
pr_info("CPUFREQ support for PXA3xx initialized\n");
return 0;
}
static struct cpufreq_driver pxa3xx_cpufreq_driver = {
.verify = pxa3xx_cpufreq_verify,
.target = pxa3xx_cpufreq_set,
.init = pxa3xx_cpufreq_init,
.get = pxa3xx_cpufreq_get,
.name = "pxa3xx-cpufreq",
};
static int __init cpufreq_init(void)
{
if (cpu_is_pxa3xx())
return cpufreq_register_driver(&pxa3xx_cpufreq_driver);
return 0;
}
module_init(cpufreq_init);
static void __exit cpufreq_exit(void)
{
cpufreq_unregister_driver(&pxa3xx_cpufreq_driver);
}
module_exit(cpufreq_exit);
MODULE_DESCRIPTION("CPU frequency scaling driver for PXA3xx");
MODULE_LICENSE("GPL");

1
arch/arm/mach-pxa/devices.h
View file

@ -32,5 +32,6 @@ extern struct platform_device pxa27x_device_pwm0;
extern struct platform_device pxa27x_device_pwm1;
extern struct platform_device pxa3xx_device_nand;
extern struct platform_device pxa3xx_device_i2c_power;
void __init pxa_register_device(struct platform_device *dev, void *data);

43
arch/arm/mach-pxa/e330.c Normal file
View file

@ -0,0 +1,43 @@
/*
* Hardware definitions for the Toshiba eseries PDAs
*
* Copyright (c) 2003 Ian Molton <spyro@f2s.com>
*
* This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <asm/setup.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
#include <mach/mfp-pxa25x.h>
#include <mach/hardware.h>
#include <mach/udc.h>
#include "generic.h"
#include "eseries.h"
static void __init e330_init(void)
{
pxa_set_udc_info(&e7xx_udc_mach_info);
}
MACHINE_START(E330, "Toshiba e330")
/* Maintainer: Ian Molton (spyro@f2s.com) */
.phys_io = 0x40000000,
.io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
.boot_params = 0xa0000100,
.map_io = pxa_map_io,
.init_irq = pxa25x_init_irq,
.fixup = eseries_fixup,
.init_machine = e330_init,
.timer = &pxa_timer,
MACHINE_END

43
arch/arm/mach-pxa/e350.c Normal file
View file

@ -0,0 +1,43 @@
/*
* Hardware definitions for the Toshiba eseries PDAs
*
* Copyright (c) 2003 Ian Molton <spyro@f2s.com>
*
* This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <asm/setup.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
#include <mach/mfp-pxa25x.h>
#include <mach/hardware.h>
#include <mach/udc.h>
#include "generic.h"
#include "eseries.h"
static void __init e350_init(void)
{
pxa_set_udc_info(&e7xx_udc_mach_info);
}
MACHINE_START(E350, "Toshiba e350")
/* Maintainer: Ian Molton (spyro@f2s.com) */
.phys_io = 0x40000000,
.io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
.boot_params = 0xa0000100,
.map_io = pxa_map_io,
.init_irq = pxa25x_init_irq,
.fixup = eseries_fixup,
.init_machine = e350_init,
.timer = &pxa_timer,
MACHINE_END

94
arch/arm/mach-pxa/e400.c Normal file
View file

@ -0,0 +1,94 @@
/*
* Hardware definitions for the Toshiba eseries PDAs
*
* Copyright (c) 2003 Ian Molton <spyro@f2s.com>
*
* This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <asm/setup.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
#include <mach/pxa-regs.h>
#include <mach/mfp-pxa25x.h>
#include <mach/hardware.h>
#include <mach/pxafb.h>
#include <mach/udc.h>
#include "generic.h"
#include "eseries.h"
/* ------------------------ E400 LCD definitions ------------------------ */
static struct pxafb_mode_info e400_pxafb_mode_info = {
.pixclock = 140703,
.xres = 240,
.yres = 320,
.bpp = 16,
.hsync_len = 4,
.left_margin = 28,
.right_margin = 8,
.vsync_len = 3,
.upper_margin = 5,
.lower_margin = 6,
.sync = 0,
};
static struct pxafb_mach_info e400_pxafb_mach_info = {
.modes = &e400_pxafb_mode_info,
.num_modes = 1,
.lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
.lccr3 = 0,
.pxafb_backlight_power = NULL,
};
/* ------------------------ E400 MFP config ----------------------------- */
static unsigned long e400_pin_config[] __initdata = {
/* Chip selects */
GPIO15_nCS_1, /* CS1 - Flash */
GPIO80_nCS_4, /* CS4 - TMIO */
/* Clocks */
GPIO12_32KHz,
/* BTUART */
GPIO42_BTUART_RXD,
GPIO43_BTUART_TXD,
GPIO44_BTUART_CTS,
GPIO45_GPIO, /* Used by TMIO for #SUSPEND */
/* wakeup */
GPIO0_GPIO | WAKEUP_ON_EDGE_RISE,
};
/* ---------------------------------------------------------------------- */
static void __init e400_init(void)
{
pxa2xx_mfp_config(ARRAY_AND_SIZE(e400_pin_config));
set_pxa_fb_info(&e400_pxafb_mach_info);
pxa_set_udc_info(&e7xx_udc_mach_info);
}
MACHINE_START(E400, "Toshiba e400")
/* Maintainer: Ian Molton (spyro@f2s.com) */
.phys_io = 0x40000000,
.io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
.boot_params = 0xa0000100,
.map_io = pxa_map_io,
.init_irq = pxa25x_init_irq,
.fixup = eseries_fixup,
.init_machine = e400_init,
.timer = &pxa_timer,
MACHINE_END

56
arch/arm/mach-pxa/e400_lcd.c
View file

@ -1,56 +0,0 @@
/*
* e400_lcd.c
*
* (c) 2005 Ian Molton <spyro@f2s.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>
#include <asm/mach-types.h>
#include <mach/pxa-regs.h>
#include <mach/pxafb.h>
static struct pxafb_mode_info e400_pxafb_mode_info = {
.pixclock = 140703,
.xres = 240,
.yres = 320,
.bpp = 16,
.hsync_len = 4,
.left_margin = 28,
.right_margin = 8,
.vsync_len = 3,
.upper_margin = 5,
.lower_margin = 6,
.sync = 0,
};
static struct pxafb_mach_info e400_pxafb_mach_info = {
.modes = &e400_pxafb_mode_info,
.num_modes = 1,
.lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
.lccr3 = 0,
.pxafb_backlight_power = NULL,
};
static int __init e400_lcd_init(void)
{
if (!machine_is_e400())
return -ENODEV;
set_pxa_fb_info(&e400_pxafb_mach_info);
return 0;
}
module_init(e400_lcd_init);
MODULE_AUTHOR("Ian Molton <spyro@f2s.com>");
MODULE_DESCRIPTION("e400 lcd driver");
MODULE_LICENSE("GPLv2");

169
arch/arm/mach-pxa/e740.c Normal file
View file

@ -0,0 +1,169 @@
/*
* Hardware definitions for the Toshiba eseries PDAs
*
* Copyright (c) 2003 Ian Molton <spyro@f2s.com>
*
* This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/fb.h>
#include <video/w100fb.h>
#include <asm/setup.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
#include <mach/mfp-pxa25x.h>
#include <mach/hardware.h>
#include <mach/udc.h>
#include "generic.h"
#include "eseries.h"
/* ------------------------ e740 video support --------------------------- */
static struct w100_gen_regs e740_lcd_regs = {
.lcd_format = 0x00008023,
.lcdd_cntl1 = 0x0f000000,
.lcdd_cntl2 = 0x0003ffff,
.genlcd_cntl1 = 0x00ffff03,
.genlcd_cntl2 = 0x003c0f03,
.genlcd_cntl3 = 0x000143aa,
};
static struct w100_mode e740_lcd_mode = {
.xres = 240,
.yres = 320,
.left_margin = 20,
.right_margin = 28,
.upper_margin = 9,
.lower_margin = 8,
.crtc_ss = 0x80140013,
.crtc_ls = 0x81150110,
.crtc_gs = 0x80050005,
.crtc_vpos_gs = 0x000a0009,
.crtc_rev = 0x0040010a,
.crtc_dclk = 0xa906000a,
.crtc_gclk = 0x80050108,
.crtc_goe = 0x80050108,
.pll_freq = 57,
.pixclk_divider = 4,
.pixclk_divider_rotated = 4,
.pixclk_src = CLK_SRC_XTAL,
.sysclk_divider = 1,
.sysclk_src = CLK_SRC_PLL,
.crtc_ps1_active = 0x41060010,
};
static struct w100_gpio_regs e740_w100_gpio_info = {
.init_data1 = 0x21002103,
.gpio_dir1 = 0xffffdeff,
.gpio_oe1 = 0x03c00643,
.init_data2 = 0x003f003f,
.gpio_dir2 = 0xffffffff,
.gpio_oe2 = 0x000000ff,
};
static struct w100fb_mach_info e740_fb_info = {
.modelist = &e740_lcd_mode,
.num_modes = 1,
.regs = &e740_lcd_regs,
.gpio = &e740_w100_gpio_info,
.xtal_freq = 14318000,
.xtal_dbl = 1,
};
static struct resource e740_fb_resources[] = {
[0] = {
.start = 0x0c000000,
.end = 0x0cffffff,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device e740_fb_device = {
.name = "w100fb",
.id = -1,
.dev = {
.platform_data = &e740_fb_info,
},
.num_resources = ARRAY_SIZE(e740_fb_resources),
.resource = e740_fb_resources,
};
/* --------------------------- MFP Pin config -------------------------- */
static unsigned long e740_pin_config[] __initdata = {
/* Chip selects */
GPIO15_nCS_1, /* CS1 - Flash */
GPIO79_nCS_3, /* CS3 - IMAGEON */
GPIO80_nCS_4, /* CS4 - TMIO */
/* Clocks */
GPIO12_32KHz,
/* BTUART */
GPIO42_BTUART_RXD,
GPIO43_BTUART_TXD,
GPIO44_BTUART_CTS,
GPIO45_GPIO, /* Used by TMIO for #SUSPEND */
/* PC Card */
GPIO8_GPIO, /* CD0 */
GPIO44_GPIO, /* CD1 */
GPIO11_GPIO, /* IRQ0 */
GPIO6_GPIO, /* IRQ1 */
GPIO27_GPIO, /* RST0 */
GPIO24_GPIO, /* RST1 */
GPIO20_GPIO, /* PWR0 */
GPIO23_GPIO, /* PWR1 */
GPIO48_nPOE,
GPIO49_nPWE,
GPIO50_nPIOR,
GPIO51_nPIOW,
GPIO52_nPCE_1,
GPIO53_nPCE_2,
GPIO54_nPSKTSEL,
GPIO55_nPREG,
GPIO56_nPWAIT,
GPIO57_nIOIS16,
/* wakeup */
GPIO0_GPIO | WAKEUP_ON_EDGE_RISE,
};
/* ----------------------------------------------------------------------- */
static struct platform_device *devices[] __initdata = {
&e740_fb_device,
};
static void __init e740_init(void)
{
pxa2xx_mfp_config(ARRAY_AND_SIZE(e740_pin_config));
platform_add_devices(devices, ARRAY_SIZE(devices));
pxa_set_udc_info(&e7xx_udc_mach_info);
}
MACHINE_START(E740, "Toshiba e740")
/* Maintainer: Ian Molton (spyro@f2s.com) */
.phys_io = 0x40000000,
.io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
.boot_params = 0xa0000100,
.map_io = pxa_map_io,
.init_irq = pxa25x_init_irq,
.fixup = eseries_fixup,
.init_machine = e740_init,
.timer = &pxa_timer,
MACHINE_END

123
arch/arm/mach-pxa/e740_lcd.c
View file

@ -1,123 +0,0 @@
/* e740_lcd.c
*
* This file contains the definitions for the LCD timings and functions
* to control the LCD power / frontlighting via the w100fb driver.
*
* (c) 2005 Ian Molton <spyro@f2s.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/module.h>
#include <linux/device.h>
#include <linux/fb.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <asm/mach-types.h>
#include <video/w100fb.h>
/*
**potential** shutdown routine - to be investigated
devmem2 0x0c010528 w 0xff3fff00
devmem2 0x0c010190 w 0x7FFF8000
devmem2 0x0c0101b0 w 0x00FF0000
devmem2 0x0c01008c w 0x00000000
devmem2 0x0c010080 w 0x000000bf
devmem2 0x0c010098 w 0x00000015
devmem2 0x0c010088 w 0x4b000204
devmem2 0x0c010098 w 0x0000001d
*/
static struct w100_gen_regs e740_lcd_regs = {
.lcd_format = 0x00008023,
.lcdd_cntl1 = 0x0f000000,
.lcdd_cntl2 = 0x0003ffff,
.genlcd_cntl1 = 0x00ffff03,
.genlcd_cntl2 = 0x003c0f03,
.genlcd_cntl3 = 0x000143aa,
};
static struct w100_mode e740_lcd_mode = {
.xres = 240,
.yres = 320,
.left_margin = 20,
.right_margin = 28,
.upper_margin = 9,
.lower_margin = 8,
.crtc_ss = 0x80140013,
.crtc_ls = 0x81150110,
.crtc_gs = 0x80050005,
.crtc_vpos_gs = 0x000a0009,
.crtc_rev = 0x0040010a,
.crtc_dclk = 0xa906000a,
.crtc_gclk = 0x80050108,
.crtc_goe = 0x80050108,
.pll_freq = 57,
.pixclk_divider = 4,
.pixclk_divider_rotated = 4,
.pixclk_src = CLK_SRC_XTAL,
.sysclk_divider = 1,
.sysclk_src = CLK_SRC_PLL,
.crtc_ps1_active = 0x41060010,
};
static struct w100_gpio_regs e740_w100_gpio_info = {
.init_data1 = 0x21002103,
.gpio_dir1 = 0xffffdeff,
.gpio_oe1 = 0x03c00643,
.init_data2 = 0x003f003f,
.gpio_dir2 = 0xffffffff,
.gpio_oe2 = 0x000000ff,
};
static struct w100fb_mach_info e740_fb_info = {
.modelist = &e740_lcd_mode,
.num_modes = 1,
.regs = &e740_lcd_regs,
.gpio = &e740_w100_gpio_info,
.xtal_freq = 14318000,
.xtal_dbl = 1,
};
static struct resource e740_fb_resources[] = {
[0] = {
.start = 0x0c000000,
.end = 0x0cffffff,
.flags = IORESOURCE_MEM,
},
};
/* ----------------------- device declarations -------------------------- */
static struct platform_device e740_fb_device = {
.name = "w100fb",
.id = -1,
.dev = {
.platform_data = &e740_fb_info,
},
.num_resources = ARRAY_SIZE(e740_fb_resources),
.resource = e740_fb_resources,
};
static int e740_lcd_init(void)
{
int ret;
if (!machine_is_e740())
return -ENODEV;
return platform_device_register(&e740_fb_device);
}
module_init(e740_lcd_init);
MODULE_AUTHOR("Ian Molton <spyro@f2s.com>");
MODULE_DESCRIPTION("e740 lcd driver");
MODULE_LICENSE("GPLv2");

69
arch/arm/mach-pxa/e750_lcd.c → arch/arm/mach-pxa/e750.c
View file

@ -1,26 +1,36 @@
/* e750_lcd.c
/*
* Hardware definitions for the Toshiba eseries PDAs
*
* This file contains the definitions for the LCD timings and functions
* to control the LCD power / frontlighting via the w100fb driver.
* Copyright (c) 2003 Ian Molton <spyro@f2s.com>
*
* (c) 2005 Ian Molton <spyro@f2s.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
* This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/fb.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <asm/mach-types.h>
#include <linux/fb.h>
#include <video/w100fb.h>
#include <asm/setup.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
#include <mach/mfp-pxa25x.h>
#include <mach/hardware.h>
#include <mach/udc.h>
#include "generic.h"
#include "eseries.h"
/* ---------------------- E750 LCD definitions -------------------- */
static struct w100_gen_regs e750_lcd_regs = {
.lcd_format = 0x00008003,
.lcdd_cntl1 = 0x00000000,
@ -54,7 +64,6 @@ static struct w100_mode e750_lcd_mode = {
.sysclk_src = CLK_SRC_PLL,
};
static struct w100_gpio_regs e750_w100_gpio_info = {
.init_data1 = 0x01192f1b,
.gpio_dir1 = 0xd5ffdeff,
@ -81,9 +90,6 @@ static struct resource e750_fb_resources[] = {
},
};
/* ----------------------- device declarations -------------------------- */
static struct platform_device e750_fb_device = {
.name = "w100fb",
.id = -1,
@ -94,16 +100,27 @@ static struct platform_device e750_fb_device = {
.resource = e750_fb_resources,
};
static int e750_lcd_init(void)
{
if (!machine_is_e750())
return -ENODEV;
/* ----------------------------------------------------------------------- */
return platform_device_register(&e750_fb_device);
static struct platform_device *devices[] __initdata = {
&e750_fb_device,
};
static void __init e750_init(void)
{
platform_add_devices(devices, ARRAY_SIZE(devices));
pxa_set_udc_info(&e7xx_udc_mach_info);
}
module_init(e750_lcd_init);
MACHINE_START(E750, "Toshiba e750")
/* Maintainer: Ian Molton (spyro@f2s.com) */
.phys_io = 0x40000000,
.io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
.boot_params = 0xa0000100,
.map_io = pxa_map_io,
.init_irq = pxa25x_init_irq,
.fixup = eseries_fixup,
.init_machine = e750_init,
.timer = &pxa_timer,
MACHINE_END
MODULE_AUTHOR("Ian Molton <spyro@f2s.com>");
MODULE_DESCRIPTION("e750 lcd driver");
MODULE_LICENSE("GPLv2");

81
arch/arm/mach-pxa/e800_lcd.c → arch/arm/mach-pxa/e800.c
View file

@ -1,26 +1,37 @@
/* e800_lcd.c
/*
* Hardware definitions for the Toshiba eseries PDAs
*
* This file contains the definitions for the LCD timings and functions
* to control the LCD power / frontlighting via the w100fb driver.
* Copyright (c) 2003 Ian Molton <spyro@f2s.com>
*
* (c) 2005 Ian Molton <spyro@f2s.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
* This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/fb.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <asm/mach-types.h>
#include <linux/fb.h>
#include <video/w100fb.h>
#include <asm/setup.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
#include <mach/mfp-pxa25x.h>
#include <mach/hardware.h>
#include <mach/eseries-gpio.h>
#include <mach/udc.h>
#include "generic.h"
#include "eseries.h"
/* ------------------------ e800 LCD definitions ------------------------- */
static struct w100_gen_regs e800_lcd_regs = {
.lcd_format = 0x00008003,
.lcdd_cntl1 = 0x02a00000,
@ -71,8 +82,8 @@ static struct w100_mode e800_lcd_mode[2] = {
.crtc_goe = 0x80cc0015,
.crtc_ps1_active = 0x00000000,
.pll_freq = 100,
.pixclk_divider = 6, /* Wince uses 14 which gives a 7MHz pclk. */
.pixclk_divider_rotated = 6, /* we want a 14MHz one (much nicer to look at) */
.pixclk_divider = 6, /* Wince uses 14 which gives a */
.pixclk_divider_rotated = 6, /* 7MHz Pclk. We use a 14MHz one */
.pixclk_src = CLK_SRC_PLL,
.sysclk_divider = 0,
.sysclk_src = CLK_SRC_PLL,
@ -131,9 +142,6 @@ static struct resource e800_fb_resources[] = {
},
};
/* ----------------------- device declarations -------------------------- */
static struct platform_device e800_fb_device = {
.name = "w100fb",
.id = -1,
@ -144,16 +152,35 @@ static struct platform_device e800_fb_device = {
.resource = e800_fb_resources,
};
static int e800_lcd_init(void)
{
if (!machine_is_e800())
return -ENODEV;
/* --------------------------- UDC definitions --------------------------- */
return platform_device_register(&e800_fb_device);
static struct pxa2xx_udc_mach_info e800_udc_mach_info = {
.gpio_vbus = GPIO_E800_USB_DISC,
.gpio_pullup = GPIO_E800_USB_PULLUP,
.gpio_pullup_inverted = 1
};
/* ----------------------------------------------------------------------- */
static struct platform_device *devices[] __initdata = {
&e800_fb_device,
};
static void __init e800_init(void)
{
platform_add_devices(devices, ARRAY_SIZE(devices));
pxa_set_udc_info(&e800_udc_mach_info);
}
module_init(e800_lcd_init);
MACHINE_START(E800, "Toshiba e800")
/* Maintainer: Ian Molton (spyro@f2s.com) */
.phys_io = 0x40000000,
.io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
.boot_params = 0xa0000100,
.map_io = pxa_map_io,
.init_irq = pxa25x_init_irq,
.fixup = eseries_fixup,
.init_machine = e800_init,
.timer = &pxa_timer,
MACHINE_END
MODULE_AUTHOR("Ian Molton <spyro@f2s.com>");
MODULE_DESCRIPTION("e800 lcd driver");
MODULE_LICENSE("GPLv2");

5
arch/arm/mach-pxa/em-x270.c
View file

@ -373,10 +373,6 @@ static inline void em_x270_init_nand(void) {}
#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
static int em_x270_ohci_init(struct device *dev)
{
/* Set the Power Control Polarity Low */
UHCHR = (UHCHR | UHCHR_PCPL) &
~(UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE);
/* enable port 2 transiever */
UP2OCR = UP2OCR_HXS | UP2OCR_HXOE;
@ -385,6 +381,7 @@ static int em_x270_ohci_init(struct device *dev)
static struct pxaohci_platform_data em_x270_ohci_platform_data = {
.port_mode = PMM_PERPORT_MODE,
.flags = ENABLE_PORT1 | ENABLE_PORT2 | POWER_CONTROL_LOW,
.init = em_x270_ohci_init,
};

157
arch/arm/mach-pxa/eseries.c
View file

@ -19,68 +19,13 @@
#include <mach/mfp-pxa25x.h>
#include <mach/hardware.h>
#include <mach/eseries-gpio.h>
#include <mach/udc.h>
#include "generic.h"
static unsigned long e740_pin_config[] __initdata = {
/* Chip selects */
GPIO15_nCS_1, /* CS1 - Flash */
GPIO79_nCS_3, /* CS3 - IMAGEON */
GPIO80_nCS_4, /* CS4 - TMIO */
/* Clocks */
GPIO12_32KHz,
/* BTUART */
GPIO42_BTUART_RXD,
GPIO43_BTUART_TXD,
GPIO44_BTUART_CTS,
GPIO45_GPIO, /* Used by TMIO for #SUSPEND */
/* PC Card */
GPIO8_GPIO, /* CD0 */
GPIO44_GPIO, /* CD1 */
GPIO11_GPIO, /* IRQ0 */
GPIO6_GPIO, /* IRQ1 */
GPIO27_GPIO, /* RST0 */
GPIO24_GPIO, /* RST1 */
GPIO20_GPIO, /* PWR0 */
GPIO23_GPIO, /* PWR1 */
GPIO48_nPOE,
GPIO49_nPWE,
GPIO50_nPIOR,
GPIO51_nPIOW,
GPIO52_nPCE_1,
GPIO53_nPCE_2,
GPIO54_nPSKTSEL,
GPIO55_nPREG,
GPIO56_nPWAIT,
GPIO57_nIOIS16,
/* wakeup */
GPIO0_GPIO | WAKEUP_ON_EDGE_RISE,
};
static unsigned long e400_pin_config[] __initdata = {
/* Chip selects */
GPIO15_nCS_1, /* CS1 - Flash */
GPIO80_nCS_4, /* CS4 - TMIO */
/* Clocks */
GPIO12_32KHz,
/* BTUART */
GPIO42_BTUART_RXD,
GPIO43_BTUART_TXD,
GPIO44_BTUART_CTS,
GPIO45_GPIO, /* Used by TMIO for #SUSPEND */
/* wakeup */
GPIO0_GPIO | WAKEUP_ON_EDGE_RISE,
};
/* Only e800 has 128MB RAM */
static void __init eseries_fixup(struct machine_desc *desc,
void __init eseries_fixup(struct machine_desc *desc,
struct tag *tags, char **cmdline, struct meminfo *mi)
{
mi->nr_banks=1;
@ -92,95 +37,9 @@ static void __init eseries_fixup(struct machine_desc *desc,
mi->bank[0].size = (64*1024*1024);
}
static void __init e740_init(void)
{
pxa2xx_mfp_config(ARRAY_AND_SIZE(e740_pin_config));
}
static void __init e400_init(void)
{
pxa2xx_mfp_config(ARRAY_AND_SIZE(e400_pin_config));
}
/* e-series machine definitions */
#ifdef CONFIG_MACH_E330
MACHINE_START(E330, "Toshiba e330")
/* Maintainer: Ian Molton (spyro@f2s.com) */
.phys_io = 0x40000000,
.io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
.boot_params = 0xa0000100,
.map_io = pxa_map_io,
.init_irq = pxa25x_init_irq,
.fixup = eseries_fixup,
.timer = &pxa_timer,
MACHINE_END
#endif
#ifdef CONFIG_MACH_E350
MACHINE_START(E350, "Toshiba e350")
/* Maintainer: Ian Molton (spyro@f2s.com) */
.phys_io = 0x40000000,
.io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
.boot_params = 0xa0000100,
.map_io = pxa_map_io,
.init_irq = pxa25x_init_irq,
.fixup = eseries_fixup,
.timer = &pxa_timer,
MACHINE_END
#endif
#ifdef CONFIG_MACH_E740
MACHINE_START(E740, "Toshiba e740")
/* Maintainer: Ian Molton (spyro@f2s.com) */
.phys_io = 0x40000000,
.io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
.boot_params = 0xa0000100,
.map_io = pxa_map_io,
.init_irq = pxa25x_init_irq,
.fixup = eseries_fixup,
.init_machine = e740_init,
.timer = &pxa_timer,
MACHINE_END
#endif
#ifdef CONFIG_MACH_E750
MACHINE_START(E750, "Toshiba e750")
/* Maintainer: Ian Molton (spyro@f2s.com) */
.phys_io = 0x40000000,
.io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
.boot_params = 0xa0000100,
.map_io = pxa_map_io,
.init_irq = pxa25x_init_irq,
.fixup = eseries_fixup,
.timer = &pxa_timer,
MACHINE_END
#endif
#ifdef CONFIG_MACH_E400
MACHINE_START(E400, "Toshiba e400")
/* Maintainer: Ian Molton (spyro@f2s.com) */
.phys_io = 0x40000000,
.io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
.boot_params = 0xa0000100,
.map_io = pxa_map_io,
.init_irq = pxa25x_init_irq,
.fixup = eseries_fixup,
.init_machine = e400_init,
.timer = &pxa_timer,
MACHINE_END
#endif
#ifdef CONFIG_MACH_E800
MACHINE_START(E800, "Toshiba e800")
/* Maintainer: Ian Molton (spyro@f2s.com) */
.phys_io = 0x40000000,
.io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
.boot_params = 0xa0000100,
.map_io = pxa_map_io,
.init_irq = pxa25x_init_irq,
.fixup = eseries_fixup,
.timer = &pxa_timer,
MACHINE_END
#endif
struct pxa2xx_udc_mach_info e7xx_udc_mach_info = {
.gpio_vbus = GPIO_E7XX_USB_DISC,
.gpio_pullup = GPIO_E7XX_USB_PULLUP,
.gpio_pullup_inverted = 1
};

4
arch/arm/mach-pxa/eseries.h Normal file
View file

@ -0,0 +1,4 @@
void __init eseries_fixup(struct machine_desc *desc,
struct tag *tags, char **cmdline, struct meminfo *mi);
extern struct pxa2xx_udc_mach_info e7xx_udc_mach_info;

57
arch/arm/mach-pxa/eseries_udc.c
View file

@ -1,57 +0,0 @@
/*
* UDC functions for the Toshiba e-series PDAs
*
* Copyright (c) Ian Molton 2003
*
* This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/device.h>
#include <mach/udc.h>
#include <mach/eseries-gpio.h>
#include <mach/hardware.h>
#include <mach/pxa-regs.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
#include <asm/mach/map.h>
#include <asm/domain.h>
/* local PXA generic code */
#include "generic.h"
static struct pxa2xx_udc_mach_info e7xx_udc_mach_info = {
.gpio_vbus = GPIO_E7XX_USB_DISC,
.gpio_pullup = GPIO_E7XX_USB_PULLUP,
.gpio_pullup_inverted = 1
};
static struct pxa2xx_udc_mach_info e800_udc_mach_info = {
.gpio_vbus = GPIO_E800_USB_DISC,
.gpio_pullup = GPIO_E800_USB_PULLUP,
.gpio_pullup_inverted = 1
};
static int __init eseries_udc_init(void)
{
if (machine_is_e330() || machine_is_e350() ||
machine_is_e740() || machine_is_e750() ||
machine_is_e400())
pxa_set_udc_info(&e7xx_udc_mach_info);
else if (machine_is_e800())
pxa_set_udc_info(&e800_udc_mach_info);
return 0;
}
module_init(eseries_udc_init);
MODULE_AUTHOR("Ian Molton <spyro@f2s.com>");
MODULE_DESCRIPTION("eseries UDC support");
MODULE_LICENSE("GPLv2");

9
arch/arm/mach-pxa/generic.c
View file

@ -46,7 +46,7 @@ void clear_reset_status(unsigned int mask)
*/
unsigned int get_clk_frequency_khz(int info)
{
if (cpu_is_pxa21x() || cpu_is_pxa25x())
if (cpu_is_pxa25x())
return pxa25x_get_clk_frequency_khz(info);
else if (cpu_is_pxa27x())
return pxa27x_get_clk_frequency_khz(info);
@ -60,7 +60,7 @@ EXPORT_SYMBOL(get_clk_frequency_khz);
*/
unsigned int get_memclk_frequency_10khz(void)
{
if (cpu_is_pxa21x() || cpu_is_pxa25x())
if (cpu_is_pxa25x())
return pxa25x_get_memclk_frequency_10khz();
else if (cpu_is_pxa27x())
return pxa27x_get_memclk_frequency_10khz();
@ -88,11 +88,6 @@ static struct map_desc standard_io_desc[] __initdata = {
.pfn = __phys_to_pfn(0x48000000),
.length = 0x00200000,
.type = MT_DEVICE
}, { /* USB host */
.virtual = 0xf8000000,
.pfn = __phys_to_pfn(0x4c000000),
.length = 0x00100000,
.type = MT_DEVICE
}, { /* Camera */
.virtual = 0xfa000000,
.pfn = __phys_to_pfn(0x50000000),

1
arch/arm/mach-pxa/generic.h
View file

@ -65,4 +65,5 @@ static inline void pxa3xx_clear_reset_status(unsigned int mask) {}
extern struct sysdev_class pxa_irq_sysclass;
extern struct sysdev_class pxa_gpio_sysclass;
extern struct sysdev_class pxa2xx_mfp_sysclass;
extern struct sysdev_class pxa3xx_mfp_sysclass;

2
arch/arm/mach-pxa/gpio.c
View file

@ -275,7 +275,7 @@ static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
loop = 1;
n = PXA_GPIO_IRQ_BASE + bit;
desc_handle_irq(n, irq_desc + n);
generic_handle_irq(n);
bit = find_next_bit(gedr, GEDR_BITS, bit + 1);
}

100
arch/arm/mach-pxa/gumstix.c
View file

@ -20,8 +20,12 @@
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/gpio.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <asm/setup.h>
#include <asm/memory.h>
@ -40,7 +44,7 @@
#include <mach/pxa-regs.h>
#include <mach/pxa2xx-regs.h>
#include <mach/pxa2xx-gpio.h>
#include <mach/mfp-pxa25x.h>
#include "generic.h"
@ -85,21 +89,8 @@ static struct platform_device *devices[] __initdata = {
};
#ifdef CONFIG_MMC_PXA
static struct pxamci_platform_data gumstix_mci_platform_data;
static int gumstix_mci_init(struct device *dev, irq_handler_t detect_int,
void *data)
{
pxa_gpio_mode(GPIO6_MMCCLK_MD);
pxa_gpio_mode(GPIO53_MMCCLK_MD);
pxa_gpio_mode(GPIO8_MMCCS0_MD);
return 0;
}
static struct pxamci_platform_data gumstix_mci_platform_data = {
.ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
.init = gumstix_mci_init,
};
static void __init gumstix_mmc_init(void)
@ -109,11 +100,11 @@ static void __init gumstix_mmc_init(void)
#else
static void __init gumstix_mmc_init(void)
{
printk(KERN_INFO "Gumstix mmc disabled\n");
pr_debug("Gumstix mmc disabled\n");
}
#endif
#ifdef CONFIG_USB_GADGET_PXA2XX
#ifdef CONFIG_USB_GADGET_PXA25X
static struct pxa2xx_udc_mach_info gumstix_udc_info __initdata = {
.gpio_vbus = GPIO_GUMSTIX_USB_GPIOn,
.gpio_pullup = GPIO_GUMSTIX_USB_GPIOx,
@ -126,12 +117,87 @@ static void __init gumstix_udc_init(void)
#else
static void gumstix_udc_init(void)
{
printk(KERN_INFO "Gumstix udc is disabled\n");
pr_debug("Gumstix udc is disabled\n");
}
#endif
#ifdef CONFIG_BT
/* Normally, the bootloader would have enabled this 32kHz clock but many
** boards still have u-boot 1.1.4 so we check if it has been turned on and
** if not, we turn it on with a warning message. */
static void gumstix_setup_bt_clock(void)
{
int timeout = 500;
if (!(OSCC & OSCC_OOK))
pr_warning("32kHz clock was not on. Bootloader may need to "
"be updated\n");
else
return;
OSCC |= OSCC_OON;
do {
if (OSCC & OSCC_OOK)
break;
udelay(1);
} while (--timeout);
if (!timeout)
pr_err("Failed to start 32kHz clock\n");
}
static void __init gumstix_bluetooth_init(void)
{
int err;
gumstix_setup_bt_clock();
err = gpio_request(GPIO_GUMSTIX_BTRESET, "BTRST");
if (err) {
pr_err("gumstix: failed request gpio for bluetooth reset\n");
return;
}
err = gpio_direction_output(GPIO_GUMSTIX_BTRESET, 1);
if (err) {
pr_err("gumstix: can't reset bluetooth\n");
return;
}
gpio_set_value(GPIO_GUMSTIX_BTRESET, 0);
udelay(100);
gpio_set_value(GPIO_GUMSTIX_BTRESET, 1);
}
#else
static void gumstix_bluetooth_init(void)
{
pr_debug("Gumstix Bluetooth is disabled\n");
}
#endif
static unsigned long gumstix_pin_config[] __initdata = {
GPIO12_32KHz,
/* BTUART */
GPIO42_HWUART_RXD,
GPIO43_HWUART_TXD,
GPIO44_HWUART_CTS,
GPIO45_HWUART_RTS,
/* MMC */
GPIO6_MMC_CLK,
GPIO53_MMC_CLK,
GPIO8_MMC_CS0,
/* these are used by AM200EPD */
GPIO51_GPIO,
GPIO49_GPIO,
GPIO48_GPIO,
GPIO32_GPIO,
GPIO17_GPIO,
GPIO16_GPIO,
};
static void __init gumstix_init(void)
{
pxa2xx_mfp_config(ARRAY_AND_SIZE(gumstix_pin_config));
gumstix_bluetooth_init();
gumstix_udc_init();
gumstix_mmc_init();
(void) platform_add_devices(devices, ARRAY_SIZE(devices));

78
arch/arm/mach-pxa/idp.c
View file

@ -32,7 +32,7 @@
#include <asm/mach/map.h>
#include <mach/pxa-regs.h>
#include <mach/pxa2xx-gpio.h>
#include <mach/mfp-pxa25x.h>
#include <mach/idp.h>
#include <mach/pxafb.h>
#include <mach/bitfield.h>
@ -46,6 +46,47 @@
* - Ethernet interrupt
*/
static unsigned long idp_pin_config[] __initdata = {
/* LCD */
GPIO58_LCD_LDD_0,
GPIO59_LCD_LDD_1,
GPIO60_LCD_LDD_2,
GPIO61_LCD_LDD_3,
GPIO62_LCD_LDD_4,
GPIO63_LCD_LDD_5,
GPIO64_LCD_LDD_6,
GPIO65_LCD_LDD_7,
GPIO66_LCD_LDD_8,
GPIO67_LCD_LDD_9,
GPIO68_LCD_LDD_10,
GPIO69_LCD_LDD_11,
GPIO70_LCD_LDD_12,
GPIO71_LCD_LDD_13,
GPIO72_LCD_LDD_14,
GPIO73_LCD_LDD_15,
GPIO74_LCD_FCLK,
GPIO75_LCD_LCLK,
GPIO76_LCD_PCLK,
/* BTUART */
GPIO42_BTUART_RXD,
GPIO43_BTUART_TXD,
GPIO44_BTUART_CTS,
GPIO45_BTUART_RTS,
/* STUART */
GPIO46_STUART_RXD,
GPIO47_STUART_TXD,
/* MMC */
GPIO6_MMC_CLK,
GPIO8_MMC_CS0,
/* Ethernet */
GPIO33_nCS_5, /* Ethernet CS */
GPIO4_GPIO, /* Ethernet IRQ */
};
static struct resource smc91x_resources[] = {
[0] = {
.start = (IDP_ETH_PHYS + 0x300),
@ -121,44 +162,28 @@ static struct pxafb_mach_info sharp_lm8v31 = {
.num_modes = 1,
.cmap_inverse = 0,
.cmap_static = 0,
.lccr0 = LCCR0_SDS,
.lccr3 = LCCR3_PCP | LCCR3_Acb(255),
.lcd_conn = LCD_COLOR_DSTN_16BPP | LCD_PCLK_EDGE_FALL |
LCD_AC_BIAS_FREQ(255),
.pxafb_backlight_power = &idp_backlight_power,
.pxafb_lcd_power = &idp_lcd_power
};
static int idp_mci_init(struct device *dev, irq_handler_t idp_detect_int, void *data)
{
/* setup GPIO for PXA25x MMC controller */
pxa_gpio_mode(GPIO6_MMCCLK_MD);
pxa_gpio_mode(GPIO8_MMCCS0_MD);
return 0;
}
static struct pxamci_platform_data idp_mci_platform_data = {
.ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
.init = idp_mci_init,
};
static void __init idp_init(void)
{
printk("idp_init()\n");
pxa2xx_mfp_config(ARRAY_AND_SIZE(idp_pin_config));
platform_device_register(&smc91x_device);
//platform_device_register(&mst_audio_device);
set_pxa_fb_info(&sharp_lm8v31);
pxa_set_mci_info(&idp_mci_platform_data);
}
static void __init idp_init_irq(void)
{
pxa25x_init_irq();
set_irq_type(TOUCH_PANEL_IRQ, TOUCH_PANEL_IRQ_EDGE);
}
static struct map_desc idp_io_desc[] __initdata = {
{
.virtual = IDP_COREVOLT_VIRT,
@ -177,15 +202,6 @@ static void __init idp_map_io(void)
{
pxa_map_io();
iotable_init(idp_io_desc, ARRAY_SIZE(idp_io_desc));
// serial ports 2 & 3
pxa_gpio_mode(GPIO42_BTRXD_MD);
pxa_gpio_mode(GPIO43_BTTXD_MD);
pxa_gpio_mode(GPIO44_BTCTS_MD);
pxa_gpio_mode(GPIO45_BTRTS_MD);
pxa_gpio_mode(GPIO46_STRXD_MD);
pxa_gpio_mode(GPIO47_STTXD_MD);
}
@ -194,7 +210,7 @@ MACHINE_START(PXA_IDP, "Vibren PXA255 IDP")
.phys_io = 0x40000000,
.io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
.map_io = idp_map_io,
.init_irq = idp_init_irq,
.init_irq = pxa25x_init_irq,
.timer = &pxa_timer,
.init_machine = idp_init,
MACHINE_END

32
arch/arm/mach-pxa/include/mach/akita.h
View file

@ -1,32 +0,0 @@
/*
* Hardware specific definitions for SL-C1000 (Akita)
*
* Copyright (c) 2005 Richard Purdie
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
/* Akita IO Expander GPIOs */
#define AKITA_IOEXP_RESERVED_7 (1 << 7)
#define AKITA_IOEXP_IR_ON (1 << 6)
#define AKITA_IOEXP_AKIN_PULLUP (1 << 5)
#define AKITA_IOEXP_BACKLIGHT_CONT (1 << 4)
#define AKITA_IOEXP_BACKLIGHT_ON (1 << 3)
#define AKITA_IOEXP_MIC_BIAS (1 << 2)
#define AKITA_IOEXP_RESERVED_1 (1 << 1)
#define AKITA_IOEXP_RESERVED_0 (1 << 0)
/* Direction Bitfield 0=output 1=input */
#define AKITA_IOEXP_IO_DIR 0
/* Default Values */
#define AKITA_IOEXP_IO_OUT (AKITA_IOEXP_IR_ON | AKITA_IOEXP_AKIN_PULLUP)
extern struct platform_device akitaioexp_device;
void akita_set_ioexp(struct device *dev, unsigned char bitmask);
void akita_reset_ioexp(struct device *dev, unsigned char bitmask);

11
arch/arm/mach-pxa/include/mach/corgi.h
View file

@ -98,12 +98,21 @@
CORGI_SCP_MIC_BIAS )
#define CORGI_SCOOP_IO_OUT ( CORGI_SCP_MUTE_L | CORGI_SCP_MUTE_R )
#define CORGI_SCOOP_GPIO_BASE (NR_BUILTIN_GPIO)
#define CORGI_GPIO_LED_GREEN (CORGI_SCOOP_GPIO_BASE + 0)
#define CORGI_GPIO_SWA (CORGI_SCOOP_GPIO_BASE + 1) /* Hinge Switch A */
#define CORGI_GPIO_SWB (CORGI_SCOOP_GPIO_BASE + 2) /* Hinge Switch B */
#define CORGI_GPIO_MUTE_L (CORGI_SCOOP_GPIO_BASE + 3)
#define CORGI_GPIO_MUTE_R (CORGI_SCOOP_GPIO_BASE + 4)
#define CORGI_GPIO_AKIN_PULLUP (CORGI_SCOOP_GPIO_BASE + 5)
#define CORGI_GPIO_APM_ON (CORGI_SCOOP_GPIO_BASE + 6)
#define CORGI_GPIO_BACKLIGHT_CONT (CORGI_SCOOP_GPIO_BASE + 7)
#define CORGI_GPIO_MIC_BIAS (CORGI_SCOOP_GPIO_BASE + 8)
/*
* Shared data structures
*/
extern struct platform_device corgiscoop_device;
extern struct platform_device corgissp_device;
#endif /* __ASM_ARCH_CORGI_H */

4
arch/arm/mach-pxa/include/mach/entry-macro.S
View file

@ -41,7 +41,7 @@
and \irqstat, \irqstat, \irqnr
clz \irqnr, \irqstat
rsb \irqnr, \irqnr, #31
add \irqnr, \irqnr, #32
add \irqnr, \irqnr, #(32 + PXA_IRQ(0))
b 1001f
1003:
mrc p6, 0, \irqstat, c0, c0, 0 @ ICIP
@ -52,6 +52,6 @@
rsb \irqstat, \irqnr, #0
and \irqstat, \irqstat, \irqnr
clz \irqnr, \irqstat
rsb \irqnr, \irqnr, #31
rsb \irqnr, \irqnr, #(31 + PXA_IRQ(0))
1001:
.endm

79
arch/arm/mach-pxa/include/mach/hardware.h
View file

@ -64,26 +64,72 @@
#include <asm/cputype.h>
/*
* CPU Stepping CPU_ID JTAG_ID
*
* PXA210 B0 0x69052922 0x2926C013
* PXA210 B1 0x69052923 0x3926C013
* PXA210 B2 0x69052924 0x4926C013
* PXA210 C0 0x69052D25 0x5926C013
*
* PXA250 A0 0x69052100 0x09264013
* PXA250 A1 0x69052101 0x19264013
* PXA250 B0 0x69052902 0x29264013
* PXA250 B1 0x69052903 0x39264013
* PXA250 B2 0x69052904 0x49264013
* PXA250 C0 0x69052D05 0x59264013
*
* PXA255 A0 0x69052D06 0x69264013
*
* PXA26x A0 0x69052903 0x39264013
* PXA26x B0 0x69052D05 0x59264013
*
* PXA27x A0 0x69054110 0x09265013
* PXA27x A1 0x69054111 0x19265013
* PXA27x B0 0x69054112 0x29265013
* PXA27x B1 0x69054113 0x39265013
* PXA27x C0 0x69054114 0x49265013
* PXA27x C5 0x69054117 0x79265013
*
* PXA30x A0 0x69056880 0x0E648013
* PXA30x A1 0x69056881 0x1E648013
* PXA31x A0 0x69056890 0x0E649013
* PXA31x A1 0x69056891 0x1E649013
* PXA31x A2 0x69056892 0x2E649013
* PXA32x B1 0x69056825 0x5E642013
* PXA32x B2 0x69056826 0x6E642013
*
* PXA930 B0 0x69056835 0x5E643013
* PXA930 B1 0x69056837 0x7E643013
* PXA930 B2 0x69056838 0x8E643013
*/
#ifdef CONFIG_PXA25x
#define __cpu_is_pxa21x(id) \
#define __cpu_is_pxa210(id) \
({ \
unsigned int _id = (id) >> 4 & 0xf3f; \
_id == 0x212; \
unsigned int _id = (id) & 0xf3f0; \
_id == 0x2120; \
})
#define __cpu_is_pxa255(id) \
({ \
unsigned int _id = (id) >> 4 & 0xfff; \
_id == 0x2d0; \
})
#define __cpu_is_pxa250(id) \
({ \
unsigned int _id = (id) & 0xf3ff; \
_id <= 0x2105; \
})
#define __cpu_is_pxa255(id) \
({ \
unsigned int _id = (id) & 0xffff; \
_id == 0x2d06; \
})
#define __cpu_is_pxa25x(id) \
({ \
unsigned int _id = (id) >> 4 & 0xfff; \
_id == 0x2d0 || _id == 0x290; \
unsigned int _id = (id) & 0xf300; \
_id == 0x2100; \
})
#else
#define __cpu_is_pxa21x(id) (0)
#define __cpu_is_pxa210(id) (0)
#define __cpu_is_pxa250(id) (0)
#define __cpu_is_pxa255(id) (0)
#define __cpu_is_pxa25x(id) (0)
#endif
@ -138,9 +184,14 @@
#define __cpu_is_pxa930(id) (0)
#endif
#define cpu_is_pxa21x() \
#define cpu_is_pxa210() \
({ \
__cpu_is_pxa21x(read_cpuid_id()); \
__cpu_is_pxa210(read_cpuid_id()); \
})
#define cpu_is_pxa250() \
({ \
__cpu_is_pxa250(read_cpuid_id()); \
})
#define cpu_is_pxa255() \
@ -153,6 +204,8 @@
__cpu_is_pxa25x(read_cpuid_id()); \
})
extern int cpu_is_pxa26x(void);
#define cpu_is_pxa27x() \
({ \
__cpu_is_pxa27x(read_cpuid_id()); \

9
arch/arm/mach-pxa/include/mach/i2c.h
View file

@ -65,13 +65,18 @@ struct i2c_pxa_platform_data {
unsigned int slave_addr;
struct i2c_slave_client *slave;
unsigned int class;
int use_pio;
unsigned int use_pio :1;
unsigned int fast_mode :1;
};
extern void pxa_set_i2c_info(struct i2c_pxa_platform_data *info);
#ifdef CONFIG_PXA27x
extern void pxa_set_i2c_power_info(struct i2c_pxa_platform_data *info);
extern void pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info);
#endif
#ifdef CONFIG_PXA3xx
extern void pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info);
#endif
#endif

19
arch/arm/mach-pxa/include/mach/irqs.h
View file

@ -11,7 +11,14 @@
*/
#define PXA_IRQ(x) (x)
#ifdef CONFIG_PXA_HAVE_ISA_IRQS
#define PXA_ISA_IRQ(x) (x)
#define PXA_ISA_IRQ_NUM (16)
#else
#define PXA_ISA_IRQ_NUM (0)
#endif
#define PXA_IRQ(x) (PXA_ISA_IRQ_NUM + (x))
#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
#define IRQ_SSP3 PXA_IRQ(0) /* SSP3 service request */
@ -73,7 +80,7 @@
#define IRQ_MMC3 PXA_IRQ(55) /* MMC3 Controller (PXA310) */
#endif
#define PXA_GPIO_IRQ_BASE (64)
#define PXA_GPIO_IRQ_BASE PXA_IRQ(64)
#define PXA_GPIO_IRQ_NUM (128)
#define GPIO_2_x_TO_IRQ(x) (PXA_GPIO_IRQ_BASE + (x))
@ -178,13 +185,7 @@
#define NR_IRQS (IRQ_S1_BVD1_STSCHG + 1)
#elif defined(CONFIG_SHARP_LOCOMO)
#define NR_IRQS (IRQ_LOCOMO_SPI_TEND + 1)
#elif defined(CONFIG_ARCH_LUBBOCK) || \
defined(CONFIG_MACH_LOGICPD_PXA270) || \
defined(CONFIG_MACH_TOSA) || \
defined(CONFIG_MACH_MAINSTONE) || \
defined(CONFIG_MACH_PCM027) || \
defined(CONFIG_ARCH_PXA_ESERIES) || \
defined(CONFIG_MACH_MAGICIAN)
#elif defined(CONFIG_PXA_HAVE_BOARD_IRQS)
#define NR_IRQS (IRQ_BOARD_END)
#elif defined(CONFIG_MACH_ZYLONITE)
#define NR_IRQS (IRQ_BOARD_START + 32)

2
arch/arm/mach-pxa/include/mach/littleton.h
View file

@ -3,4 +3,6 @@
#define LITTLETON_ETH_PHYS 0x30000000
#define LITTLETON_GPIO_LCD_CS (17)
#endif /* __ASM_ARCH_ZYLONITE_H */

4
arch/arm/mach-pxa/include/mach/memory.h
View file

@ -40,11 +40,11 @@
#define NODE_MEM_SIZE_BITS 26
#if !defined(__ASSEMBLY__) && defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI)
void cmx270_pci_adjust_zones(int node, unsigned long *size,
void cmx2xx_pci_adjust_zones(int node, unsigned long *size,
unsigned long *holes);
#define arch_adjust_zones(node, size, holes) \
cmx270_pci_adjust_zones(node, size, holes)
cmx2xx_pci_adjust_zones(node, size, holes)
#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_64M - 1)
#endif

4
arch/arm/mach-pxa/include/mach/mfp-pxa25x.h
View file

@ -17,7 +17,7 @@
/* Crystal and Clock Signals */
#define GPIO10_RTCCLK MFP_CFG_OUT(GPIO10, AF1, DRIVE_LOW)
#define GPIO70_RTC_CLK MFP_CFG_OUT(GPIO70, AF1, DRIVE_LOW)
#define GPIO70_RTCCLK MFP_CFG_OUT(GPIO70, AF1, DRIVE_LOW)
#define GPIO7_48MHz MFP_CFG_OUT(GPIO7, AF1, DRIVE_LOW)
#define GPIO11_3_6MHz MFP_CFG_OUT(GPIO11, AF1, DRIVE_LOW)
#define GPIO71_3_6MHz MFP_CFG_OUT(GPIO71, AF1, DRIVE_LOW)
@ -156,6 +156,6 @@
#define GPIO74_LCD_FCLK MFP_CFG_OUT(GPIO74, AF2, DRIVE_LOW)
#define GPIO75_LCD_LCLK MFP_CFG_OUT(GPIO75, AF2, DRIVE_LOW)
#define GPIO76_LCD_PCLK MFP_CFG_OUT(GPIO76, AF2, DRIVE_LOW)
#define GPIO77_LCD_ACBIAS MFP_CFG_OUT(GPIO77, AF2, DRIVE_LOW)
#define GPIO77_LCD_BIAS MFP_CFG_OUT(GPIO77, AF2, DRIVE_LOW)
#endif /* __ASM_ARCH_MFP_PXA25X_H */

8
arch/arm/mach-pxa/include/mach/mfp-pxa320.h
View file

@ -257,10 +257,10 @@
#define GPIO38_SSP2_RXD MFP_CFG(GPIO38, AF2)
#define GPIO38_SSP2_TXD MFP_CFG(GPIO38, AF5)
#define GPIO69_SSP3_SCLK MFP_CFG(GPIO69, AF2, DS08X, FLOAT)
#define GPIO70_SSP3_FRM MFP_CFG(GPIO70, AF2, DS08X, DRIVE_LOW)
#define GPIO89_SSP3_SCLK MFP_CFG(GPIO89, AF1, DS08X, FLOAT)
#define GPIO90_SSP3_FRM MFP_CFG(GPIO90, AF1, DS08X, DRIVE_LOW)
#define GPIO69_SSP3_SCLK MFP_CFG_X(GPIO69, AF2, DS08X, FLOAT)
#define GPIO70_SSP3_FRM MFP_CFG_X(GPIO70, AF2, DS08X, DRIVE_LOW)
#define GPIO89_SSP3_SCLK MFP_CFG_X(GPIO89, AF1, DS08X, FLOAT)
#define GPIO90_SSP3_FRM MFP_CFG_X(GPIO90, AF1, DS08X, DRIVE_LOW)
#define GPIO71_SSP3_RXD MFP_CFG_X(GPIO71, AF5, DS08X, FLOAT)
#define GPIO71_SSP3_TXD MFP_CFG_X(GPIO71, AF2, DS08X, DRIVE_LOW)
#define GPIO72_SSP3_RXD MFP_CFG_X(GPIO72, AF2, DS08X, FLOAT)

5
arch/arm/mach-pxa/include/mach/mfp.h
View file

@ -274,12 +274,13 @@ typedef unsigned long mfp_cfg_t;
#define MFP_DS_MASK (0x7 << 13)
#define MFP_DS(x) (((x) >> 13) & 0x7)
#define MFP_LPM_INPUT (0x0 << 16)
#define MFP_LPM_DEFAULT (0x0 << 16)
#define MFP_LPM_DRIVE_LOW (0x1 << 16)
#define MFP_LPM_DRIVE_HIGH (0x2 << 16)
#define MFP_LPM_PULL_LOW (0x3 << 16)
#define MFP_LPM_PULL_HIGH (0x4 << 16)
#define MFP_LPM_FLOAT (0x5 << 16)
#define MFP_LPM_INPUT (0x6 << 16)
#define MFP_LPM_STATE_MASK (0x7 << 16)
#define MFP_LPM_STATE(x) (((x) >> 16) & 0x7)
@ -297,7 +298,7 @@ typedef unsigned long mfp_cfg_t;
#define MFP_PULL_MASK (0x3 << 21)
#define MFP_PULL(x) (((x) >> 21) & 0x3)
#define MFP_CFG_DEFAULT (MFP_AF0 | MFP_DS03X | MFP_LPM_INPUT |\
#define MFP_CFG_DEFAULT (MFP_AF0 | MFP_DS03X | MFP_LPM_DEFAULT |\
MFP_LPM_EDGE_NONE | MFP_PULL_NONE)
#define MFP_CFG(pin, af) \

67
arch/arm/mach-pxa/include/mach/mioa701.h Normal file
View file

@ -0,0 +1,67 @@
#ifndef _MIOA701_H_
#define _MIOA701_H_
#define MIO_CFG_IN(pin, af) \
((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DIR_MASK)) |\
(MFP_PIN(pin) | MFP_##af | MFP_DIR_IN))
#define MIO_CFG_OUT(pin, af, state) \
((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DIR_MASK | MFP_LPM_STATE_MASK)) |\
(MFP_PIN(pin) | MFP_##af | MFP_DIR_OUT | MFP_LPM_##state))
/* Global GPIOs */
#define GPIO9_CHARGE_nEN 9
#define GPIO18_POWEROFF 18
#define GPIO87_LCD_POWER 87
/* USB */
#define GPIO13_USB_DETECT 13
#define GPIO22_USB_ENABLE 22
/* SDIO bits */
#define GPIO78_SDIO_RO 78
#define GPIO15_SDIO_INSERT 15
#define GPIO91_SDIO_EN 91
/* Bluetooth */
#define GPIO83_BT_ON 83
/* GPS */
#define GPIO23_GPS_UNKNOWN1 23
#define GPIO26_GPS_ON 26
#define GPIO27_GPS_RESET 27
#define GPIO106_GPS_UNKNOWN2 106
#define GPIO107_GPS_UNKNOWN3 107
/* GSM */
#define GPIO24_GSM_MOD_RESET_CMD 24
#define GPIO88_GSM_nMOD_ON_CMD 88
#define GPIO90_GSM_nMOD_OFF_CMD 90
#define GPIO114_GSM_nMOD_DTE_UART_STATE 114
#define GPIO25_GSM_MOD_ON_STATE 25
#define GPIO113_GSM_EVENT 113
/* SOUND */
#define GPIO12_HPJACK_INSERT 12
/* LEDS */
#define GPIO10_LED_nCharging 10
#define GPIO97_LED_nBlue 97
#define GPIO98_LED_nOrange 98
#define GPIO82_LED_nVibra 82
#define GPIO115_LED_nKeyboard 115
/* Keyboard */
#define GPIO0_KEY_POWER 0
#define GPIO93_KEY_VOLUME_UP 93
#define GPIO94_KEY_VOLUME_DOWN 94
extern struct input_dev *mioa701_evdev;
extern void mioa701_gpio_lpm_set(unsigned long mfp_pin);
/* Assembler externals mioa701_bootresume.S */
extern u32 mioa701_bootstrap;
extern u32 mioa701_jumpaddr;
extern u32 mioa701_bootstrap_lg;
#endif /* _MIOA701_H */

16
arch/arm/mach-pxa/include/mach/ohci.h
View file

@ -7,6 +7,22 @@ struct pxaohci_platform_data {
int (*init)(struct device *);
void (*exit)(struct device *);
unsigned long flags;
#define ENABLE_PORT1 (1 << 0)
#define ENABLE_PORT2 (1 << 1)
#define ENABLE_PORT3 (1 << 2)
#define ENABLE_PORT_ALL (ENABLE_PORT1 | ENABLE_PORT2 | ENABLE_PORT3)
#define POWER_SENSE_LOW (1 << 3)
#define POWER_CONTROL_LOW (1 << 4)
#define NO_OC_PROTECTION (1 << 5)
#define OC_MODE_GLOBAL (0 << 6)
#define OC_MODE_PERPORT (1 << 6)
int power_on_delay; /* Power On to Power Good time - in ms
* HCD must wait for this duration before
* accessing a powered on port
*/
int port_mode;
#define PMM_NPS_MODE 1
#define PMM_GLOBAL_MODE 2

80
arch/arm/mach-pxa/include/mach/palmz72.h Normal file
View file

@ -0,0 +1,80 @@
/*
* GPIOs and interrupts for Palm Zire72 Handheld Computer
*
* Authors: Alex Osborne <bobofdoom@gmail.com>
* Jan Herman <2hp@seznam.cz>
* Sergey Lapin <slapin@ossfans.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef _INCLUDE_PALMZ72_H_
#define _INCLUDE_PALMZ72_H_
/* Power and control */
#define GPIO_NR_PALMZ72_GPIO_RESET 1
#define GPIO_NR_PALMZ72_POWER_DETECT 0
/* SD/MMC */
#define GPIO_NR_PALMZ72_SD_DETECT_N 14
#define GPIO_NR_PALMZ72_SD_POWER_N 98
#define GPIO_NR_PALMZ72_SD_RO 115
/* Touchscreen */
#define GPIO_NR_PALMZ72_WM9712_IRQ 27
/* IRDA - disable GPIO connected to SD pin of tranceiver (TFBS4710?) ? */
#define GPIO_NR_PALMZ72_IR_DISABLE 49
/* USB */
#define GPIO_NR_PALMZ72_USB_DETECT_N 15
#define GPIO_NR_PALMZ72_USB_POWER 95
#define GPIO_NR_PALMZ72_USB_PULLUP 12
/* LCD/Backlight */
#define GPIO_NR_PALMZ72_BL_POWER 20
#define GPIO_NR_PALMZ72_LCD_POWER 96
/* LED */
#define GPIO_NR_PALMZ72_LED_GREEN 88
/* Bluetooth */
#define GPIO_NR_PALMZ72_BT_POWER 17
#define GPIO_NR_PALMZ72_BT_RESET 83
/** Initial values **/
/* Battery */
#define PALMZ72_BAT_MAX_VOLTAGE 4000 /* 4.00v current voltage */
#define PALMZ72_BAT_MIN_VOLTAGE 3550 /* 3.55v critical voltage */
#define PALMZ72_BAT_MAX_CURRENT 0 /* unknokn */
#define PALMZ72_BAT_MIN_CURRENT 0 /* unknown */
#define PALMZ72_BAT_MAX_CHARGE 1 /* unknown */
#define PALMZ72_BAT_MIN_CHARGE 1 /* unknown */
#define PALMZ72_MAX_LIFE_MINS 360 /* on-life in minutes */
/* Backlight */
#define PALMZ72_MAX_INTENSITY 0xFE
#define PALMZ72_DEFAULT_INTENSITY 0x7E
#define PALMZ72_LIMIT_MASK 0x7F
#define PALMZ72_PRESCALER 0x3F
#define PALMZ72_PERIOD_NS 3500
#ifdef CONFIG_PM
struct palmz72_resume_info {
u32 magic0; /* 0x0 */
u32 magic1; /* 0x4 */
u32 resume_addr; /* 0x8 */
u32 pad[11]; /* 0xc..0x37 */
u32 arm_control; /* 0x38 */
u32 aux_control; /* 0x3c */
u32 ttb; /* 0x40 */
u32 domain_access; /* 0x44 */
u32 process_id; /* 0x48 */
};
#endif
#endif

2
arch/arm/mach-pxa/include/mach/pm.h
View file

@ -15,6 +15,8 @@ struct pxa_cpu_pm_fns {
void (*restore)(unsigned long *);
int (*valid)(suspend_state_t state);
void (*enter)(suspend_state_t state);
int (*prepare)(void);
void (*finish)(void);
};
extern struct pxa_cpu_pm_fns *pxa_cpu_pm_fns;

9
arch/arm/mach-pxa/include/mach/poodle.h
View file

@ -23,6 +23,7 @@
#define POODLE_GPIO_AC_IN (1)
#define POODLE_GPIO_CO 16
#define POODLE_GPIO_TP_INT (5)
#define POODLE_GPIO_TP_CS (24)
#define POODLE_GPIO_WAKEUP (11) /* change battery */
#define POODLE_GPIO_GA_INT (10)
#define POODLE_GPIO_IR_ON (22)
@ -70,6 +71,14 @@
#define POODLE_SCOOP_IO_DIR ( POODLE_SCOOP_VPEN | POODLE_SCOOP_HS_OUT )
#define POODLE_SCOOP_IO_OUT ( 0 )
#define POODLE_SCOOP_GPIO_BASE (NR_BUILTIN_GPIO)
#define POODLE_GPIO_CHARGE_ON (POODLE_SCOOP_GPIO_BASE + 0)
#define POODLE_GPIO_CP401 (POODLE_SCOOP_GPIO_BASE + 2)
#define POODLE_GPIO_VPEN (POODLE_SCOOP_GPIO_BASE + 7)
#define POODLE_GPIO_L_PCLK (POODLE_SCOOP_GPIO_BASE + 9)
#define POODLE_GPIO_L_LCLK (POODLE_SCOOP_GPIO_BASE + 10)
#define POODLE_GPIO_HS_OUT (POODLE_SCOOP_GPIO_BASE + 11)
#define POODLE_LOCOMO_GPIO_AMP_ON LOCOMO_GPIO(8)
#define POODLE_LOCOMO_GPIO_MUTE_L LOCOMO_GPIO(10)
#define POODLE_LOCOMO_GPIO_MUTE_R LOCOMO_GPIO(11)

320
arch/arm/mach-pxa/include/mach/pxa-regs.h
View file

@ -69,30 +69,18 @@
/*
* DMA Controller
*/
#define DCSR0 __REG(0x40000000) /* DMA Control / Status Register for Channel 0 */
#define DCSR1 __REG(0x40000004) /* DMA Control / Status Register for Channel 1 */
#define DCSR2 __REG(0x40000008) /* DMA Control / Status Register for Channel 2 */
#define DCSR3 __REG(0x4000000c) /* DMA Control / Status Register for Channel 3 */
#define DCSR4 __REG(0x40000010) /* DMA Control / Status Register for Channel 4 */
#define DCSR5 __REG(0x40000014) /* DMA Control / Status Register for Channel 5 */
#define DCSR6 __REG(0x40000018) /* DMA Control / Status Register for Channel 6 */
#define DCSR7 __REG(0x4000001c) /* DMA Control / Status Register for Channel 7 */
#define DCSR8 __REG(0x40000020) /* DMA Control / Status Register for Channel 8 */
#define DCSR9 __REG(0x40000024) /* DMA Control / Status Register for Channel 9 */
#define DCSR10 __REG(0x40000028) /* DMA Control / Status Register for Channel 10 */
#define DCSR11 __REG(0x4000002c) /* DMA Control / Status Register for Channel 11 */
#define DCSR12 __REG(0x40000030) /* DMA Control / Status Register for Channel 12 */
#define DCSR13 __REG(0x40000034) /* DMA Control / Status Register for Channel 13 */
#define DCSR14 __REG(0x40000038) /* DMA Control / Status Register for Channel 14 */
#define DCSR15 __REG(0x4000003c) /* DMA Control / Status Register for Channel 15 */
#define DCSR(x) __REG2(0x40000000, (x) << 2)
#define DCSR_RUN (1 << 31) /* Run Bit (read / write) */
#define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */
#define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */
#ifdef CONFIG_PXA27x
#define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */
#define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */
#define DCSR_ENDINTR (1 << 2) /* End Interrupt (read / write) */
#define DCSR_STARTINTR (1 << 1) /* Start Interrupt (read / write) */
#define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt (read / write) */
#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
#define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */
#define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */
#define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */
@ -101,11 +89,6 @@
#define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */
#define DCSR_EORINTR (1 << 9) /* The end of Receive */
#endif
#define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */
#define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */
#define DCSR_ENDINTR (1 << 2) /* End Interrupt (read / write) */
#define DCSR_STARTINTR (1 << 1) /* Start Interrupt (read / write) */
#define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt (read / write) */
#define DALGN __REG(0x400000a0) /* DMA Alignment Register */
#define DINT __REG(0x400000f0) /* DMA Interrupt Register */
@ -114,145 +97,9 @@
&__REG2(0x40000100, ((n) & 0x3f) << 2) : \
&__REG2(0x40001100, ((n) & 0x3f) << 2)))
#define DRCMR0 __REG(0x40000100) /* Request to Channel Map Register for DREQ 0 */
#define DRCMR1 __REG(0x40000104) /* Request to Channel Map Register for DREQ 1 */
#define DRCMR2 __REG(0x40000108) /* Request to Channel Map Register for I2S receive Request */
#define DRCMR3 __REG(0x4000010c) /* Request to Channel Map Register for I2S transmit Request */
#define DRCMR4 __REG(0x40000110) /* Request to Channel Map Register for BTUART receive Request */
#define DRCMR5 __REG(0x40000114) /* Request to Channel Map Register for BTUART transmit Request. */
#define DRCMR6 __REG(0x40000118) /* Request to Channel Map Register for FFUART receive Request */
#define DRCMR7 __REG(0x4000011c) /* Request to Channel Map Register for FFUART transmit Request */
#define DRCMR8 __REG(0x40000120) /* Request to Channel Map Register for AC97 microphone Request */
#define DRCMR9 __REG(0x40000124) /* Request to Channel Map Register for AC97 modem receive Request */
#define DRCMR10 __REG(0x40000128) /* Request to Channel Map Register for AC97 modem transmit Request */
#define DRCMR11 __REG(0x4000012c) /* Request to Channel Map Register for AC97 audio receive Request */
#define DRCMR12 __REG(0x40000130) /* Request to Channel Map Register for AC97 audio transmit Request */
#define DRCMR13 __REG(0x40000134) /* Request to Channel Map Register for SSP receive Request */
#define DRCMR14 __REG(0x40000138) /* Request to Channel Map Register for SSP transmit Request */
#define DRCMR15 __REG(0x4000013c) /* Request to Channel Map Register for SSP2 receive Request */
#define DRCMR16 __REG(0x40000140) /* Request to Channel Map Register for SSP2 transmit Request */
#define DRCMR17 __REG(0x40000144) /* Request to Channel Map Register for ICP receive Request */
#define DRCMR18 __REG(0x40000148) /* Request to Channel Map Register for ICP transmit Request */
#define DRCMR19 __REG(0x4000014c) /* Request to Channel Map Register for STUART receive Request */
#define DRCMR20 __REG(0x40000150) /* Request to Channel Map Register for STUART transmit Request */
#define DRCMR21 __REG(0x40000154) /* Request to Channel Map Register for MMC receive Request */
#define DRCMR22 __REG(0x40000158) /* Request to Channel Map Register for MMC transmit Request */
#define DRCMR23 __REG(0x4000015c) /* Reserved */
#define DRCMR24 __REG(0x40000160) /* Reserved */
#define DRCMR25 __REG(0x40000164) /* Request to Channel Map Register for USB endpoint 1 Request */
#define DRCMR26 __REG(0x40000168) /* Request to Channel Map Register for USB endpoint 2 Request */
#define DRCMR27 __REG(0x4000016C) /* Request to Channel Map Register for USB endpoint 3 Request */
#define DRCMR28 __REG(0x40000170) /* Request to Channel Map Register for USB endpoint 4 Request */
#define DRCMR29 __REG(0x40000174) /* Reserved */
#define DRCMR30 __REG(0x40000178) /* Request to Channel Map Register for USB endpoint 6 Request */
#define DRCMR31 __REG(0x4000017C) /* Request to Channel Map Register for USB endpoint 7 Request */
#define DRCMR32 __REG(0x40000180) /* Request to Channel Map Register for USB endpoint 8 Request */
#define DRCMR33 __REG(0x40000184) /* Request to Channel Map Register for USB endpoint 9 Request */
#define DRCMR34 __REG(0x40000188) /* Reserved */
#define DRCMR35 __REG(0x4000018C) /* Request to Channel Map Register for USB endpoint 11 Request */
#define DRCMR36 __REG(0x40000190) /* Request to Channel Map Register for USB endpoint 12 Request */
#define DRCMR37 __REG(0x40000194) /* Request to Channel Map Register for USB endpoint 13 Request */
#define DRCMR38 __REG(0x40000198) /* Request to Channel Map Register for USB endpoint 14 Request */
#define DRCMR39 __REG(0x4000019C) /* Reserved */
#define DRCMR66 __REG(0x40001108) /* Request to Channel Map Register for SSP3 receive Request */
#define DRCMR67 __REG(0x4000110C) /* Request to Channel Map Register for SSP3 transmit Request */
#define DRCMR68 __REG(0x40001110) /* Request to Channel Map Register for Camera FIFO 0 Request */
#define DRCMR69 __REG(0x40001114) /* Request to Channel Map Register for Camera FIFO 1 Request */
#define DRCMR70 __REG(0x40001118) /* Request to Channel Map Register for Camera FIFO 2 Request */
#define DRCMRRXSADR DRCMR2
#define DRCMRTXSADR DRCMR3
#define DRCMRRXBTRBR DRCMR4
#define DRCMRTXBTTHR DRCMR5
#define DRCMRRXFFRBR DRCMR6
#define DRCMRTXFFTHR DRCMR7
#define DRCMRRXMCDR DRCMR8
#define DRCMRRXMODR DRCMR9
#define DRCMRTXMODR DRCMR10
#define DRCMRRXPCDR DRCMR11
#define DRCMRTXPCDR DRCMR12
#define DRCMRRXSSDR DRCMR13
#define DRCMRTXSSDR DRCMR14
#define DRCMRRXSS2DR DRCMR15
#define DRCMRTXSS2DR DRCMR16
#define DRCMRRXICDR DRCMR17
#define DRCMRTXICDR DRCMR18
#define DRCMRRXSTRBR DRCMR19
#define DRCMRTXSTTHR DRCMR20
#define DRCMRRXMMC DRCMR21
#define DRCMRTXMMC DRCMR22
#define DRCMRRXSS3DR DRCMR66
#define DRCMRTXSS3DR DRCMR67
#define DRCMRUDC(x) DRCMR((x) + 24)
#define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */
#define DRCMR_CHLNUM 0x1f /* mask for Channel Number (read / write) */
#define DDADR0 __REG(0x40000200) /* DMA Descriptor Address Register Channel 0 */
#define DSADR0 __REG(0x40000204) /* DMA Source Address Register Channel 0 */
#define DTADR0 __REG(0x40000208) /* DMA Target Address Register Channel 0 */
#define DCMD0 __REG(0x4000020c) /* DMA Command Address Register Channel 0 */
#define DDADR1 __REG(0x40000210) /* DMA Descriptor Address Register Channel 1 */
#define DSADR1 __REG(0x40000214) /* DMA Source Address Register Channel 1 */
#define DTADR1 __REG(0x40000218) /* DMA Target Address Register Channel 1 */
#define DCMD1 __REG(0x4000021c) /* DMA Command Address Register Channel 1 */
#define DDADR2 __REG(0x40000220) /* DMA Descriptor Address Register Channel 2 */
#define DSADR2 __REG(0x40000224) /* DMA Source Address Register Channel 2 */
#define DTADR2 __REG(0x40000228) /* DMA Target Address Register Channel 2 */
#define DCMD2 __REG(0x4000022c) /* DMA Command Address Register Channel 2 */
#define DDADR3 __REG(0x40000230) /* DMA Descriptor Address Register Channel 3 */
#define DSADR3 __REG(0x40000234) /* DMA Source Address Register Channel 3 */
#define DTADR3 __REG(0x40000238) /* DMA Target Address Register Channel 3 */
#define DCMD3 __REG(0x4000023c) /* DMA Command Address Register Channel 3 */
#define DDADR4 __REG(0x40000240) /* DMA Descriptor Address Register Channel 4 */
#define DSADR4 __REG(0x40000244) /* DMA Source Address Register Channel 4 */
#define DTADR4 __REG(0x40000248) /* DMA Target Address Register Channel 4 */
#define DCMD4 __REG(0x4000024c) /* DMA Command Address Register Channel 4 */
#define DDADR5 __REG(0x40000250) /* DMA Descriptor Address Register Channel 5 */
#define DSADR5 __REG(0x40000254) /* DMA Source Address Register Channel 5 */
#define DTADR5 __REG(0x40000258) /* DMA Target Address Register Channel 5 */
#define DCMD5 __REG(0x4000025c) /* DMA Command Address Register Channel 5 */
#define DDADR6 __REG(0x40000260) /* DMA Descriptor Address Register Channel 6 */
#define DSADR6 __REG(0x40000264) /* DMA Source Address Register Channel 6 */
#define DTADR6 __REG(0x40000268) /* DMA Target Address Register Channel 6 */
#define DCMD6 __REG(0x4000026c) /* DMA Command Address Register Channel 6 */
#define DDADR7 __REG(0x40000270) /* DMA Descriptor Address Register Channel 7 */
#define DSADR7 __REG(0x40000274) /* DMA Source Address Register Channel 7 */
#define DTADR7 __REG(0x40000278) /* DMA Target Address Register Channel 7 */
#define DCMD7 __REG(0x4000027c) /* DMA Command Address Register Channel 7 */
#define DDADR8 __REG(0x40000280) /* DMA Descriptor Address Register Channel 8 */
#define DSADR8 __REG(0x40000284) /* DMA Source Address Register Channel 8 */
#define DTADR8 __REG(0x40000288) /* DMA Target Address Register Channel 8 */
#define DCMD8 __REG(0x4000028c) /* DMA Command Address Register Channel 8 */
#define DDADR9 __REG(0x40000290) /* DMA Descriptor Address Register Channel 9 */
#define DSADR9 __REG(0x40000294) /* DMA Source Address Register Channel 9 */
#define DTADR9 __REG(0x40000298) /* DMA Target Address Register Channel 9 */
#define DCMD9 __REG(0x4000029c) /* DMA Command Address Register Channel 9 */
#define DDADR10 __REG(0x400002a0) /* DMA Descriptor Address Register Channel 10 */
#define DSADR10 __REG(0x400002a4) /* DMA Source Address Register Channel 10 */
#define DTADR10 __REG(0x400002a8) /* DMA Target Address Register Channel 10 */
#define DCMD10 __REG(0x400002ac) /* DMA Command Address Register Channel 10 */
#define DDADR11 __REG(0x400002b0) /* DMA Descriptor Address Register Channel 11 */
#define DSADR11 __REG(0x400002b4) /* DMA Source Address Register Channel 11 */
#define DTADR11 __REG(0x400002b8) /* DMA Target Address Register Channel 11 */
#define DCMD11 __REG(0x400002bc) /* DMA Command Address Register Channel 11 */
#define DDADR12 __REG(0x400002c0) /* DMA Descriptor Address Register Channel 12 */
#define DSADR12 __REG(0x400002c4) /* DMA Source Address Register Channel 12 */
#define DTADR12 __REG(0x400002c8) /* DMA Target Address Register Channel 12 */
#define DCMD12 __REG(0x400002cc) /* DMA Command Address Register Channel 12 */
#define DDADR13 __REG(0x400002d0) /* DMA Descriptor Address Register Channel 13 */
#define DSADR13 __REG(0x400002d4) /* DMA Source Address Register Channel 13 */
#define DTADR13 __REG(0x400002d8) /* DMA Target Address Register Channel 13 */
#define DCMD13 __REG(0x400002dc) /* DMA Command Address Register Channel 13 */
#define DDADR14 __REG(0x400002e0) /* DMA Descriptor Address Register Channel 14 */
#define DSADR14 __REG(0x400002e4) /* DMA Source Address Register Channel 14 */
#define DTADR14 __REG(0x400002e8) /* DMA Target Address Register Channel 14 */
#define DCMD14 __REG(0x400002ec) /* DMA Command Address Register Channel 14 */
#define DDADR15 __REG(0x400002f0) /* DMA Descriptor Address Register Channel 15 */
#define DSADR15 __REG(0x400002f4) /* DMA Source Address Register Channel 15 */
#define DTADR15 __REG(0x400002f8) /* DMA Target Address Register Channel 15 */
#define DCMD15 __REG(0x400002fc) /* DMA Command Address Register Channel 15 */
#define DDADR(x) __REG2(0x40000200, (x) << 4)
#define DSADR(x) __REG2(0x40000204, (x) << 4)
#define DTADR(x) __REG2(0x40000208, (x) << 4)
@ -418,91 +265,13 @@
/*
* I2C registers
* I2C registers - moved into drivers/i2c/busses/i2c-pxa.c
*/
#define IBMR __REG(0x40301680) /* I2C Bus Monitor Register - IBMR */
#define IDBR __REG(0x40301688) /* I2C Data Buffer Register - IDBR */
#define ICR __REG(0x40301690) /* I2C Control Register - ICR */
#define ISR __REG(0x40301698) /* I2C Status Register - ISR */
#define ISAR __REG(0x403016A0) /* I2C Slave Address Register - ISAR */
#define PWRIBMR __REG(0x40f00180) /* Power I2C Bus Monitor Register-IBMR */
#define PWRIDBR __REG(0x40f00188) /* Power I2C Data Buffer Register-IDBR */
#define PWRICR __REG(0x40f00190) /* Power I2C Control Register - ICR */
#define PWRISR __REG(0x40f00198) /* Power I2C Status Register - ISR */
#define PWRISAR __REG(0x40f001A0) /*Power I2C Slave Address Register-ISAR */
#define ICR_START (1 << 0) /* start bit */
#define ICR_STOP (1 << 1) /* stop bit */
#define ICR_ACKNAK (1 << 2) /* send ACK(0) or NAK(1) */
#define ICR_TB (1 << 3) /* transfer byte bit */
#define ICR_MA (1 << 4) /* master abort */
#define ICR_SCLE (1 << 5) /* master clock enable */
#define ICR_IUE (1 << 6) /* unit enable */
#define ICR_GCD (1 << 7) /* general call disable */
#define ICR_ITEIE (1 << 8) /* enable tx interrupts */
#define ICR_IRFIE (1 << 9) /* enable rx interrupts */
#define ICR_BEIE (1 << 10) /* enable bus error ints */
#define ICR_SSDIE (1 << 11) /* slave STOP detected int enable */
#define ICR_ALDIE (1 << 12) /* enable arbitration interrupt */
#define ICR_SADIE (1 << 13) /* slave address detected int enable */
#define ICR_UR (1 << 14) /* unit reset */
#define ISR_RWM (1 << 0) /* read/write mode */
#define ISR_ACKNAK (1 << 1) /* ack/nak status */
#define ISR_UB (1 << 2) /* unit busy */
#define ISR_IBB (1 << 3) /* bus busy */
#define ISR_SSD (1 << 4) /* slave stop detected */
#define ISR_ALD (1 << 5) /* arbitration loss detected */
#define ISR_ITE (1 << 6) /* tx buffer empty */
#define ISR_IRF (1 << 7) /* rx buffer full */
#define ISR_GCAD (1 << 8) /* general call address detected */
#define ISR_SAD (1 << 9) /* slave address detected */
#define ISR_BED (1 << 10) /* bus error no ACK/NAK */
/*
* Serial Audio Controller
* Serial Audio Controller - moved into sound/soc/pxa/pxa2xx-i2s.c
*/
#define SACR0 __REG(0x40400000) /* Global Control Register */
#define SACR1 __REG(0x40400004) /* Serial Audio I 2 S/MSB-Justified Control Register */
#define SASR0 __REG(0x4040000C) /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */
#define SAIMR __REG(0x40400014) /* Serial Audio Interrupt Mask Register */
#define SAICR __REG(0x40400018) /* Serial Audio Interrupt Clear Register */
#define SADIV __REG(0x40400060) /* Audio Clock Divider Register. */
#define SADR __REG(0x40400080) /* Serial Audio Data Register (TX and RX FIFO access Register). */
#define SACR0_RFTH(x) ((x) << 12) /* Rx FIFO Interrupt or DMA Trigger Threshold */
#define SACR0_TFTH(x) ((x) << 8) /* Tx FIFO Interrupt or DMA Trigger Threshold */
#define SACR0_STRF (1 << 5) /* FIFO Select for EFWR Special Function */
#define SACR0_EFWR (1 << 4) /* Enable EFWR Function */
#define SACR0_RST (1 << 3) /* FIFO, i2s Register Reset */
#define SACR0_BCKD (1 << 2) /* Bit Clock Direction */
#define SACR0_ENB (1 << 0) /* Enable I2S Link */
#define SACR1_ENLBF (1 << 5) /* Enable Loopback */
#define SACR1_DRPL (1 << 4) /* Disable Replaying Function */
#define SACR1_DREC (1 << 3) /* Disable Recording Function */
#define SACR1_AMSL (1 << 0) /* Specify Alternate Mode */
#define SASR0_I2SOFF (1 << 7) /* Controller Status */
#define SASR0_ROR (1 << 6) /* Rx FIFO Overrun */
#define SASR0_TUR (1 << 5) /* Tx FIFO Underrun */
#define SASR0_RFS (1 << 4) /* Rx FIFO Service Request */
#define SASR0_TFS (1 << 3) /* Tx FIFO Service Request */
#define SASR0_BSY (1 << 2) /* I2S Busy */
#define SASR0_RNE (1 << 1) /* Rx FIFO Not Empty */
#define SASR0_TNF (1 << 0) /* Tx FIFO Not Empty */
#define SAICR_ROR (1 << 6) /* Clear Rx FIFO Overrun Interrupt */
#define SAICR_TUR (1 << 5) /* Clear Tx FIFO Underrun Interrupt */
#define SAIMR_ROR (1 << 6) /* Enable Rx FIFO Overrun Condition Interrupt */
#define SAIMR_TUR (1 << 5) /* Enable Tx FIFO Underrun Condition Interrupt */
#define SAIMR_RFS (1 << 4) /* Enable Rx FIFO Service Interrupt */
#define SAIMR_TFS (1 << 3) /* Enable Tx FIFO Service Interrupt */
/*
* AC97 Controller registers
*/
@ -989,77 +758,6 @@
#endif
#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
/*
* UHC: USB Host Controller (OHCI-like) register definitions
*/
#define UHC_BASE_PHYS (0x4C000000)
#define UHCREV __REG(0x4C000000) /* UHC HCI Spec Revision */
#define UHCHCON __REG(0x4C000004) /* UHC Host Control Register */
#define UHCCOMS __REG(0x4C000008) /* UHC Command Status Register */
#define UHCINTS __REG(0x4C00000C) /* UHC Interrupt Status Register */
#define UHCINTE __REG(0x4C000010) /* UHC Interrupt Enable */
#define UHCINTD __REG(0x4C000014) /* UHC Interrupt Disable */
#define UHCHCCA __REG(0x4C000018) /* UHC Host Controller Comm. Area */
#define UHCPCED __REG(0x4C00001C) /* UHC Period Current Endpt Descr */
#define UHCCHED __REG(0x4C000020) /* UHC Control Head Endpt Descr */
#define UHCCCED __REG(0x4C000024) /* UHC Control Current Endpt Descr */
#define UHCBHED __REG(0x4C000028) /* UHC Bulk Head Endpt Descr */
#define UHCBCED __REG(0x4C00002C) /* UHC Bulk Current Endpt Descr */
#define UHCDHEAD __REG(0x4C000030) /* UHC Done Head */
#define UHCFMI __REG(0x4C000034) /* UHC Frame Interval */
#define UHCFMR __REG(0x4C000038) /* UHC Frame Remaining */
#define UHCFMN __REG(0x4C00003C) /* UHC Frame Number */
#define UHCPERS __REG(0x4C000040) /* UHC Periodic Start */
#define UHCLS __REG(0x4C000044) /* UHC Low Speed Threshold */
#define UHCRHDA __REG(0x4C000048) /* UHC Root Hub Descriptor A */
#define UHCRHDA_NOCP (1 << 12) /* No over current protection */
#define UHCRHDB __REG(0x4C00004C) /* UHC Root Hub Descriptor B */
#define UHCRHS __REG(0x4C000050) /* UHC Root Hub Status */
#define UHCRHPS1 __REG(0x4C000054) /* UHC Root Hub Port 1 Status */
#define UHCRHPS2 __REG(0x4C000058) /* UHC Root Hub Port 2 Status */
#define UHCRHPS3 __REG(0x4C00005C) /* UHC Root Hub Port 3 Status */
#define UHCSTAT __REG(0x4C000060) /* UHC Status Register */
#define UHCSTAT_UPS3 (1 << 16) /* USB Power Sense Port3 */
#define UHCSTAT_SBMAI (1 << 15) /* System Bus Master Abort Interrupt*/
#define UHCSTAT_SBTAI (1 << 14) /* System Bus Target Abort Interrupt*/
#define UHCSTAT_UPRI (1 << 13) /* USB Port Resume Interrupt */
#define UHCSTAT_UPS2 (1 << 12) /* USB Power Sense Port 2 */
#define UHCSTAT_UPS1 (1 << 11) /* USB Power Sense Port 1 */
#define UHCSTAT_HTA (1 << 10) /* HCI Target Abort */
#define UHCSTAT_HBA (1 << 8) /* HCI Buffer Active */
#define UHCSTAT_RWUE (1 << 7) /* HCI Remote Wake Up Event */
#define UHCHR __REG(0x4C000064) /* UHC Reset Register */
#define UHCHR_SSEP3 (1 << 11) /* Sleep Standby Enable for Port3 */
#define UHCHR_SSEP2 (1 << 10) /* Sleep Standby Enable for Port2 */
#define UHCHR_SSEP1 (1 << 9) /* Sleep Standby Enable for Port1 */
#define UHCHR_PCPL (1 << 7) /* Power control polarity low */
#define UHCHR_PSPL (1 << 6) /* Power sense polarity low */
#define UHCHR_SSE (1 << 5) /* Sleep Standby Enable */
#define UHCHR_UIT (1 << 4) /* USB Interrupt Test */
#define UHCHR_SSDC (1 << 3) /* Simulation Scale Down Clock */
#define UHCHR_CGR (1 << 2) /* Clock Generation Reset */
#define UHCHR_FHR (1 << 1) /* Force Host Controller Reset */
#define UHCHR_FSBIR (1 << 0) /* Force System Bus Iface Reset */
#define UHCHIE __REG(0x4C000068) /* UHC Interrupt Enable Register*/
#define UHCHIE_UPS3IE (1 << 14) /* Power Sense Port3 IntEn */
#define UHCHIE_UPRIE (1 << 13) /* Port Resume IntEn */
#define UHCHIE_UPS2IE (1 << 12) /* Power Sense Port2 IntEn */
#define UHCHIE_UPS1IE (1 << 11) /* Power Sense Port1 IntEn */
#define UHCHIE_TAIE (1 << 10) /* HCI Interface Transfer Abort
Interrupt Enable*/
#define UHCHIE_HBAIE (1 << 8) /* HCI Buffer Active IntEn */
#define UHCHIE_RWIE (1 << 7) /* Remote Wake-up IntEn */
#define UHCHIT __REG(0x4C00006C) /* UHC Interrupt Test register */
#endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
/* PWRMODE register M field values */
#define PWRMODE_IDLE 0x1

22
arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
View file

@ -131,6 +131,28 @@
#define CKENB __REG(0x41340010) /* B Clock Enable Register */
#define AC97_DIV __REG(0x41340014) /* AC97 clock divisor value register */
#define ACCR_XPDIS (1 << 31) /* Core PLL Output Disable */
#define ACCR_SPDIS (1 << 30) /* System PLL Output Disable */
#define ACCR_D0CS (1 << 26) /* D0 Mode Clock Select */
#define ACCR_PCCE (1 << 11) /* Power Mode Change Clock Enable */
#define ACCR_DDR_D0CS (1 << 7) /* DDR SDRAM clock frequency in D0CS (PXA31x only) */
#define ACCR_SMCFS_MASK (0x7 << 23) /* Static Memory Controller Frequency Select */
#define ACCR_SFLFS_MASK (0x3 << 18) /* Frequency Select for Internal Memory Controller */
#define ACCR_XSPCLK_MASK (0x3 << 16) /* Core Frequency during Frequency Change */
#define ACCR_HSS_MASK (0x3 << 14) /* System Bus-Clock Frequency Select */
#define ACCR_DMCFS_MASK (0x3 << 12) /* Dynamic Memory Controller Clock Frequency Select */
#define ACCR_XN_MASK (0x7 << 8) /* Core PLL Turbo-Mode-to-Run-Mode Ratio */
#define ACCR_XL_MASK (0x1f) /* Core PLL Run-Mode-to-Oscillator Ratio */
#define ACCR_SMCFS(x) (((x) & 0x7) << 23)
#define ACCR_SFLFS(x) (((x) & 0x3) << 18)
#define ACCR_XSPCLK(x) (((x) & 0x3) << 16)
#define ACCR_HSS(x) (((x) & 0x3) << 14)
#define ACCR_DMCFS(x) (((x) & 0x3) << 12)
#define ACCR_XN(x) (((x) & 0x7) << 8)
#define ACCR_XL(x) ((x) & 0x1f)
/*
* Clock Enable Bit
*/

42
arch/arm/mach-pxa/include/mach/spitz.h
View file

@ -16,6 +16,7 @@
#endif
#include <linux/fb.h>
#include <linux/gpio.h>
/* Spitz/Akita GPIOs */
@ -100,13 +101,24 @@
#define SPITZ_SCP_JK_A SCOOP_GPCR_PA18 /* Low */
#define SPITZ_SCP_ADC_TEMP_ON SCOOP_GPCR_PA19 /* Low */
#define SPITZ_SCP_IO_DIR (SPITZ_SCP_LED_GREEN | SPITZ_SCP_JK_B | SPITZ_SCP_CHRG_ON | \
SPITZ_SCP_MUTE_L | SPITZ_SCP_MUTE_R | SPITZ_SCP_LED_ORANGE | \
#define SPITZ_SCP_IO_DIR (SPITZ_SCP_JK_B | SPITZ_SCP_CHRG_ON | \
SPITZ_SCP_MUTE_L | SPITZ_SCP_MUTE_R | \
SPITZ_SCP_CF_POWER | SPITZ_SCP_JK_A | SPITZ_SCP_ADC_TEMP_ON)
#define SPITZ_SCP_IO_OUT (SPITZ_SCP_CHRG_ON | SPITZ_SCP_MUTE_L | SPITZ_SCP_MUTE_R)
#define SPITZ_SCP_SUS_CLR (SPITZ_SCP_MUTE_L | SPITZ_SCP_MUTE_R | SPITZ_SCP_JK_A | SPITZ_SCP_ADC_TEMP_ON)
#define SPITZ_SCP_SUS_SET 0
#define SPITZ_SCP_GPIO_BASE (NR_BUILTIN_GPIO)
#define SPITZ_GPIO_LED_GREEN (SPITZ_SCP_GPIO_BASE + 0)
#define SPITZ_GPIO_JK_B (SPITZ_SCP_GPIO_BASE + 1)
#define SPITZ_GPIO_CHRG_ON (SPITZ_SCP_GPIO_BASE + 2)
#define SPITZ_GPIO_MUTE_L (SPITZ_SCP_GPIO_BASE + 3)
#define SPITZ_GPIO_MUTE_R (SPITZ_SCP_GPIO_BASE + 4)
#define SPITZ_GPIO_CF_POWER (SPITZ_SCP_GPIO_BASE + 5)
#define SPITZ_GPIO_LED_ORANGE (SPITZ_SCP_GPIO_BASE + 6)
#define SPITZ_GPIO_JK_A (SPITZ_SCP_GPIO_BASE + 7)
#define SPITZ_GPIO_ADC_TEMP_ON (SPITZ_SCP_GPIO_BASE + 8)
/* Spitz Scoop Device (No. 2) GPIOs */
/* Suspend States in comments */
#define SPITZ_SCP2_IR_ON SCOOP_GPCR_PA11 /* High */
@ -119,15 +131,36 @@
#define SPITZ_SCP2_BACKLIGHT_ON SCOOP_GPCR_PA18 /* Low */
#define SPITZ_SCP2_MIC_BIAS SCOOP_GPCR_PA19 /* Low */
#define SPITZ_SCP2_IO_DIR (SPITZ_SCP2_IR_ON | SPITZ_SCP2_AKIN_PULLUP | SPITZ_SCP2_RESERVED_1 | \
#define SPITZ_SCP2_IO_DIR (SPITZ_SCP2_AKIN_PULLUP | SPITZ_SCP2_RESERVED_1 | \
SPITZ_SCP2_RESERVED_2 | SPITZ_SCP2_RESERVED_3 | SPITZ_SCP2_RESERVED_4 | \
SPITZ_SCP2_BACKLIGHT_CONT | SPITZ_SCP2_BACKLIGHT_ON | SPITZ_SCP2_MIC_BIAS)
#define SPITZ_SCP2_IO_OUT (SPITZ_SCP2_IR_ON | SPITZ_SCP2_AKIN_PULLUP | SPITZ_SCP2_RESERVED_1)
#define SPITZ_SCP2_IO_OUT (SPITZ_SCP2_AKIN_PULLUP | SPITZ_SCP2_RESERVED_1)
#define SPITZ_SCP2_SUS_CLR (SPITZ_SCP2_RESERVED_2 | SPITZ_SCP2_RESERVED_3 | SPITZ_SCP2_RESERVED_4 | \
SPITZ_SCP2_BACKLIGHT_CONT | SPITZ_SCP2_BACKLIGHT_ON | SPITZ_SCP2_MIC_BIAS)
#define SPITZ_SCP2_SUS_SET (SPITZ_SCP2_IR_ON | SPITZ_SCP2_RESERVED_1)
#define SPITZ_SCP2_GPIO_BASE (NR_BUILTIN_GPIO + 12)
#define SPITZ_GPIO_IR_ON (SPITZ_SCP2_GPIO_BASE + 0)
#define SPITZ_GPIO_AKIN_PULLUP (SPITZ_SCP2_GPIO_BASE + 1
#define SPITZ_GPIO_RESERVED_1 (SPITZ_SCP2_GPIO_BASE + 2)
#define SPITZ_GPIO_RESERVED_2 (SPITZ_SCP2_GPIO_BASE + 3)
#define SPITZ_GPIO_RESERVED_3 (SPITZ_SCP2_GPIO_BASE + 4)
#define SPITZ_GPIO_RESERVED_4 (SPITZ_SCP2_GPIO_BASE + 5)
#define SPITZ_GPIO_BACKLIGHT_CONT (SPITZ_SCP2_GPIO_BASE + 6)
#define SPITZ_GPIO_BACKLIGHT_ON (SPITZ_SCP2_GPIO_BASE + 7)
#define SPITZ_GPIO_MIC_BIAS (SPITZ_SCP2_GPIO_BASE + 8)
/* Akita IO Expander GPIOs */
#define AKITA_IOEXP_GPIO_BASE (NR_BUILTIN_GPIO + 12)
#define AKITA_GPIO_RESERVED_0 (AKITA_IOEXP_GPIO_BASE + 0)
#define AKITA_GPIO_RESERVED_1 (AKITA_IOEXP_GPIO_BASE + 1)
#define AKITA_GPIO_MIC_BIAS (AKITA_IOEXP_GPIO_BASE + 2)
#define AKITA_GPIO_BACKLIGHT_ON (AKITA_IOEXP_GPIO_BASE + 3)
#define AKITA_GPIO_BACKLIGHT_CONT (AKITA_IOEXP_GPIO_BASE + 4)
#define AKITA_GPIO_AKIN_PULLUP (AKITA_IOEXP_GPIO_BASE + 5)
#define AKITA_GPIO_IR_ON (AKITA_IOEXP_GPIO_BASE + 6)
#define AKITA_GPIO_RESERVED_7 (AKITA_IOEXP_GPIO_BASE + 7)
/* Spitz IRQ Definitions */
@ -154,5 +187,4 @@
*/
extern struct platform_device spitzscoop_device;
extern struct platform_device spitzscoop2_device;
extern struct platform_device spitzssp_device;
extern struct sharpsl_charger_machinfo spitz_pm_machinfo;

24
arch/arm/mach-pxa/include/mach/ssp.h
View file

@ -20,6 +20,7 @@
#define __ASM_ARCH_SSP_H
#include <linux/list.h>
#include <linux/io.h>
enum pxa_ssp_type {
SSP_UNDEFINED = 0,
@ -78,6 +79,29 @@ int ssp_init(struct ssp_dev *dev, u32 port, u32 init_flags);
int ssp_config(struct ssp_dev *dev, u32 mode, u32 flags, u32 psp_flags, u32 speed);
void ssp_exit(struct ssp_dev *dev);
/**
* ssp_write_reg - Write to a SSP register
*
* @dev: SSP device to access
* @reg: Register to write to
* @val: Value to be written.
*/
static inline void ssp_write_reg(struct ssp_device *dev, u32 reg, u32 val)
{
__raw_writel(val, dev->mmio_base + reg);
}
/**
* ssp_read_reg - Read from a SSP register
*
* @dev: SSP device to access
* @reg: Register to read from
*/
static inline u32 ssp_read_reg(struct ssp_device *dev, u32 reg)
{
return __raw_readl(dev->mmio_base + reg);
}
struct ssp_device *ssp_request(int port, const char *label);
void ssp_free(struct ssp_device *);
#endif /* __ASM_ARCH_SSP_H */

84
arch/arm/mach-pxa/include/mach/trizeps4.h
View file

@ -17,11 +17,16 @@
#define TRIZEPS4_PIC_PHYS (PXA_CS3_PHYS) /* Logic chip on ConXS-Board */
#define TRIZEPS4_SDRAM_BASE 0xa0000000 /* SDRAM region */
#define TRIZEPS4_CFSR_PHYS (PXA_CS3_PHYS) /* Logic chip on ConXS-Board CSFR register */
#define TRIZEPS4_BOCR_PHYS (PXA_CS3_PHYS+0x02000000) /* Logic chip on ConXS-Board BOCR register */
#define TRIZEPS4_IRCR_PHYS (PXA_CS3_PHYS+0x02400000) /* Logic chip on ConXS-Board IRCR register*/
#define TRIZEPS4_UPSR_PHYS (PXA_CS3_PHYS+0x02800000) /* Logic chip on ConXS-Board UPSR register*/
#define TRIZEPS4_DICR_PHYS (PXA_CS3_PHYS+0x03800000) /* Logic chip on ConXS-Board DICR register*/
/* Logic on ConXS-board CSFR register*/
#define TRIZEPS4_CFSR_PHYS (PXA_CS3_PHYS)
/* Logic on ConXS-board BOCR register*/
#define TRIZEPS4_BOCR_PHYS (PXA_CS3_PHYS+0x02000000)
/* Logic on ConXS-board IRCR register*/
#define TRIZEPS4_IRCR_PHYS (PXA_CS3_PHYS+0x02400000)
/* Logic on ConXS-board UPSR register*/
#define TRIZEPS4_UPSR_PHYS (PXA_CS3_PHYS+0x02800000)
/* Logic on ConXS-board DICR register*/
#define TRIZEPS4_DICR_PHYS (PXA_CS3_PHYS+0x03800000)
/* virtual memory regions */
#define TRIZEPS4_DISK_VIRT 0xF0000000 /* Disk On Chip region */
@ -54,6 +59,15 @@
#define GPIO_MMC_DET 12
#define TRIZEPS4_MMC_IRQ IRQ_GPIO(GPIO_MMC_DET)
/* DOC NAND chip */
#define GPIO_DOC_LOCK 94
#define GPIO_DOC_IRQ 93
#define TRIZEPS4_DOC_IRQ IRQ_GPIO(GPIO_DOC_IRQ)
/* SPI interface */
#define GPIO_SPI 53
#define TRIZEPS4_SPI_IRQ IRQ_GPIO(GPIO_SPI)
/* LEDS using tx2 / rx2 */
#define GPIO_SYS_BUSY_LED 46
#define GPIO_HEARTBEAT_LED 47
@ -62,24 +76,66 @@
#define GPIO_PIC 0
#define TRIZEPS4_PIC_IRQ IRQ_GPIO(GPIO_PIC)
#define CFSR_P2V(x) ((x) - TRIZEPS4_CFSR_PHYS + TRIZEPS4_CFSR_VIRT)
#define CFSR_V2P(x) ((x) - TRIZEPS4_CFSR_VIRT + TRIZEPS4_CFSR_PHYS)
#ifdef CONFIG_MACH_TRIZEPS_CONXS
/* for CONXS base board define these registers */
#define CFSR_P2V(x) ((x) - TRIZEPS4_CFSR_PHYS + TRIZEPS4_CFSR_VIRT)
#define CFSR_V2P(x) ((x) - TRIZEPS4_CFSR_VIRT + TRIZEPS4_CFSR_PHYS)
#define BCR_P2V(x) ((x) - TRIZEPS4_BOCR_PHYS + TRIZEPS4_BOCR_VIRT)
#define BCR_V2P(x) ((x) - TRIZEPS4_BOCR_VIRT + TRIZEPS4_BOCR_PHYS)
#define BCR_P2V(x) ((x) - TRIZEPS4_BOCR_PHYS + TRIZEPS4_BOCR_VIRT)
#define BCR_V2P(x) ((x) - TRIZEPS4_BOCR_VIRT + TRIZEPS4_BOCR_PHYS)
#define DCR_P2V(x) ((x) - TRIZEPS4_DICR_PHYS + TRIZEPS4_DICR_VIRT)
#define DCR_V2P(x) ((x) - TRIZEPS4_DICR_VIRT + TRIZEPS4_DICR_PHYS)
#define DCR_P2V(x) ((x) - TRIZEPS4_DICR_PHYS + TRIZEPS4_DICR_VIRT)
#define DCR_V2P(x) ((x) - TRIZEPS4_DICR_VIRT + TRIZEPS4_DICR_PHYS)
#define IRCR_P2V(x) ((x) - TRIZEPS4_IRCR_PHYS + TRIZEPS4_IRCR_VIRT)
#define IRCR_V2P(x) ((x) - TRIZEPS4_IRCR_VIRT + TRIZEPS4_IRCR_PHYS)
#ifndef __ASSEMBLY__
#define ConXS_CFSR (*((volatile unsigned short *)CFSR_P2V(0x0C000000)))
#define ConXS_BCR (*((volatile unsigned short *)BCR_P2V(0x0E000000)))
#define ConXS_DCR (*((volatile unsigned short *)DCR_P2V(0x0F800000)))
static inline unsigned short CFSR_readw(void)
{
/* [Compact Flash Status Register] is read only */
return *((unsigned short *)CFSR_P2V(0x0C000000));
}
static inline void BCR_writew(unsigned short value)
{
/* [Board Control Regsiter] is write only */
*((unsigned short *)BCR_P2V(0x0E000000)) = value;
}
static inline void DCR_writew(unsigned short value)
{
/* [Display Control Register] is write only */
*((unsigned short *)DCR_P2V(0x0E000000)) = value;
}
static inline void IRCR_writew(unsigned short value)
{
/* [InfraRed data Control Register] is write only */
*((unsigned short *)IRCR_P2V(0x0E000000)) = value;
}
#else
#define ConXS_CFSR CFSR_P2V(0x0C000000)
#define ConXS_BCR BCR_P2V(0x0E000000)
#define ConXS_DCR DCR_P2V(0x0F800000)
#define ConXS_IRCR IRCR_P2V(0x0F800000)
#endif
#else
/* for whatever baseboard define function registers */
static inline unsigned short CFSR_readw(void)
{
return 0;
}
static inline void BCR_writew(unsigned short value)
{
;
}
static inline void DCR_writew(unsigned short value)
{
;
}
static inline void IRCR_writew(unsigned short value)
{
;
}
#endif /* CONFIG_MACH_TRIZEPS_CONXS */
#define ConXS_CFSR_BVD_MASK 0x0003
#define ConXS_CFSR_BVD1 (1 << 0)

96
arch/arm/mach-pxa/include/mach/viper.h Normal file
View file

@ -0,0 +1,96 @@
/*
* arch/arm/mach-pxa/include/mach/viper.h
*
* Author: Ian Campbell
* Created: Feb 03, 2003
* Copyright: Arcom Control Systems.
*
* Maintained by Marc Zyngier <maz@misterjones.org>
* <marc.zyngier@altran.com>
*
* Created based on lubbock.h:
* Author: Nicolas Pitre
* Created: Jun 15, 2001
* Copyright: MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef ARCH_VIPER_H
#define ARCH_VIPER_H
#define VIPER_BOOT_PHYS PXA_CS0_PHYS
#define VIPER_FLASH_PHYS PXA_CS1_PHYS
#define VIPER_ETH_PHYS PXA_CS2_PHYS
#define VIPER_USB_PHYS PXA_CS3_PHYS
#define VIPER_ETH_DATA_PHYS PXA_CS4_PHYS
#define VIPER_CPLD_PHYS PXA_CS5_PHYS
#define VIPER_CPLD_BASE (0xf0000000)
#define VIPER_PC104IO_BASE (0xf1000000)
#define VIPER_USB_BASE (0xf1800000)
#define VIPER_ETH_GPIO (0)
#define VIPER_CPLD_GPIO (1)
#define VIPER_USB_GPIO (2)
#define VIPER_UARTA_GPIO (4)
#define VIPER_UARTB_GPIO (3)
#define VIPER_CF_CD_GPIO (32)
#define VIPER_CF_RDY_GPIO (8)
#define VIPER_BCKLIGHT_EN_GPIO (9)
#define VIPER_LCD_EN_GPIO (10)
#define VIPER_PSU_DATA_GPIO (6)
#define VIPER_PSU_CLK_GPIO (11)
#define VIPER_UART_SHDN_GPIO (12)
#define VIPER_BRIGHTNESS_GPIO (16)
#define VIPER_PSU_nCS_LD_GPIO (19)
#define VIPER_UPS_GPIO (20)
#define VIPER_CF_POWER_GPIO (82)
#define VIPER_TPM_I2C_SDA_GPIO (26)
#define VIPER_TPM_I2C_SCL_GPIO (27)
#define VIPER_RTC_I2C_SDA_GPIO (83)
#define VIPER_RTC_I2C_SCL_GPIO (84)
#define VIPER_CPLD_P2V(x) ((x) - VIPER_CPLD_PHYS + VIPER_CPLD_BASE)
#define VIPER_CPLD_V2P(x) ((x) - VIPER_CPLD_BASE + VIPER_CPLD_PHYS)
#ifndef __ASSEMBLY__
# define __VIPER_CPLD_REG(x) (*((volatile u16 *)VIPER_CPLD_P2V(x)))
#endif
/* board level registers in the CPLD: (offsets from CPLD_BASE) ... */
/* ... Physical addresses */
#define _VIPER_LO_IRQ_STATUS (VIPER_CPLD_PHYS + 0x100000)
#define _VIPER_ICR_PHYS (VIPER_CPLD_PHYS + 0x100002)
#define _VIPER_HI_IRQ_STATUS (VIPER_CPLD_PHYS + 0x100004)
#define _VIPER_VERSION_PHYS (VIPER_CPLD_PHYS + 0x100006)
#define VIPER_UARTA_PHYS (VIPER_CPLD_PHYS + 0x300010)
#define VIPER_UARTB_PHYS (VIPER_CPLD_PHYS + 0x300000)
#define _VIPER_SRAM_BASE (VIPER_CPLD_PHYS + 0x800000)
/* ... Virtual addresses */
#define VIPER_LO_IRQ_STATUS __VIPER_CPLD_REG(_VIPER_LO_IRQ_STATUS)
#define VIPER_HI_IRQ_STATUS __VIPER_CPLD_REG(_VIPER_HI_IRQ_STATUS)
#define VIPER_VERSION __VIPER_CPLD_REG(_VIPER_VERSION_PHYS)
#define VIPER_ICR __VIPER_CPLD_REG(_VIPER_ICR_PHYS)
/* Decode VIPER_VERSION register */
#define VIPER_CPLD_REVISION(x) (((x) >> 5) & 0x7)
#define VIPER_BOARD_VERSION(x) (((x) >> 3) & 0x3)
#define VIPER_BOARD_ISSUE(x) (((x) >> 0) & 0x7)
/* Interrupt and Configuration Register (VIPER_ICR) */
/* This is a write only register. Only CF_RST is used under Linux */
extern void viper_cf_rst(int state);
#define VIPER_ICR_RETRIG (1 << 0)
#define VIPER_ICR_AUTO_CLR (1 << 1)
#define VIPER_ICR_R_DIS (1 << 2)
#define VIPER_ICR_CF_RST (1 << 3)
#endif

2
arch/arm/mach-pxa/irq.c
View file

@ -57,7 +57,7 @@ void __init pxa_init_irq(int irq_nr, set_wake_t fn)
pxa_internal_irq_nr = irq_nr;
for (irq = 0; irq < irq_nr; irq += 32) {
for (irq = PXA_IRQ(0); irq < PXA_IRQ(irq_nr); irq += 32) {
_ICMR(irq) = 0; /* disable all IRQs */
_ICLR(irq) = 0; /* all IRQs are IRQ, not FIQ */
}

134
arch/arm/mach-pxa/leds-trizeps4.c
View file

@ -1,134 +0,0 @@
/*
* linux/arch/arm/mach-pxa/leds-trizeps4.c
*
* Author: Jürgen Schindele
* Created: 20 02, 2006
* Copyright: Jürgen Schindele
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/init.h>
#include <mach/hardware.h>
#include <asm/system.h>
#include <asm/types.h>
#include <asm/leds.h>
#include <mach/pxa-regs.h>
#include <mach/pxa2xx-gpio.h>
#include <mach/trizeps4.h>
#include "leds.h"
#define LED_STATE_ENABLED 1
#define LED_STATE_CLAIMED 2
#define SYS_BUSY 0x01
#define HEARTBEAT 0x02
#define BLINK 0x04
static unsigned int led_state;
static unsigned int hw_led_state;
void trizeps4_leds_event(led_event_t evt)
{
unsigned long flags;
local_irq_save(flags);
switch (evt) {
case led_start:
hw_led_state = 0;
pxa_gpio_mode( GPIO_SYS_BUSY_LED | GPIO_OUT); /* LED1 */
pxa_gpio_mode( GPIO_HEARTBEAT_LED | GPIO_OUT); /* LED2 */
led_state = LED_STATE_ENABLED;
break;
case led_stop:
led_state &= ~LED_STATE_ENABLED;
break;
case led_claim:
led_state |= LED_STATE_CLAIMED;
hw_led_state = 0;
break;
case led_release:
led_state &= ~LED_STATE_CLAIMED;
hw_led_state = 0;
break;
#ifdef CONFIG_LEDS_TIMER
case led_timer:
hw_led_state ^= HEARTBEAT;
break;
#endif
#ifdef CONFIG_LEDS_CPU
case led_idle_start:
hw_led_state &= ~SYS_BUSY;
break;
case led_idle_end:
hw_led_state |= SYS_BUSY;
break;
#endif
case led_halted:
break;
case led_green_on:
hw_led_state |= BLINK;
break;
case led_green_off:
hw_led_state &= ~BLINK;
break;
case led_amber_on:
break;
case led_amber_off:
break;
case led_red_on:
break;
case led_red_off:
break;
default:
break;
}
if (led_state & LED_STATE_ENABLED) {
switch (hw_led_state) {
case 0:
GPSR(GPIO_SYS_BUSY_LED) |= GPIO_bit(GPIO_SYS_BUSY_LED);
GPSR(GPIO_HEARTBEAT_LED) |= GPIO_bit(GPIO_HEARTBEAT_LED);
break;
case 1:
GPCR(GPIO_SYS_BUSY_LED) |= GPIO_bit(GPIO_SYS_BUSY_LED);
GPSR(GPIO_HEARTBEAT_LED) |= GPIO_bit(GPIO_HEARTBEAT_LED);
break;
case 2:
GPSR(GPIO_SYS_BUSY_LED) |= GPIO_bit(GPIO_SYS_BUSY_LED);
GPCR(GPIO_HEARTBEAT_LED) |= GPIO_bit(GPIO_HEARTBEAT_LED);
break;
case 3:
GPCR(GPIO_SYS_BUSY_LED) |= GPIO_bit(GPIO_SYS_BUSY_LED);
GPCR(GPIO_HEARTBEAT_LED) |= GPIO_bit(GPIO_HEARTBEAT_LED);
break;
}
}
else {
/* turn all off */
GPSR(GPIO_SYS_BUSY_LED) |= GPIO_bit(GPIO_SYS_BUSY_LED);
GPSR(GPIO_HEARTBEAT_LED) |= GPIO_bit(GPIO_HEARTBEAT_LED);
}
local_irq_restore(flags);
}

2
arch/arm/mach-pxa/leds.c
View file

@ -24,8 +24,6 @@ pxa_leds_init(void)
leds_event = mainstone_leds_event;
if (machine_is_pxa_idp())
leds_event = idp_leds_event;
if (machine_is_trizeps4())
leds_event = trizeps4_leds_event;
leds_event(led_start);
return 0;

205
arch/arm/mach-pxa/littleton.c
View file

@ -20,6 +20,7 @@
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/spi/spi.h>
#include <linux/smc91x.h>
#include <asm/types.h>
@ -38,6 +39,7 @@
#include <mach/gpio.h>
#include <mach/pxafb.h>
#include <mach/ssp.h>
#include <mach/pxa2xx_spi.h>
#include <mach/pxa27x_keypad.h>
#include <mach/pxa3xx_nand.h>
#include <mach/littleton.h>
@ -72,8 +74,8 @@ static mfp_cfg_t littleton_mfp_cfg[] __initdata = {
/* SSP2 */
GPIO25_SSP2_SCLK,
GPIO17_SSP2_FRM,
GPIO27_SSP2_TXD,
GPIO17_GPIO, /* SFRM as chip-select */
/* Debug Ethernet */
GPIO90_GPIO,
@ -123,160 +125,6 @@ static struct platform_device smc91x_device = {
};
#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
/* use bit 30, 31 as the indicator of command parameter number */
#define CMD0(x) ((0x00000000) | ((x) << 9))
#define CMD1(x, x1) ((0x40000000) | ((x) << 9) | 0x100 | (x1))
#define CMD2(x, x1, x2) ((0x80000000) | ((x) << 18) | 0x20000 |\
((x1) << 9) | 0x100 | (x2))
static uint32_t lcd_panel_reset[] = {
CMD0(0x1), /* reset */
CMD0(0x0), /* nop */
CMD0(0x0), /* nop */
CMD0(0x0), /* nop */
};
static uint32_t lcd_panel_on[] = {
CMD0(0x29), /* Display ON */
CMD2(0xB8, 0xFF, 0xF9), /* Output Control */
CMD0(0x11), /* Sleep out */
CMD1(0xB0, 0x16), /* Wake */
};
static uint32_t lcd_panel_off[] = {
CMD0(0x28), /* Display OFF */
CMD2(0xB8, 0x80, 0x02), /* Output Control */
CMD0(0x10), /* Sleep in */
CMD1(0xB0, 0x00), /* Deep stand by in */
};
static uint32_t lcd_vga_pass_through[] = {
CMD1(0xB0, 0x16),
CMD1(0xBC, 0x80),
CMD1(0xE1, 0x00),
CMD1(0x36, 0x50),
CMD1(0x3B, 0x00),
};
static uint32_t lcd_qvga_pass_through[] = {
CMD1(0xB0, 0x16),
CMD1(0xBC, 0x81),
CMD1(0xE1, 0x00),
CMD1(0x36, 0x50),
CMD1(0x3B, 0x22),
};
static uint32_t lcd_vga_transfer[] = {
CMD1(0xcf, 0x02), /* Blanking period control (1) */
CMD2(0xd0, 0x08, 0x04), /* Blanking period control (2) */
CMD1(0xd1, 0x01), /* CKV timing control on/off */
CMD2(0xd2, 0x14, 0x00), /* CKV 1,2 timing control */
CMD2(0xd3, 0x1a, 0x0f), /* OEV timing control */
CMD2(0xd4, 0x1f, 0xaf), /* ASW timing control (1) */
CMD1(0xd5, 0x14), /* ASW timing control (2) */
CMD0(0x21), /* Invert for normally black display */
CMD0(0x29), /* Display on */
};
static uint32_t lcd_qvga_transfer[] = {
CMD1(0xd6, 0x02), /* Blanking period control (1) */
CMD2(0xd7, 0x08, 0x04), /* Blanking period control (2) */
CMD1(0xd8, 0x01), /* CKV timing control on/off */
CMD2(0xd9, 0x00, 0x08), /* CKV 1,2 timing control */
CMD2(0xde, 0x05, 0x0a), /* OEV timing control */
CMD2(0xdf, 0x0a, 0x19), /* ASW timing control (1) */
CMD1(0xe0, 0x0a), /* ASW timing control (2) */
CMD0(0x21), /* Invert for normally black display */
CMD0(0x29), /* Display on */
};
static uint32_t lcd_panel_config[] = {
CMD2(0xb8, 0xff, 0xf9), /* Output control */
CMD0(0x11), /* sleep out */
CMD1(0xba, 0x01), /* Display mode (1) */
CMD1(0xbb, 0x00), /* Display mode (2) */
CMD1(0x3a, 0x60), /* Display mode 18-bit RGB */
CMD1(0xbf, 0x10), /* Drive system change control */
CMD1(0xb1, 0x56), /* Booster operation setup */
CMD1(0xb2, 0x33), /* Booster mode setup */
CMD1(0xb3, 0x11), /* Booster frequency setup */
CMD1(0xb4, 0x02), /* Op amp/system clock */
CMD1(0xb5, 0x35), /* VCS voltage */
CMD1(0xb6, 0x40), /* VCOM voltage */
CMD1(0xb7, 0x03), /* External display signal */
CMD1(0xbd, 0x00), /* ASW slew rate */
CMD1(0xbe, 0x00), /* Dummy data for QuadData operation */
CMD1(0xc0, 0x11), /* Sleep out FR count (A) */
CMD1(0xc1, 0x11), /* Sleep out FR count (B) */
CMD1(0xc2, 0x11), /* Sleep out FR count (C) */
CMD2(0xc3, 0x20, 0x40), /* Sleep out FR count (D) */
CMD2(0xc4, 0x60, 0xc0), /* Sleep out FR count (E) */
CMD2(0xc5, 0x10, 0x20), /* Sleep out FR count (F) */
CMD1(0xc6, 0xc0), /* Sleep out FR count (G) */
CMD2(0xc7, 0x33, 0x43), /* Gamma 1 fine tuning (1) */
CMD1(0xc8, 0x44), /* Gamma 1 fine tuning (2) */
CMD1(0xc9, 0x33), /* Gamma 1 inclination adjustment */
CMD1(0xca, 0x00), /* Gamma 1 blue offset adjustment */
CMD2(0xec, 0x01, 0xf0), /* Horizontal clock cycles */
};
static void ssp_reconfig(struct ssp_dev *dev, int nparam)
{
static int last_nparam = -1;
/* check if it is necessary to re-config SSP */
if (nparam == last_nparam)
return;
ssp_disable(dev);
ssp_config(dev, (nparam == 2) ? 0x0010058a : 0x00100581, 0x18, 0, 0);
last_nparam = nparam;
}
static void ssp_send_cmd(uint32_t *cmd, int num)
{
static int ssp_initialized;
static struct ssp_dev ssp2;
int i;
if (!ssp_initialized) {
ssp_init(&ssp2, 2, SSP_NO_IRQ);
ssp_initialized = 1;
}
clk_enable(ssp2.ssp->clk);
for (i = 0; i < num; i++, cmd++) {
ssp_reconfig(&ssp2, (*cmd >> 30) & 0x3);
ssp_write_word(&ssp2, *cmd & 0x3fffffff);
/* FIXME: ssp_flush() is mandatory here to work */
ssp_flush(&ssp2);
}
clk_disable(ssp2.ssp->clk);
}
static void littleton_lcd_power(int on, struct fb_var_screeninfo *var)
{
if (on) {
ssp_send_cmd(ARRAY_AND_SIZE(lcd_panel_on));
ssp_send_cmd(ARRAY_AND_SIZE(lcd_panel_reset));
if (var->xres > 240) {
/* VGA */
ssp_send_cmd(ARRAY_AND_SIZE(lcd_vga_pass_through));
ssp_send_cmd(ARRAY_AND_SIZE(lcd_panel_config));
ssp_send_cmd(ARRAY_AND_SIZE(lcd_vga_transfer));
} else {
/* QVGA */
ssp_send_cmd(ARRAY_AND_SIZE(lcd_qvga_pass_through));
ssp_send_cmd(ARRAY_AND_SIZE(lcd_panel_config));
ssp_send_cmd(ARRAY_AND_SIZE(lcd_qvga_transfer));
}
} else
ssp_send_cmd(ARRAY_AND_SIZE(lcd_panel_off));
}
static struct pxafb_mode_info tpo_tdo24mtea1_modes[] = {
[0] = {
/* VGA */
@ -312,7 +160,6 @@ static struct pxafb_mach_info littleton_lcd_info = {
.modes = tpo_tdo24mtea1_modes,
.num_modes = 2,
.lcd_conn = LCD_COLOR_TFT_16BPP,
.pxafb_lcd_power = littleton_lcd_power,
};
static void littleton_init_lcd(void)
@ -323,6 +170,51 @@ static void littleton_init_lcd(void)
static inline void littleton_init_lcd(void) {};
#endif /* CONFIG_FB_PXA || CONFIG_FB_PXA_MODULE */
#if defined(CONFIG_SPI_PXA2XX) || defined(CONFIG_SPI_PXA2XX_MODULE)
static struct pxa2xx_spi_master littleton_spi_info = {
.num_chipselect = 1,
};
static void littleton_tdo24m_cs(u32 cmd)
{
gpio_set_value(LITTLETON_GPIO_LCD_CS, !(cmd == PXA2XX_CS_ASSERT));
}
static struct pxa2xx_spi_chip littleton_tdo24m_chip = {
.rx_threshold = 1,
.tx_threshold = 1,
.cs_control = littleton_tdo24m_cs,
};
static struct spi_board_info littleton_spi_devices[] __initdata = {
{
.modalias = "tdo24m",
.max_speed_hz = 1000000,
.bus_num = 2,
.chip_select = 0,
.controller_data= &littleton_tdo24m_chip,
},
};
static void __init littleton_init_spi(void)
{
int err;
err = gpio_request(LITTLETON_GPIO_LCD_CS, "LCD_CS");
if (err) {
pr_warning("failed to request GPIO for LCS CS\n");
return;
}
gpio_direction_output(LITTLETON_GPIO_LCD_CS, 1);
pxa2xx_set_spi_info(2, &littleton_spi_info);
spi_register_board_info(ARRAY_AND_SIZE(littleton_spi_devices));
}
#else
static inline void littleton_init_spi(void) {}
#endif
#if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULE)
static unsigned int littleton_matrix_key_map[] = {
/* KEY(row, col, key_code) */
@ -433,6 +325,7 @@ static void __init littleton_init(void)
*/
platform_device_register(&smc91x_device);
littleton_init_spi();
littleton_init_lcd();
littleton_init_keypad();
littleton_init_nand();

99
arch/arm/mach-pxa/lpd270.c
View file

@ -40,7 +40,7 @@
#include <mach/pxa-regs.h>
#include <mach/pxa2xx-regs.h>
#include <mach/pxa2xx-gpio.h>
#include <mach/mfp-pxa27x.h>
#include <mach/lpd270.h>
#include <mach/audio.h>
#include <mach/pxafb.h>
@ -51,6 +51,43 @@
#include "generic.h"
#include "devices.h"
static unsigned long lpd270_pin_config[] __initdata = {
/* Chip Selects */
GPIO15_nCS_1, /* Mainboard Flash */
GPIO78_nCS_2, /* CPLD + Ethernet */
/* LCD - 16bpp Active TFT */
GPIO58_LCD_LDD_0,
GPIO59_LCD_LDD_1,
GPIO60_LCD_LDD_2,
GPIO61_LCD_LDD_3,
GPIO62_LCD_LDD_4,
GPIO63_LCD_LDD_5,
GPIO64_LCD_LDD_6,
GPIO65_LCD_LDD_7,
GPIO66_LCD_LDD_8,
GPIO67_LCD_LDD_9,
GPIO68_LCD_LDD_10,
GPIO69_LCD_LDD_11,
GPIO70_LCD_LDD_12,
GPIO71_LCD_LDD_13,
GPIO72_LCD_LDD_14,
GPIO73_LCD_LDD_15,
GPIO74_LCD_FCLK,
GPIO75_LCD_LCLK,
GPIO76_LCD_PCLK,
GPIO77_LCD_BIAS,
GPIO16_PWM0_OUT, /* Backlight */
/* USB Host */
GPIO88_USBH1_PWR,
GPIO89_USBH1_PEN,
/* AC97 */
GPIO45_AC97_SYSCLK,
GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH,
};
static unsigned int lpd270_irq_enabled;
@ -88,8 +125,7 @@ static void lpd270_irq_handler(unsigned int irq, struct irq_desc *desc)
GEDR(0) = GPIO_bit(0); /* clear useless edge notification */
if (likely(pending)) {
irq = LPD270_IRQ(0) + __ffs(pending);
desc = irq_desc + irq;
desc_handle_irq(irq, desc);
generic_handle_irq(irq);
pending = __raw_readw(LPD270_INT_STATUS) &
lpd270_irq_enabled;
@ -265,8 +301,8 @@ static struct pxafb_mode_info sharp_lq057q3dc02_mode = {
static struct pxafb_mach_info sharp_lq057q3dc02 = {
.modes = &sharp_lq057q3dc02_mode,
.num_modes = 1,
.lccr0 = 0x07800080,
.lccr3 = 0x00400000,
.lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
LCD_ALTERNATE_MAPPING,
};
/* 12.1" TFT SVGA (LoLo display number 2) */
@ -287,8 +323,8 @@ static struct pxafb_mode_info sharp_lq121s1dg31_mode = {
static struct pxafb_mach_info sharp_lq121s1dg31 = {
.modes = &sharp_lq121s1dg31_mode,
.num_modes = 1,
.lccr0 = 0x07800080,
.lccr3 = 0x00400000,
.lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
LCD_ALTERNATE_MAPPING,
};
/* 3.6" TFT QVGA (LoLo display number 3) */
@ -309,8 +345,8 @@ static struct pxafb_mode_info sharp_lq036q1da01_mode = {
static struct pxafb_mach_info sharp_lq036q1da01 = {
.modes = &sharp_lq036q1da01_mode,
.num_modes = 1,
.lccr0 = 0x07800080,
.lccr3 = 0x00400000,
.lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
LCD_ALTERNATE_MAPPING,
};
/* 6.4" TFT VGA (LoLo display number 5) */
@ -331,8 +367,8 @@ static struct pxafb_mode_info sharp_lq64d343_mode = {
static struct pxafb_mach_info sharp_lq64d343 = {
.modes = &sharp_lq64d343_mode,
.num_modes = 1,
.lccr0 = 0x07800080,
.lccr3 = 0x00400000,
.lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
LCD_ALTERNATE_MAPPING,
};
/* 10.4" TFT VGA (LoLo display number 7) */
@ -353,8 +389,8 @@ static struct pxafb_mode_info sharp_lq10d368_mode = {
static struct pxafb_mach_info sharp_lq10d368 = {
.modes = &sharp_lq10d368_mode,
.num_modes = 1,
.lccr0 = 0x07800080,
.lccr3 = 0x00400000,
.lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
LCD_ALTERNATE_MAPPING,
};
/* 3.5" TFT QVGA (LoLo display number 8) */
@ -375,8 +411,8 @@ static struct pxafb_mode_info sharp_lq035q7db02_20_mode = {
static struct pxafb_mach_info sharp_lq035q7db02_20 = {
.modes = &sharp_lq035q7db02_20_mode,
.num_modes = 1,
.lccr0 = 0x07800080,
.lccr3 = 0x00400000,
.lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
LCD_ALTERNATE_MAPPING,
};
static struct pxafb_mach_info *lpd270_lcd_to_use;
@ -411,27 +447,15 @@ static struct platform_device *platform_devices[] __initdata = {
&lpd270_flash_device[1],
};
static int lpd270_ohci_init(struct device *dev)
{
/* setup Port1 GPIO pin. */
pxa_gpio_mode(88 | GPIO_ALT_FN_1_IN); /* USBHPWR1 */
pxa_gpio_mode(89 | GPIO_ALT_FN_2_OUT); /* USBHPEN1 */
/* Set the Power Control Polarity Low and Power Sense
Polarity Low to active low. */
UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
~(UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSEP3 | UHCHR_SSE);
return 0;
}
static struct pxaohci_platform_data lpd270_ohci_platform_data = {
.port_mode = PMM_PERPORT_MODE,
.init = lpd270_ohci_init,
.flags = ENABLE_PORT_ALL | POWER_CONTROL_LOW | POWER_SENSE_LOW,
};
static void __init lpd270_init(void)
{
pxa2xx_mfp_config(ARRAY_AND_SIZE(lpd270_pin_config));
lpd270_flash_data[0].width = (BOOT_DEF & 1) ? 2 : 4;
lpd270_flash_data[1].width = 4;
@ -442,12 +466,6 @@ static void __init lpd270_init(void)
*/
ARB_CNTRL = ARB_CORE_PARK | 0x234;
/*
* On LogicPD PXA270, we route AC97_SYSCLK via GPIO45.
*/
pxa_gpio_mode(GPIO45_SYSCLK_AC97_MD);
pxa_gpio_mode(GPIO16_PWM0_MD);
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
pxa_set_ac97_info(NULL);
@ -473,15 +491,6 @@ static void __init lpd270_map_io(void)
pxa_map_io();
iotable_init(lpd270_io_desc, ARRAY_SIZE(lpd270_io_desc));
/* initialize sleep mode regs (wake-up sources, etc) */
PGSR0 = 0x00008800;
PGSR1 = 0x00000002;
PGSR2 = 0x0001FC00;
PGSR3 = 0x00001F81;
PWER = 0xC0000002;
PRER = 0x00000002;
PFER = 0x00000002;
/* for use I SRAM as framebuffer. */
PSLR |= 0x00000F04;
PCFR = 0x00000066;

26
arch/arm/mach-pxa/lubbock.c
View file

@ -57,13 +57,36 @@
static unsigned long lubbock_pin_config[] __initdata = {
GPIO15_nCS_1, /* CS1 - Flash */
GPIO78_nCS_2, /* CS2 - Baseboard FGPA */
GPIO79_nCS_3, /* CS3 - SMC ethernet */
GPIO80_nCS_4, /* CS4 - SA1111 */
/* SSP data pins */
GPIO23_SSP1_SCLK,
GPIO25_SSP1_TXD,
GPIO26_SSP1_RXD,
/* LCD - 16bpp DSTN */
GPIO58_LCD_LDD_0,
GPIO59_LCD_LDD_1,
GPIO60_LCD_LDD_2,
GPIO61_LCD_LDD_3,
GPIO62_LCD_LDD_4,
GPIO63_LCD_LDD_5,
GPIO64_LCD_LDD_6,
GPIO65_LCD_LDD_7,
GPIO66_LCD_LDD_8,
GPIO67_LCD_LDD_9,
GPIO68_LCD_LDD_10,
GPIO69_LCD_LDD_11,
GPIO70_LCD_LDD_12,
GPIO71_LCD_LDD_13,
GPIO72_LCD_LDD_14,
GPIO73_LCD_LDD_15,
GPIO74_LCD_FCLK,
GPIO75_LCD_LCLK,
GPIO76_LCD_PCLK,
/* BTUART */
GPIO42_BTUART_RXD,
GPIO43_BTUART_TXD,
@ -132,8 +155,7 @@ static void lubbock_irq_handler(unsigned int irq, struct irq_desc *desc)
GEDR(0) = GPIO_bit(0); /* clear our parent irq */
if (likely(pending)) {
irq = LUBBOCK_IRQ(0) + __ffs(pending);
desc = irq_desc + irq;
desc_handle_irq(irq, desc);
generic_handle_irq(irq);
}
pending = LUB_IRQ_SET_CLR & lubbock_irq_enabled;
} while (pending);

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