[ARM] pxa: use __raw_writel()/__raw_readl() for ssp_xxxx()
1. change SSP register definitions from absolute virtual addresses to offsets 2. use __raw_writel()/__raw_readl() for functions of ssp_xxxx() Signed-off-by: eric miao <eric.miao@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
eric miao
Russell King
parent
0aea1fd565
commit
3dcb00ea58
2 changed files with 63 additions and 103 deletions
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@ -48,9 +48,11 @@
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static irqreturn_t ssp_interrupt(int irq, void *dev_id)
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{
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struct ssp_dev *dev = (struct ssp_dev*) dev_id;
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unsigned int status = SSSR_P(dev->port);
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struct ssp_device *ssp = dev->ssp;
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unsigned int status;
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SSSR_P(dev->port) = status; /* clear status bits */
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status = __raw_readl(ssp->mmio_base + SSSR);
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__raw_writel(status, ssp->mmio_base + SSSR);
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if (status & SSSR_ROR)
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printk(KERN_WARNING "SSP(%d): receiver overrun\n", dev->port);
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@ -79,15 +81,16 @@ static irqreturn_t ssp_interrupt(int irq, void *dev_id)
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*/
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int ssp_write_word(struct ssp_dev *dev, u32 data)
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{
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struct ssp_device *ssp = dev->ssp;
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int timeout = TIMEOUT;
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while (!(SSSR_P(dev->port) & SSSR_TNF)) {
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while (!(__raw_readl(ssp->mmio_base + SSSR) & SSSR_TNF)) {
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if (!--timeout)
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return -ETIMEDOUT;
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cpu_relax();
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}
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SSDR_P(dev->port) = data;
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__raw_writel(data, ssp->mmio_base + SSDR);
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return 0;
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}
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@ -109,15 +112,16 @@ int ssp_write_word(struct ssp_dev *dev, u32 data)
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*/
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int ssp_read_word(struct ssp_dev *dev, u32 *data)
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{
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struct ssp_device *ssp = dev->ssp;
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int timeout = TIMEOUT;
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while (!(SSSR_P(dev->port) & SSSR_RNE)) {
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while (!(__raw_readl(ssp->mmio_base + SSSR) & SSSR_RNE)) {
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if (!--timeout)
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return -ETIMEDOUT;
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cpu_relax();
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}
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*data = SSDR_P(dev->port);
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*data = __raw_readl(ssp->mmio_base + SSDR);
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return 0;
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}
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@ -131,17 +135,18 @@ int ssp_read_word(struct ssp_dev *dev, u32 *data)
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*/
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int ssp_flush(struct ssp_dev *dev)
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{
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struct ssp_device *ssp = dev->ssp;
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int timeout = TIMEOUT * 2;
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do {
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while (SSSR_P(dev->port) & SSSR_RNE) {
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while (__raw_readl(ssp->mmio_base + SSSR) & SSSR_RNE) {
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if (!--timeout)
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return -ETIMEDOUT;
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(void) SSDR_P(dev->port);
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(void)__raw_readl(ssp->mmio_base + SSDR);
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}
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if (!--timeout)
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return -ETIMEDOUT;
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} while (SSSR_P(dev->port) & SSSR_BSY);
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} while (__raw_readl(ssp->mmio_base + SSSR) & SSSR_BSY);
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return 0;
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}
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@ -153,7 +158,12 @@ int ssp_flush(struct ssp_dev *dev)
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*/
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void ssp_enable(struct ssp_dev *dev)
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{
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SSCR0_P(dev->port) |= SSCR0_SSE;
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struct ssp_device *ssp = dev->ssp;
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uint32_t sscr0;
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sscr0 = __raw_readl(ssp->mmio_base + SSCR0);
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sscr0 |= SSCR0_SSE;
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__raw_writel(sscr0, ssp->mmio_base + SSCR0);
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}
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/**
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@ -163,7 +173,12 @@ void ssp_enable(struct ssp_dev *dev)
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*/
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void ssp_disable(struct ssp_dev *dev)
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{
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SSCR0_P(dev->port) &= ~SSCR0_SSE;
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struct ssp_device *ssp = dev->ssp;
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uint32_t sscr0;
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sscr0 = __raw_readl(ssp->mmio_base + SSCR0);
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sscr0 &= ~SSCR0_SSE;
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__raw_writel(sscr0, ssp->mmio_base + SSCR0);
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}
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/**
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@ -172,14 +187,16 @@ void ssp_disable(struct ssp_dev *dev)
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*
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* Save the configured SSP state for suspend.
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*/
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void ssp_save_state(struct ssp_dev *dev, struct ssp_state *ssp)
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void ssp_save_state(struct ssp_dev *dev, struct ssp_state *state)
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{
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ssp->cr0 = SSCR0_P(dev->port);
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ssp->cr1 = SSCR1_P(dev->port);
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ssp->to = SSTO_P(dev->port);
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ssp->psp = SSPSP_P(dev->port);
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struct ssp_device *ssp = dev->ssp;
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SSCR0_P(dev->port) &= ~SSCR0_SSE;
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state->cr0 = __raw_readl(ssp->mmio_base + SSCR0);
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state->cr1 = __raw_readl(ssp->mmio_base + SSCR1);
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state->to = __raw_readl(ssp->mmio_base + SSTO);
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state->psp = __raw_readl(ssp->mmio_base + SSPSP);
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ssp_disable(dev);
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}
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/**
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@ -188,16 +205,18 @@ void ssp_save_state(struct ssp_dev *dev, struct ssp_state *ssp)
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*
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* Restore the SSP configuration saved previously by ssp_save_state.
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*/
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void ssp_restore_state(struct ssp_dev *dev, struct ssp_state *ssp)
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void ssp_restore_state(struct ssp_dev *dev, struct ssp_state *state)
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{
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SSSR_P(dev->port) = SSSR_ROR | SSSR_TUR | SSSR_BCE;
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struct ssp_device *ssp = dev->ssp;
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uint32_t sssr = SSSR_ROR | SSSR_TUR | SSSR_BCE;
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SSCR0_P(dev->port) = ssp->cr0 & ~SSCR0_SSE;
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SSCR1_P(dev->port) = ssp->cr1;
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SSTO_P(dev->port) = ssp->to;
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SSPSP_P(dev->port) = ssp->psp;
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__raw_writel(sssr, ssp->mmio_base + SSSR);
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SSCR0_P(dev->port) = ssp->cr0;
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__raw_writel(state->cr0 & ~SSCR0_SSE, ssp->mmio_base + SSCR0);
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__raw_writel(state->cr1, ssp->mmio_base + SSCR1);
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__raw_writel(state->to, ssp->mmio_base + SSTO);
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__raw_writel(state->psp, ssp->mmio_base + SSPSP);
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__raw_writel(state->cr0, ssp->mmio_base + SSCR0);
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}
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/**
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@ -211,15 +230,17 @@ void ssp_restore_state(struct ssp_dev *dev, struct ssp_state *ssp)
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*/
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int ssp_config(struct ssp_dev *dev, u32 mode, u32 flags, u32 psp_flags, u32 speed)
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{
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struct ssp_device *ssp = dev->ssp;
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dev->mode = mode;
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dev->flags = flags;
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dev->psp_flags = psp_flags;
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dev->speed = speed;
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/* set up port type, speed, port settings */
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SSCR0_P(dev->port) = (dev->speed | dev->mode);
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SSCR1_P(dev->port) = dev->flags;
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SSPSP_P(dev->port) = dev->psp_flags;
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__raw_writel((dev->speed | dev->mode), ssp->mmio_base + SSCR0);
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__raw_writel(dev->flags, ssp->mmio_base + SSCR1);
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__raw_writel(dev->psp_flags, ssp->mmio_base + SSPSP);
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return 0;
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}
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@ -274,7 +295,7 @@ void ssp_exit(struct ssp_dev *dev)
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{
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struct ssp_device *ssp = dev->ssp;
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SSCR0_P(dev->port) &= ~SSCR0_SSE;
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ssp_disable(dev);
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free_irq(dev->irq, dev);
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clk_disable(ssp->clk);
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ssp_free(ssp);
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@ -7,7 +7,20 @@
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* PXA255, PXA26x and PXA27x have extra ports, registers and bits.
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*/
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/* Common PXA2xx bits first */
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#define SSCR0 (0x00) /* SSP Control Register 0 */
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#define SSCR1 (0x04) /* SSP Control Register 1 */
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#define SSSR (0x08) /* SSP Status Register */
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#define SSITR (0x0C) /* SSP Interrupt Test Register */
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#define SSDR (0x10) /* SSP Data Write/Data Read Register */
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#define SSTO (0x28) /* SSP Time Out Register */
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#define SSPSP (0x2C) /* SSP Programmable Serial Protocol */
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#define SSTSA (0x30) /* SSP Tx Timeslot Active */
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#define SSRSA (0x34) /* SSP Rx Timeslot Active */
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#define SSTSS (0x38) /* SSP Timeslot Status */
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#define SSACD (0x3C) /* SSP Audio Clock Divider */
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/* Common PXA2xx bits first */
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#define SSCR0_DSS (0x0000000f) /* Data Size Select (mask) */
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#define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */
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#define SSCR0_FRF (0x00000030) /* FRame Format (mask) */
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@ -96,78 +109,4 @@
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#define SSACD_ACPS(x) ((x) << 4) /* Audio clock PLL select */
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#define SSACD_ACDS(x) ((x) << 0) /* Audio clock divider select */
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#define SSCR0_P1 __REG(0x41000000) /* SSP Port 1 Control Register 0 */
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#define SSCR1_P1 __REG(0x41000004) /* SSP Port 1 Control Register 1 */
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#define SSSR_P1 __REG(0x41000008) /* SSP Port 1 Status Register */
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#define SSITR_P1 __REG(0x4100000C) /* SSP Port 1 Interrupt Test Register */
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#define SSDR_P1 __REG(0x41000010) /* (Write / Read) SSP Port 1 Data Write Register/SSP Data Read Register */
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/* Support existing PXA25x drivers */
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#define SSCR0 SSCR0_P1 /* SSP Control Register 0 */
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#define SSCR1 SSCR1_P1 /* SSP Control Register 1 */
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#define SSSR SSSR_P1 /* SSP Status Register */
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#define SSITR SSITR_P1 /* SSP Interrupt Test Register */
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#define SSDR SSDR_P1 /* (Write / Read) SSP Data Write Register/SSP Data Read Register */
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/* PXA27x ports */
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#if defined (CONFIG_PXA27x)
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#define SSTO_P1 __REG(0x41000028) /* SSP Port 1 Time Out Register */
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#define SSPSP_P1 __REG(0x4100002C) /* SSP Port 1 Programmable Serial Protocol */
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#define SSTSA_P1 __REG(0x41000030) /* SSP Port 1 Tx Timeslot Active */
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#define SSRSA_P1 __REG(0x41000034) /* SSP Port 1 Rx Timeslot Active */
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#define SSTSS_P1 __REG(0x41000038) /* SSP Port 1 Timeslot Status */
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#define SSACD_P1 __REG(0x4100003C) /* SSP Port 1 Audio Clock Divider */
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#define SSCR0_P2 __REG(0x41700000) /* SSP Port 2 Control Register 0 */
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#define SSCR1_P2 __REG(0x41700004) /* SSP Port 2 Control Register 1 */
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#define SSSR_P2 __REG(0x41700008) /* SSP Port 2 Status Register */
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#define SSITR_P2 __REG(0x4170000C) /* SSP Port 2 Interrupt Test Register */
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#define SSDR_P2 __REG(0x41700010) /* (Write / Read) SSP Port 2 Data Write Register/SSP Data Read Register */
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#define SSTO_P2 __REG(0x41700028) /* SSP Port 2 Time Out Register */
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#define SSPSP_P2 __REG(0x4170002C) /* SSP Port 2 Programmable Serial Protocol */
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#define SSTSA_P2 __REG(0x41700030) /* SSP Port 2 Tx Timeslot Active */
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#define SSRSA_P2 __REG(0x41700034) /* SSP Port 2 Rx Timeslot Active */
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#define SSTSS_P2 __REG(0x41700038) /* SSP Port 2 Timeslot Status */
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#define SSACD_P2 __REG(0x4170003C) /* SSP Port 2 Audio Clock Divider */
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#define SSCR0_P3 __REG(0x41900000) /* SSP Port 3 Control Register 0 */
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#define SSCR1_P3 __REG(0x41900004) /* SSP Port 3 Control Register 1 */
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#define SSSR_P3 __REG(0x41900008) /* SSP Port 3 Status Register */
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#define SSITR_P3 __REG(0x4190000C) /* SSP Port 3 Interrupt Test Register */
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#define SSDR_P3 __REG(0x41900010) /* (Write / Read) SSP Port 3 Data Write Register/SSP Data Read Register */
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#define SSTO_P3 __REG(0x41900028) /* SSP Port 3 Time Out Register */
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#define SSPSP_P3 __REG(0x4190002C) /* SSP Port 3 Programmable Serial Protocol */
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#define SSTSA_P3 __REG(0x41900030) /* SSP Port 3 Tx Timeslot Active */
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#define SSRSA_P3 __REG(0x41900034) /* SSP Port 3 Rx Timeslot Active */
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#define SSTSS_P3 __REG(0x41900038) /* SSP Port 3 Timeslot Status */
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#define SSACD_P3 __REG(0x4190003C) /* SSP Port 3 Audio Clock Divider */
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#else /* PXA255 (only port 2) and PXA26x ports*/
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#define SSTO_P1 __REG(0x41000028) /* SSP Port 1 Time Out Register */
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#define SSPSP_P1 __REG(0x4100002C) /* SSP Port 1 Programmable Serial Protocol */
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#define SSCR0_P2 __REG(0x41400000) /* SSP Port 2 Control Register 0 */
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#define SSCR1_P2 __REG(0x41400004) /* SSP Port 2 Control Register 1 */
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#define SSSR_P2 __REG(0x41400008) /* SSP Port 2 Status Register */
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#define SSITR_P2 __REG(0x4140000C) /* SSP Port 2 Interrupt Test Register */
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#define SSDR_P2 __REG(0x41400010) /* (Write / Read) SSP Port 2 Data Write Register/SSP Data Read Register */
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#define SSTO_P2 __REG(0x41400028) /* SSP Port 2 Time Out Register */
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#define SSPSP_P2 __REG(0x4140002C) /* SSP Port 2 Programmable Serial Protocol */
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#define SSCR0_P3 __REG(0x41500000) /* SSP Port 3 Control Register 0 */
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#define SSCR1_P3 __REG(0x41500004) /* SSP Port 3 Control Register 1 */
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#define SSSR_P3 __REG(0x41500008) /* SSP Port 3 Status Register */
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#define SSITR_P3 __REG(0x4150000C) /* SSP Port 3 Interrupt Test Register */
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#define SSDR_P3 __REG(0x41500010) /* (Write / Read) SSP Port 3 Data Write Register/SSP Data Read Register */
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#define SSTO_P3 __REG(0x41500028) /* SSP Port 3 Time Out Register */
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#define SSPSP_P3 __REG(0x4150002C) /* SSP Port 3 Programmable Serial Protocol */
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#endif
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#define SSCR0_P(x) (*(((x) == 1) ? &SSCR0_P1 : ((x) == 2) ? &SSCR0_P2 : ((x) == 3) ? &SSCR0_P3 : NULL))
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#define SSCR1_P(x) (*(((x) == 1) ? &SSCR1_P1 : ((x) == 2) ? &SSCR1_P2 : ((x) == 3) ? &SSCR1_P3 : NULL))
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#define SSSR_P(x) (*(((x) == 1) ? &SSSR_P1 : ((x) == 2) ? &SSSR_P2 : ((x) == 3) ? &SSSR_P3 : NULL))
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#define SSITR_P(x) (*(((x) == 1) ? &SSITR_P1 : ((x) == 2) ? &SSITR_P2 : ((x) == 3) ? &SSITR_P3 : NULL))
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#define SSDR_P(x) (*(((x) == 1) ? &SSDR_P1 : ((x) == 2) ? &SSDR_P2 : ((x) == 3) ? &SSDR_P3 : NULL))
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#define SSTO_P(x) (*(((x) == 1) ? &SSTO_P1 : ((x) == 2) ? &SSTO_P2 : ((x) == 3) ? &SSTO_P3 : NULL))
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#define SSPSP_P(x) (*(((x) == 1) ? &SSPSP_P1 : ((x) == 2) ? &SSPSP_P2 : ((x) == 3) ? &SSPSP_P3 : NULL))
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#define SSTSA_P(x) (*(((x) == 1) ? &SSTSA_P1 : ((x) == 2) ? &SSTSA_P2 : ((x) == 3) ? &SSTSA_P3 : NULL))
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#define SSRSA_P(x) (*(((x) == 1) ? &SSRSA_P1 : ((x) == 2) ? &SSRSA_P2 : ((x) == 3) ? &SSRSA_P3 : NULL))
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#define SSTSS_P(x) (*(((x) == 1) ? &SSTSS_P1 : ((x) == 2) ? &SSTSS_P2 : ((x) == 3) ? &SSTSS_P3 : NULL))
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#define SSACD_P(x) (*(((x) == 1) ? &SSACD_P1 : ((x) == 2) ? &SSACD_P2 : ((x) == 3) ? &SSACD_P3 : NULL))
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#endif /* __ASM_ARCH_REGS_SSP_H */
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