[PATCH] sata_sil: separate out sil_init_controller()
Separate out controller initialization from sil_init_one() into sil_init_controller(). This will be used by resume. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
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500530f652
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3d8ec91352
1 changed files with 48 additions and 38 deletions
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@ -561,6 +561,52 @@ static void sil_dev_config(struct ata_port *ap, struct ata_device *dev)
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}
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}
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}
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}
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static void sil_init_controller(struct pci_dev *pdev,
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int n_ports, unsigned long host_flags,
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void __iomem *mmio_base)
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{
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u8 cls;
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u32 tmp;
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int i;
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/* Initialize FIFO PCI bus arbitration */
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cls = sil_get_device_cache_line(pdev);
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if (cls) {
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cls >>= 3;
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cls++; /* cls = (line_size/8)+1 */
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for (i = 0; i < n_ports; i++)
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writew(cls << 8 | cls,
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mmio_base + sil_port[i].fifo_cfg);
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} else
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dev_printk(KERN_WARNING, &pdev->dev,
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"cache line size not set. Driver may not function\n");
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/* Apply R_ERR on DMA activate FIS errata workaround */
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if (host_flags & SIL_FLAG_RERR_ON_DMA_ACT) {
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int cnt;
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for (i = 0, cnt = 0; i < n_ports; i++) {
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tmp = readl(mmio_base + sil_port[i].sfis_cfg);
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if ((tmp & 0x3) != 0x01)
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continue;
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if (!cnt)
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dev_printk(KERN_INFO, &pdev->dev,
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"Applying R_ERR on DMA activate "
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"FIS errata fix\n");
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writel(tmp & ~0x3, mmio_base + sil_port[i].sfis_cfg);
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cnt++;
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}
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}
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if (n_ports == 4) {
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/* flip the magic "make 4 ports work" bit */
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tmp = readl(mmio_base + sil_port[2].bmdma);
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if ((tmp & SIL_INTR_STEERING) == 0)
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writel(tmp | SIL_INTR_STEERING,
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mmio_base + sil_port[2].bmdma);
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}
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}
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static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
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static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
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{
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{
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static int printed_version;
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static int printed_version;
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@ -570,8 +616,6 @@ static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
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int rc;
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int rc;
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unsigned int i;
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unsigned int i;
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int pci_dev_busy = 0;
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int pci_dev_busy = 0;
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u32 tmp;
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u8 cls;
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if (!printed_version++)
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if (!printed_version++)
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dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
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dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
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@ -630,42 +674,8 @@ static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
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ata_std_ports(&probe_ent->port[i]);
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ata_std_ports(&probe_ent->port[i]);
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}
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}
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/* Initialize FIFO PCI bus arbitration */
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sil_init_controller(pdev, probe_ent->n_ports, probe_ent->host_flags,
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cls = sil_get_device_cache_line(pdev);
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mmio_base);
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if (cls) {
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cls >>= 3;
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cls++; /* cls = (line_size/8)+1 */
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for (i = 0; i < probe_ent->n_ports; i++)
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writew(cls << 8 | cls,
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mmio_base + sil_port[i].fifo_cfg);
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} else
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dev_printk(KERN_WARNING, &pdev->dev,
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"cache line size not set. Driver may not function\n");
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/* Apply R_ERR on DMA activate FIS errata workaround */
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if (probe_ent->host_flags & SIL_FLAG_RERR_ON_DMA_ACT) {
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int cnt;
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for (i = 0, cnt = 0; i < probe_ent->n_ports; i++) {
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tmp = readl(mmio_base + sil_port[i].sfis_cfg);
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if ((tmp & 0x3) != 0x01)
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continue;
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if (!cnt)
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dev_printk(KERN_INFO, &pdev->dev,
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"Applying R_ERR on DMA activate "
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"FIS errata fix\n");
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writel(tmp & ~0x3, mmio_base + sil_port[i].sfis_cfg);
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cnt++;
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}
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}
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if (ent->driver_data == sil_3114) {
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/* flip the magic "make 4 ports work" bit */
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tmp = readl(mmio_base + sil_port[2].bmdma);
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if ((tmp & SIL_INTR_STEERING) == 0)
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writel(tmp | SIL_INTR_STEERING,
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mmio_base + sil_port[2].bmdma);
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}
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pci_set_master(pdev);
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pci_set_master(pdev);
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