Merge commit 'jwb/next' into next
This commit is contained in:
Benjamin Herrenschmidt
commit
3d00d4ff11
9 changed files with 2217 additions and 7 deletions
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@ -519,7 +519,7 @@ void ibm440ep_fixup_clocks(unsigned int sys_clk,
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{
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unsigned int plb_clk = __ibm440eplike_fixup_clocks(sys_clk, tmr_clk, 0);
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/* serial clocks beed fixup based on int/ext */
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/* serial clocks need fixup based on int/ext */
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eplike_fixup_uart_clk(0, "/plb/opb/serial@ef600300", ser_clk, plb_clk);
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eplike_fixup_uart_clk(1, "/plb/opb/serial@ef600400", ser_clk, plb_clk);
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eplike_fixup_uart_clk(2, "/plb/opb/serial@ef600500", ser_clk, plb_clk);
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@ -532,7 +532,7 @@ void ibm440gx_fixup_clocks(unsigned int sys_clk,
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{
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unsigned int plb_clk = __ibm440eplike_fixup_clocks(sys_clk, tmr_clk, 1);
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/* serial clocks beed fixup based on int/ext */
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/* serial clocks need fixup based on int/ext */
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eplike_fixup_uart_clk(0, "/plb/opb/serial@40000200", ser_clk, plb_clk);
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eplike_fixup_uart_clk(1, "/plb/opb/serial@40000300", ser_clk, plb_clk);
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}
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@ -543,10 +543,10 @@ void ibm440spe_fixup_clocks(unsigned int sys_clk,
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{
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unsigned int plb_clk = __ibm440eplike_fixup_clocks(sys_clk, tmr_clk, 1);
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/* serial clocks beed fixup based on int/ext */
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eplike_fixup_uart_clk(0, "/plb/opb/serial@10000200", ser_clk, plb_clk);
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eplike_fixup_uart_clk(1, "/plb/opb/serial@10000300", ser_clk, plb_clk);
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eplike_fixup_uart_clk(2, "/plb/opb/serial@10000600", ser_clk, plb_clk);
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/* serial clocks need fixup based on int/ext */
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eplike_fixup_uart_clk(0, "/plb/opb/serial@f0000200", ser_clk, plb_clk);
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eplike_fixup_uart_clk(1, "/plb/opb/serial@f0000300", ser_clk, plb_clk);
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eplike_fixup_uart_clk(2, "/plb/opb/serial@f0000600", ser_clk, plb_clk);
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}
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void ibm405gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk)
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447
arch/powerpc/boot/dts/icon.dts
Normal file
447
arch/powerpc/boot/dts/icon.dts
Normal file
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@ -0,0 +1,447 @@
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/*
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* Device Tree Source for Mosaix Technologies, Inc. ICON board
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*
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* Copyright 2010 DENX Software Engineering, Stefan Roese <sr@denx.de>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without
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* any warranty of any kind, whether express or implied.
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*/
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/dts-v1/;
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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model = "mosaixtech,icon";
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compatible = "mosaixtech,icon";
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dcr-parent = <&{/cpus/cpu@0}>;
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aliases {
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ethernet0 = &EMAC0;
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serial0 = &UART0;
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serial1 = &UART1;
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serial2 = &UART2;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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model = "PowerPC,440SPe";
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reg = <0x00000000>;
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clock-frequency = <0>; /* Filled in by U-Boot */
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timebase-frequency = <0>; /* Filled in by U-Boot */
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i-cache-line-size = <32>;
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d-cache-line-size = <32>;
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i-cache-size = <32768>;
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d-cache-size = <32768>;
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dcr-controller;
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dcr-access-method = "native";
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reset-type = <2>; /* Use chip-reset */
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};
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};
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memory {
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device_type = "memory";
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reg = <0x0 0x00000000 0x0 0x00000000>; /* Filled in by U-Boot */
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};
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UIC0: interrupt-controller0 {
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compatible = "ibm,uic-440spe","ibm,uic";
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interrupt-controller;
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cell-index = <0>;
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dcr-reg = <0x0c0 0x009>;
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#address-cells = <0>;
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#size-cells = <0>;
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#interrupt-cells = <2>;
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};
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UIC1: interrupt-controller1 {
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compatible = "ibm,uic-440spe","ibm,uic";
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interrupt-controller;
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cell-index = <1>;
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dcr-reg = <0x0d0 0x009>;
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#address-cells = <0>;
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#size-cells = <0>;
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#interrupt-cells = <2>;
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interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
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interrupt-parent = <&UIC0>;
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};
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UIC2: interrupt-controller2 {
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compatible = "ibm,uic-440spe","ibm,uic";
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interrupt-controller;
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cell-index = <2>;
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dcr-reg = <0x0e0 0x009>;
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#address-cells = <0>;
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#size-cells = <0>;
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#interrupt-cells = <2>;
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interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
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interrupt-parent = <&UIC0>;
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};
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UIC3: interrupt-controller3 {
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compatible = "ibm,uic-440spe","ibm,uic";
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interrupt-controller;
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cell-index = <3>;
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dcr-reg = <0x0f0 0x009>;
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#address-cells = <0>;
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#size-cells = <0>;
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#interrupt-cells = <2>;
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interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
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interrupt-parent = <&UIC0>;
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};
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SDR0: sdr {
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compatible = "ibm,sdr-440spe";
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dcr-reg = <0x00e 0x002>;
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};
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CPR0: cpr {
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compatible = "ibm,cpr-440spe";
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dcr-reg = <0x00c 0x002>;
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};
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MQ0: mq {
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compatible = "ibm,mq-440spe";
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dcr-reg = <0x040 0x020>;
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};
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plb {
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compatible = "ibm,plb-440spe", "ibm,plb-440gp", "ibm,plb4";
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#address-cells = <2>;
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#size-cells = <1>;
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/* addr-child addr-parent size */
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ranges = <0x4 0x00100000 0x4 0x00100000 0x00001000
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0x4 0x00200000 0x4 0x00200000 0x00000400
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0x4 0xe0000000 0x4 0xe0000000 0x20000000
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0xc 0x00000000 0xc 0x00000000 0x20000000
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0xd 0x00000000 0xd 0x00000000 0x80000000
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0xd 0x80000000 0xd 0x80000000 0x80000000
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0xe 0x00000000 0xe 0x00000000 0x80000000
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0xe 0x80000000 0xe 0x80000000 0x80000000
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0xf 0x00000000 0xf 0x00000000 0x80000000
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0xf 0x80000000 0xf 0x80000000 0x80000000>;
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clock-frequency = <0>; /* Filled in by U-Boot */
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SDRAM0: sdram {
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compatible = "ibm,sdram-440spe", "ibm,sdram-405gp";
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dcr-reg = <0x010 0x002>;
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};
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MAL0: mcmal {
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compatible = "ibm,mcmal-440spe", "ibm,mcmal2";
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dcr-reg = <0x180 0x062>;
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num-tx-chans = <2>;
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num-rx-chans = <1>;
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interrupt-parent = <&MAL0>;
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interrupts = <0x0 0x1 0x2 0x3 0x4>;
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#interrupt-cells = <1>;
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#address-cells = <0>;
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#size-cells = <0>;
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interrupt-map = </*TXEOB*/ 0x0 &UIC1 0x6 0x4
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/*RXEOB*/ 0x1 &UIC1 0x7 0x4
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/*SERR*/ 0x2 &UIC1 0x1 0x4
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/*TXDE*/ 0x3 &UIC1 0x2 0x4
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/*RXDE*/ 0x4 &UIC1 0x3 0x4>;
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};
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POB0: opb {
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compatible = "ibm,opb-440spe", "ibm,opb-440gp", "ibm,opb";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0xe0000000 0x00000004 0xe0000000 0x20000000>;
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clock-frequency = <0>; /* Filled in by U-Boot */
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EBC0: ebc {
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compatible = "ibm,ebc-440spe", "ibm,ebc-440gp", "ibm,ebc";
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dcr-reg = <0x012 0x002>;
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#address-cells = <2>;
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#size-cells = <1>;
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clock-frequency = <0>; /* Filled in by U-Boot */
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/* ranges property is supplied by U-Boot */
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interrupts = <0x5 0x1>;
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interrupt-parent = <&UIC1>;
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nor_flash@0,0 {
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compatible = "cfi-flash";
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bank-width = <2>;
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reg = <0x00000000 0x00000000 0x01000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "kernel";
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reg = <0x00000000 0x001e0000>;
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};
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partition@1e0000 {
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label = "dtb";
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reg = <0x001e0000 0x00020000>;
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};
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partition@200000 {
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label = "root";
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reg = <0x00200000 0x00200000>;
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};
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partition@400000 {
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label = "user";
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reg = <0x00400000 0x00b60000>;
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};
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partition@f60000 {
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label = "env";
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reg = <0x00f60000 0x00040000>;
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};
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partition@fa0000 {
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label = "u-boot";
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reg = <0x00fa0000 0x00060000>;
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};
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};
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SysACE_CompactFlash: sysace@1,0 {
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compatible = "xlnx,sysace";
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interrupt-parent = <&UIC2>;
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interrupts = <24 0x4>;
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reg = <0x00000001 0x00000000 0x10000>;
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};
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};
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UART0: serial@f0000200 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <0xf0000200 0x00000008>;
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virtual-reg = <0xa0000200>;
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clock-frequency = <0>; /* Filled in by U-Boot */
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current-speed = <115200>;
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interrupt-parent = <&UIC0>;
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interrupts = <0x0 0x4>;
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};
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UART1: serial@f0000300 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <0xf0000300 0x00000008>;
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virtual-reg = <0xa0000300>;
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clock-frequency = <0>;
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current-speed = <0>;
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interrupt-parent = <&UIC0>;
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interrupts = <0x1 0x4>;
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};
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UART2: serial@f0000600 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <0xf0000600 0x00000008>;
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virtual-reg = <0xa0000600>;
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clock-frequency = <0>;
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current-speed = <0>;
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interrupt-parent = <&UIC1>;
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interrupts = <0x5 0x4>;
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};
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IIC0: i2c@f0000400 {
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compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic";
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reg = <0xf0000400 0x00000014>;
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interrupt-parent = <&UIC0>;
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interrupts = <0x2 0x4>;
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};
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IIC1: i2c@f0000500 {
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compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic";
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reg = <0xf0000500 0x00000014>;
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interrupt-parent = <&UIC0>;
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interrupts = <0x3 0x4>;
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#address-cells = <1>;
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#size-cells = <0>;
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rtc@68 {
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compatible = "stm,m41t00";
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reg = <0x68>;
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};
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};
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EMAC0: ethernet@f0000800 {
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linux,network-index = <0x0>;
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device_type = "network";
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compatible = "ibm,emac-440spe", "ibm,emac4";
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interrupt-parent = <&UIC1>;
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interrupts = <0x1c 0x4 0x1d 0x4>;
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reg = <0xf0000800 0x00000074>;
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local-mac-address = [000000000000];
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mal-device = <&MAL0>;
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mal-tx-channel = <0>;
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mal-rx-channel = <0>;
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cell-index = <0>;
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max-frame-size = <9000>;
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rx-fifo-size = <4096>;
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tx-fifo-size = <2048>;
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phy-mode = "gmii";
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phy-map = <0x00000000>;
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has-inverted-stacr-oc;
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has-new-stacr-staopc;
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};
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};
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PCIX0: pci@c0ec00000 {
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device_type = "pci";
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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compatible = "ibm,plb-pcix-440spe", "ibm,plb-pcix";
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primary;
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large-inbound-windows;
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enable-msi-hole;
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reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */
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0x00000000 0x00000000 0x00000000 /* no IACK cycles */
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0x0000000c 0x0ed00000 0x00000004 /* Special cycles */
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0x0000000c 0x0ec80000 0x00000100 /* Internal registers */
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0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */
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/* Outbound ranges, one memory and one IO,
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* later cannot be changed
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*/
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ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000
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0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>;
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/* Inbound 4GB range starting at 0 */
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dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x1 0x00000000>;
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/* This drives busses 0 to 0xf */
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bus-range = <0x0 0xf>;
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/* PCI-X interrupt (SM502) is routed to extIRQ10 (UIC1, 19) */
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interrupt-map-mask = <0x0 0x0 0x0 0x0>;
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interrupt-map = <0x0 0x0 0x0 0x0 &UIC1 19 0x8>;
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};
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PCIE0: pciex@d00000000 {
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device_type = "pci";
|
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#interrupt-cells = <1>;
|
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#size-cells = <2>;
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#address-cells = <3>;
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compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex";
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primary;
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port = <0x0>; /* port number */
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reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */
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0x0000000c 0x10000000 0x00001000>; /* Registers */
|
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dcr-reg = <0x100 0x020>;
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sdr-base = <0x300>;
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|
||||
/* Outbound ranges, one memory and one IO,
|
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* later cannot be changed
|
||||
*/
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ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
|
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0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
|
||||
|
||||
/* Inbound 4GB range starting at 0 */
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x1 0x00000000>;
|
||||
|
||||
/* This drives busses 0x10 to 0x1f */
|
||||
bus-range = <0x10 0x1f>;
|
||||
|
||||
/* Legacy interrupts (note the weird polarity, the bridge seems
|
||||
* to invert PCIe legacy interrupts).
|
||||
* We are de-swizzling here because the numbers are actually for
|
||||
* port of the root complex virtual P2P bridge. But I want
|
||||
* to avoid putting a node for it in the tree, so the numbers
|
||||
* below are basically de-swizzled numbers.
|
||||
* The real slot is on idsel 0, so the swizzling is 1:1
|
||||
*/
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
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interrupt-map = <
|
||||
0x0 0x0 0x0 0x1 &UIC3 0x0 0x4 /* swizzled int A */
|
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0x0 0x0 0x0 0x2 &UIC3 0x1 0x4 /* swizzled int B */
|
||||
0x0 0x0 0x0 0x3 &UIC3 0x2 0x4 /* swizzled int C */
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0x0 0x0 0x0 0x4 &UIC3 0x3 0x4 /* swizzled int D */>;
|
||||
};
|
||||
|
||||
PCIE1: pciex@d20000000 {
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex";
|
||||
primary;
|
||||
port = <0x1>; /* port number */
|
||||
reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */
|
||||
0x0000000c 0x10001000 0x00001000>; /* Registers */
|
||||
dcr-reg = <0x120 0x020>;
|
||||
sdr-base = <0x340>;
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed
|
||||
*/
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
|
||||
0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;
|
||||
|
||||
/* Inbound 4GB range starting at 0 */
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x1 0x00000000>;
|
||||
|
||||
/* This drives busses 0x20 to 0x2f */
|
||||
bus-range = <0x20 0x2f>;
|
||||
|
||||
/* Legacy interrupts (note the weird polarity, the bridge seems
|
||||
* to invert PCIe legacy interrupts).
|
||||
* We are de-swizzling here because the numbers are actually for
|
||||
* port of the root complex virtual P2P bridge. But I want
|
||||
* to avoid putting a node for it in the tree, so the numbers
|
||||
* below are basically de-swizzled numbers.
|
||||
* The real slot is on idsel 0, so the swizzling is 1:1
|
||||
*/
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
0x0 0x0 0x0 0x1 &UIC3 0x4 0x4 /* swizzled int A */
|
||||
0x0 0x0 0x0 0x2 &UIC3 0x5 0x4 /* swizzled int B */
|
||||
0x0 0x0 0x0 0x3 &UIC3 0x6 0x4 /* swizzled int C */
|
||||
0x0 0x0 0x0 0x4 &UIC3 0x7 0x4 /* swizzled int D */>;
|
||||
};
|
||||
|
||||
I2O: i2o@400100000 {
|
||||
compatible = "ibm,i2o-440spe";
|
||||
reg = <0x00000004 0x00100000 0x100>;
|
||||
dcr-reg = <0x060 0x020>;
|
||||
};
|
||||
|
||||
DMA0: dma0@400100100 {
|
||||
compatible = "ibm,dma-440spe";
|
||||
cell-index = <0>;
|
||||
reg = <0x00000004 0x00100100 0x100>;
|
||||
dcr-reg = <0x060 0x020>;
|
||||
interrupt-parent = <&DMA0>;
|
||||
interrupts = <0 1>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = <
|
||||
0 &UIC0 0x14 4
|
||||
1 &UIC1 0x16 4>;
|
||||
};
|
||||
|
||||
DMA1: dma1@400100200 {
|
||||
compatible = "ibm,dma-440spe";
|
||||
cell-index = <1>;
|
||||
reg = <0x00000004 0x00100200 0x100>;
|
||||
dcr-reg = <0x060 0x020>;
|
||||
interrupt-parent = <&DMA1>;
|
||||
interrupts = <0 1>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = <
|
||||
0 &UIC0 0x16 4
|
||||
1 &UIC1 0x16 4>;
|
||||
};
|
||||
|
||||
xor-accel@400200000 {
|
||||
compatible = "amcc,xor-accelerator";
|
||||
reg = <0x00000004 0x00200000 0x400>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <0x1f 4>;
|
||||
};
|
||||
};
|
||||
|
||||
chosen {
|
||||
linux,stdout-path = "/plb/opb/serial@f0000200";
|
||||
};
|
||||
};
|
||||
|
|
@ -44,6 +44,7 @@
|
|||
d-cache-size = <32768>;
|
||||
dcr-controller;
|
||||
dcr-access-method = "native";
|
||||
reset-type = <2>; /* Use chip-reset */
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -234,10 +234,132 @@
|
|||
has-inverted-stacr-oc;
|
||||
has-new-stacr-staopc;
|
||||
};
|
||||
};
|
||||
PCIE0: pciex@d00000000 {
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pciex-460sx", "ibm,plb-pciex";
|
||||
primary;
|
||||
port = <0x0>; /* port number */
|
||||
reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */
|
||||
0x0000000c 0x10000000 0x00001000>; /* Registers */
|
||||
dcr-reg = <0x100 0x020>;
|
||||
sdr-base = <0x300>;
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed
|
||||
*/
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
|
||||
0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
|
||||
|
||||
/* This drives busses 10 to 0x1f */
|
||||
bus-range = <0x10 0x1f>;
|
||||
|
||||
/* Legacy interrupts (note the weird polarity, the bridge seems
|
||||
* to invert PCIe legacy interrupts).
|
||||
* We are de-swizzling here because the numbers are actually for
|
||||
* port of the root complex virtual P2P bridge. But I want
|
||||
* to avoid putting a node for it in the tree, so the numbers
|
||||
* below are basically de-swizzled numbers.
|
||||
* The real slot is on idsel 0, so the swizzling is 1:1
|
||||
*/
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
0x0 0x0 0x0 0x1 &UIC3 0x0 0x4 /* swizzled int A */
|
||||
0x0 0x0 0x0 0x2 &UIC3 0x1 0x4 /* swizzled int B */
|
||||
0x0 0x0 0x0 0x3 &UIC3 0x2 0x4 /* swizzled int C */
|
||||
0x0 0x0 0x0 0x4 &UIC3 0x3 0x4 /* swizzled int D */>;
|
||||
};
|
||||
|
||||
PCIE1: pciex@d20000000 {
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pciex-460sx", "ibm,plb-pciex";
|
||||
primary;
|
||||
port = <0x1>; /* port number */
|
||||
reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */
|
||||
0x0000000c 0x10001000 0x00001000>; /* Registers */
|
||||
dcr-reg = <0x120 0x020>;
|
||||
sdr-base = <0x340>;
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed
|
||||
*/
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
|
||||
0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
|
||||
|
||||
/* This drives busses 10 to 0x1f */
|
||||
bus-range = <0x20 0x2f>;
|
||||
|
||||
/* Legacy interrupts (note the weird polarity, the bridge seems
|
||||
* to invert PCIe legacy interrupts).
|
||||
* We are de-swizzling here because the numbers are actually for
|
||||
* port of the root complex virtual P2P bridge. But I want
|
||||
* to avoid putting a node for it in the tree, so the numbers
|
||||
* below are basically de-swizzled numbers.
|
||||
* The real slot is on idsel 0, so the swizzling is 1:1
|
||||
*/
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
0x0 0x0 0x0 0x1 &UIC3 0x4 0x4 /* swizzled int A */
|
||||
0x0 0x0 0x0 0x2 &UIC3 0x5 0x4 /* swizzled int B */
|
||||
0x0 0x0 0x0 0x3 &UIC3 0x6 0x4 /* swizzled int C */
|
||||
0x0 0x0 0x0 0x4 &UIC3 0x7 0x4 /* swizzled int D */>;
|
||||
};
|
||||
|
||||
PCIE2: pciex@d40000000 {
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pciex-460sx", "ibm,plb-pciex";
|
||||
primary;
|
||||
port = <0x2>; /* port number */
|
||||
reg = <0x0000000d 0x40000000 0x20000000 /* Config space access */
|
||||
0x0000000c 0x10002000 0x00001000>; /* Registers */
|
||||
dcr-reg = <0x140 0x020>;
|
||||
sdr-base = <0x370>;
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed
|
||||
*/
|
||||
ranges = <0x02000000 0x00000000 0x80000000 0x0000000f 0x00000000 0x00000000 0x80000000
|
||||
0x01000000 0x00000000 0x00000000 0x0000000f 0x80020000 0x00000000 0x00010000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
|
||||
|
||||
/* This drives busses 10 to 0x1f */
|
||||
bus-range = <0x30 0x3f>;
|
||||
|
||||
/* Legacy interrupts (note the weird polarity, the bridge seems
|
||||
* to invert PCIe legacy interrupts).
|
||||
* We are de-swizzling here because the numbers are actually for
|
||||
* port of the root complex virtual P2P bridge. But I want
|
||||
* to avoid putting a node for it in the tree, so the numbers
|
||||
* below are basically de-swizzled numbers.
|
||||
* The real slot is on idsel 0, so the swizzling is 1:1
|
||||
*/
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
0x0 0x0 0x0 0x1 &UIC3 0x8 0x4 /* swizzled int A */
|
||||
0x0 0x0 0x0 0x2 &UIC3 0x9 0x4 /* swizzled int B */
|
||||
0x0 0x0 0x0 0x3 &UIC3 0xa 0x4 /* swizzled int C */
|
||||
0x0 0x0 0x0 0x4 &UIC3 0xb 0x4 /* swizzled int D */>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
chosen {
|
||||
linux,stdout-path = "/plb/opb/serial@ef600200";
|
||||
};
|
||||
|
|
|
|||
1451
arch/powerpc/configs/44x/icon_defconfig
Normal file
1451
arch/powerpc/configs/44x/icon_defconfig
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -171,6 +171,17 @@ config ISS4xx
|
|||
help
|
||||
This option enables support for the IBM ISS simulation environment
|
||||
|
||||
config ICON
|
||||
bool "Icon"
|
||||
depends on 44x
|
||||
default n
|
||||
select PPC44x_SIMPLE
|
||||
select 440SPe
|
||||
select PCI
|
||||
select PPC4xx_PCI_EXPRESS
|
||||
help
|
||||
This option enables support for the AMCC PPC440SPe evaluation board.
|
||||
|
||||
#config LUAN
|
||||
# bool "Luan"
|
||||
# depends on 44x
|
||||
|
|
|
|||
|
|
@ -61,7 +61,8 @@ static char *board[] __initdata = {
|
|||
"amcc,redwood",
|
||||
"amcc,sequoia",
|
||||
"amcc,taishan",
|
||||
"amcc,yosemite"
|
||||
"amcc,yosemite",
|
||||
"mosaixtech,icon"
|
||||
};
|
||||
|
||||
static int __init ppc44x_probe(void)
|
||||
|
|
|
|||
|
|
@ -974,6 +974,123 @@ static struct ppc4xx_pciex_hwops ppc460ex_pcie_hwops __initdata =
|
|||
.setup_utl = ppc460ex_pciex_init_utl,
|
||||
};
|
||||
|
||||
static int __init ppc460sx_pciex_core_init(struct device_node *np)
|
||||
{
|
||||
/* HSS drive amplitude */
|
||||
mtdcri(SDR0, PESDR0_460SX_HSSL0DAMP, 0xB9843211);
|
||||
mtdcri(SDR0, PESDR0_460SX_HSSL1DAMP, 0xB9843211);
|
||||
mtdcri(SDR0, PESDR0_460SX_HSSL2DAMP, 0xB9843211);
|
||||
mtdcri(SDR0, PESDR0_460SX_HSSL3DAMP, 0xB9843211);
|
||||
mtdcri(SDR0, PESDR0_460SX_HSSL4DAMP, 0xB9843211);
|
||||
mtdcri(SDR0, PESDR0_460SX_HSSL5DAMP, 0xB9843211);
|
||||
mtdcri(SDR0, PESDR0_460SX_HSSL6DAMP, 0xB9843211);
|
||||
mtdcri(SDR0, PESDR0_460SX_HSSL7DAMP, 0xB9843211);
|
||||
|
||||
mtdcri(SDR0, PESDR1_460SX_HSSL0DAMP, 0xB9843211);
|
||||
mtdcri(SDR0, PESDR1_460SX_HSSL1DAMP, 0xB9843211);
|
||||
mtdcri(SDR0, PESDR1_460SX_HSSL2DAMP, 0xB9843211);
|
||||
mtdcri(SDR0, PESDR1_460SX_HSSL3DAMP, 0xB9843211);
|
||||
|
||||
mtdcri(SDR0, PESDR2_460SX_HSSL0DAMP, 0xB9843211);
|
||||
mtdcri(SDR0, PESDR2_460SX_HSSL1DAMP, 0xB9843211);
|
||||
mtdcri(SDR0, PESDR2_460SX_HSSL2DAMP, 0xB9843211);
|
||||
mtdcri(SDR0, PESDR2_460SX_HSSL3DAMP, 0xB9843211);
|
||||
|
||||
/* HSS TX pre-emphasis */
|
||||
mtdcri(SDR0, PESDR0_460SX_HSSL0COEFA, 0xDCB98987);
|
||||
mtdcri(SDR0, PESDR0_460SX_HSSL1COEFA, 0xDCB98987);
|
||||
mtdcri(SDR0, PESDR0_460SX_HSSL2COEFA, 0xDCB98987);
|
||||
mtdcri(SDR0, PESDR0_460SX_HSSL3COEFA, 0xDCB98987);
|
||||
mtdcri(SDR0, PESDR0_460SX_HSSL4COEFA, 0xDCB98987);
|
||||
mtdcri(SDR0, PESDR0_460SX_HSSL5COEFA, 0xDCB98987);
|
||||
mtdcri(SDR0, PESDR0_460SX_HSSL6COEFA, 0xDCB98987);
|
||||
mtdcri(SDR0, PESDR0_460SX_HSSL7COEFA, 0xDCB98987);
|
||||
|
||||
mtdcri(SDR0, PESDR1_460SX_HSSL0COEFA, 0xDCB98987);
|
||||
mtdcri(SDR0, PESDR1_460SX_HSSL1COEFA, 0xDCB98987);
|
||||
mtdcri(SDR0, PESDR1_460SX_HSSL2COEFA, 0xDCB98987);
|
||||
mtdcri(SDR0, PESDR1_460SX_HSSL3COEFA, 0xDCB98987);
|
||||
|
||||
mtdcri(SDR0, PESDR2_460SX_HSSL0COEFA, 0xDCB98987);
|
||||
mtdcri(SDR0, PESDR2_460SX_HSSL1COEFA, 0xDCB98987);
|
||||
mtdcri(SDR0, PESDR2_460SX_HSSL2COEFA, 0xDCB98987);
|
||||
mtdcri(SDR0, PESDR2_460SX_HSSL3COEFA, 0xDCB98987);
|
||||
|
||||
/* HSS TX calibration control */
|
||||
mtdcri(SDR0, PESDR0_460SX_HSSL1CALDRV, 0x22222222);
|
||||
mtdcri(SDR0, PESDR1_460SX_HSSL1CALDRV, 0x22220000);
|
||||
mtdcri(SDR0, PESDR2_460SX_HSSL1CALDRV, 0x22220000);
|
||||
|
||||
/* HSS TX slew control */
|
||||
mtdcri(SDR0, PESDR0_460SX_HSSSLEW, 0xFFFFFFFF);
|
||||
mtdcri(SDR0, PESDR1_460SX_HSSSLEW, 0xFFFF0000);
|
||||
mtdcri(SDR0, PESDR2_460SX_HSSSLEW, 0xFFFF0000);
|
||||
|
||||
udelay(100);
|
||||
|
||||
/* De-assert PLLRESET */
|
||||
dcri_clrset(SDR0, PESDR0_PLLLCT2, 0x00000100, 0);
|
||||
|
||||
/* Reset DL, UTL, GPL before configuration */
|
||||
mtdcri(SDR0, PESDR0_460SX_RCSSET,
|
||||
PESDRx_RCSSET_RSTDL | PESDRx_RCSSET_RSTGU);
|
||||
mtdcri(SDR0, PESDR1_460SX_RCSSET,
|
||||
PESDRx_RCSSET_RSTDL | PESDRx_RCSSET_RSTGU);
|
||||
mtdcri(SDR0, PESDR2_460SX_RCSSET,
|
||||
PESDRx_RCSSET_RSTDL | PESDRx_RCSSET_RSTGU);
|
||||
|
||||
udelay(100);
|
||||
|
||||
/*
|
||||
* If bifurcation is not enabled, u-boot would have disabled the
|
||||
* third PCIe port
|
||||
*/
|
||||
if (((mfdcri(SDR0, PESDR1_460SX_HSSCTLSET) & 0x00000001) ==
|
||||
0x00000001)) {
|
||||
printk(KERN_INFO "PCI: PCIE bifurcation setup successfully.\n");
|
||||
printk(KERN_INFO "PCI: Total 3 PCIE ports are present\n");
|
||||
return 3;
|
||||
}
|
||||
|
||||
printk(KERN_INFO "PCI: Total 2 PCIE ports are present\n");
|
||||
return 2;
|
||||
}
|
||||
|
||||
static int ppc460sx_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
|
||||
{
|
||||
|
||||
if (port->endpoint)
|
||||
dcri_clrset(SDR0, port->sdr_base + PESDRn_UTLSET2,
|
||||
0x01000000, 0);
|
||||
else
|
||||
dcri_clrset(SDR0, port->sdr_base + PESDRn_UTLSET2,
|
||||
0, 0x01000000);
|
||||
|
||||
/*Gen-1*/
|
||||
mtdcri(SDR0, port->sdr_base + PESDRn_460SX_RCEI, 0x08000000);
|
||||
|
||||
dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET,
|
||||
(PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL),
|
||||
PESDRx_RCSSET_RSTPYN);
|
||||
|
||||
port->has_ibpre = 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ppc460sx_pciex_init_utl(struct ppc4xx_pciex_port *port)
|
||||
{
|
||||
/* Max 128 Bytes */
|
||||
out_be32 (port->utl_base + PEUTL_PBBSZ, 0x00000000);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct ppc4xx_pciex_hwops ppc460sx_pcie_hwops __initdata = {
|
||||
.core_init = ppc460sx_pciex_core_init,
|
||||
.port_init_hw = ppc460sx_pciex_init_port_hw,
|
||||
.setup_utl = ppc460sx_pciex_init_utl,
|
||||
};
|
||||
|
||||
#endif /* CONFIG_44x */
|
||||
|
||||
#ifdef CONFIG_40x
|
||||
|
|
@ -1089,6 +1206,8 @@ static int __init ppc4xx_pciex_check_core_init(struct device_node *np)
|
|||
}
|
||||
if (of_device_is_compatible(np, "ibm,plb-pciex-460ex"))
|
||||
ppc4xx_pciex_hwops = &ppc460ex_pcie_hwops;
|
||||
if (of_device_is_compatible(np, "ibm,plb-pciex-460sx"))
|
||||
ppc4xx_pciex_hwops = &ppc460sx_pcie_hwops;
|
||||
#endif /* CONFIG_44x */
|
||||
#ifdef CONFIG_40x
|
||||
if (of_device_is_compatible(np, "ibm,plb-pciex-405ex"))
|
||||
|
|
|
|||
|
|
@ -323,6 +323,64 @@
|
|||
#define PESDR0_460EX_IHS1 0x036C
|
||||
#define PESDR0_460EX_IHS2 0x036D
|
||||
|
||||
/*
|
||||
* 460SX addtional DCRs
|
||||
*/
|
||||
#define PESDRn_460SX_RCEI 0x02
|
||||
|
||||
#define PESDR0_460SX_HSSL0DAMP 0x320
|
||||
#define PESDR0_460SX_HSSL1DAMP 0x321
|
||||
#define PESDR0_460SX_HSSL2DAMP 0x322
|
||||
#define PESDR0_460SX_HSSL3DAMP 0x323
|
||||
#define PESDR0_460SX_HSSL4DAMP 0x324
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#define PESDR0_460SX_HSSL5DAMP 0x325
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#define PESDR0_460SX_HSSL6DAMP 0x326
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#define PESDR0_460SX_HSSL7DAMP 0x327
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#define PESDR1_460SX_HSSL0DAMP 0x354
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#define PESDR1_460SX_HSSL1DAMP 0x355
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#define PESDR1_460SX_HSSL2DAMP 0x356
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#define PESDR1_460SX_HSSL3DAMP 0x357
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#define PESDR2_460SX_HSSL0DAMP 0x384
|
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#define PESDR2_460SX_HSSL1DAMP 0x385
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#define PESDR2_460SX_HSSL2DAMP 0x386
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#define PESDR2_460SX_HSSL3DAMP 0x387
|
||||
|
||||
#define PESDR0_460SX_HSSL0COEFA 0x328
|
||||
#define PESDR0_460SX_HSSL1COEFA 0x329
|
||||
#define PESDR0_460SX_HSSL2COEFA 0x32A
|
||||
#define PESDR0_460SX_HSSL3COEFA 0x32B
|
||||
#define PESDR0_460SX_HSSL4COEFA 0x32C
|
||||
#define PESDR0_460SX_HSSL5COEFA 0x32D
|
||||
#define PESDR0_460SX_HSSL6COEFA 0x32E
|
||||
#define PESDR0_460SX_HSSL7COEFA 0x32F
|
||||
|
||||
#define PESDR1_460SX_HSSL0COEFA 0x358
|
||||
#define PESDR1_460SX_HSSL1COEFA 0x359
|
||||
#define PESDR1_460SX_HSSL2COEFA 0x35A
|
||||
#define PESDR1_460SX_HSSL3COEFA 0x35B
|
||||
|
||||
#define PESDR2_460SX_HSSL0COEFA 0x388
|
||||
#define PESDR2_460SX_HSSL1COEFA 0x389
|
||||
#define PESDR2_460SX_HSSL2COEFA 0x38A
|
||||
#define PESDR2_460SX_HSSL3COEFA 0x38B
|
||||
|
||||
#define PESDR0_460SX_HSSL1CALDRV 0x339
|
||||
#define PESDR1_460SX_HSSL1CALDRV 0x361
|
||||
#define PESDR2_460SX_HSSL1CALDRV 0x391
|
||||
|
||||
#define PESDR0_460SX_HSSSLEW 0x338
|
||||
#define PESDR1_460SX_HSSSLEW 0x360
|
||||
#define PESDR2_460SX_HSSSLEW 0x390
|
||||
|
||||
#define PESDR0_460SX_HSSCTLSET 0x31E
|
||||
#define PESDR1_460SX_HSSCTLSET 0x352
|
||||
#define PESDR2_460SX_HSSCTLSET 0x382
|
||||
|
||||
#define PESDR0_460SX_RCSSET 0x304
|
||||
#define PESDR1_460SX_RCSSET 0x344
|
||||
#define PESDR2_460SX_RCSSET 0x374
|
||||
/*
|
||||
* Of the above, some are common offsets from the base
|
||||
*/
|
||||
|
|
|
|||
Loading…
Reference in a new issue