xHCI: store ring's type
When allocate a ring, store its type - four transfer types for endpoint, TYPE_STREAM for stream transfer, and TYPE_COMMAND/TYPE_EVENT for xHCI host. This helps to get rid of three bool function parameters: link_trbs, isoc and consumer. Signed-off-by: Andiry Xu <andiry.xu@amd.com> Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com> Tested-by: Paul Zimmerman <Paul.Zimmerman@synopsys.com>
This commit is contained in:
Andiry Xu
Sarah Sharp
parent
8d3709f3dd
commit
3b72fca09d
3 changed files with 92 additions and 75 deletions
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@ -73,14 +73,14 @@ static void xhci_segment_free(struct xhci_hcd *xhci, struct xhci_segment *seg)
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* related flags, such as End TRB, Toggle Cycle, and no snoop.
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*/
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static void xhci_link_segments(struct xhci_hcd *xhci, struct xhci_segment *prev,
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struct xhci_segment *next, bool link_trbs, bool isoc)
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struct xhci_segment *next, enum xhci_ring_type type)
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{
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u32 val;
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if (!prev || !next)
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return;
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prev->next = next;
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if (link_trbs) {
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if (type != TYPE_EVENT) {
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prev->trbs[TRBS_PER_SEGMENT-1].link.segment_ptr =
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cpu_to_le64(next->dma);
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@ -91,7 +91,8 @@ static void xhci_link_segments(struct xhci_hcd *xhci, struct xhci_segment *prev,
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/* Always set the chain bit with 0.95 hardware */
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/* Set chain bit for isoc rings on AMD 0.96 host */
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if (xhci_link_trb_quirk(xhci) ||
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(isoc && (xhci->quirks & XHCI_AMD_0x96_HOST)))
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(type == TYPE_ISOC &&
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(xhci->quirks & XHCI_AMD_0x96_HOST)))
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val |= TRB_CHAIN;
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prev->trbs[TRBS_PER_SEGMENT-1].link.control = cpu_to_le32(val);
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}
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@ -144,7 +145,7 @@ static void xhci_initialize_ring_info(struct xhci_ring *ring)
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* See section 4.9.1 and figures 15 and 16.
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*/
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static struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
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unsigned int num_segs, bool link_trbs, bool isoc, gfp_t flags)
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unsigned int num_segs, enum xhci_ring_type type, gfp_t flags)
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{
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struct xhci_ring *ring;
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struct xhci_segment *prev;
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@ -154,6 +155,7 @@ static struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
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return NULL;
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INIT_LIST_HEAD(&ring->td_list);
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ring->type = type;
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if (num_segs == 0)
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return ring;
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@ -169,14 +171,15 @@ static struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
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next = xhci_segment_alloc(xhci, flags);
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if (!next)
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goto fail;
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xhci_link_segments(xhci, prev, next, link_trbs, isoc);
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xhci_link_segments(xhci, prev, next, type);
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prev = next;
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num_segs--;
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}
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xhci_link_segments(xhci, prev, ring->first_seg, link_trbs, isoc);
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xhci_link_segments(xhci, prev, ring->first_seg, type);
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if (link_trbs) {
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/* Only event ring does not use link TRB */
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if (type != TYPE_EVENT) {
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/* See section 4.9.2.1 and 6.4.4.1 */
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prev->trbs[TRBS_PER_SEGMENT-1].link.control |=
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cpu_to_le32(LINK_TOGGLE);
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@ -217,16 +220,17 @@ void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci,
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* pointers to the beginning of the ring.
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*/
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static void xhci_reinit_cached_ring(struct xhci_hcd *xhci,
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struct xhci_ring *ring, bool isoc)
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struct xhci_ring *ring, enum xhci_ring_type type)
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{
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struct xhci_segment *seg = ring->first_seg;
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do {
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memset(seg->trbs, 0,
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sizeof(union xhci_trb)*TRBS_PER_SEGMENT);
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/* All endpoint rings have link TRBs */
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xhci_link_segments(xhci, seg, seg->next, 1, isoc);
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xhci_link_segments(xhci, seg, seg->next, type);
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seg = seg->next;
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} while (seg != ring->first_seg);
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ring->type = type;
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xhci_initialize_ring_info(ring);
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/* td list should be empty since all URBs have been cancelled,
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* but just in case...
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@ -528,7 +532,7 @@ struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
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*/
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for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
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stream_info->stream_rings[cur_stream] =
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xhci_ring_alloc(xhci, 1, true, false, mem_flags);
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xhci_ring_alloc(xhci, 1, TYPE_STREAM, mem_flags);
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cur_ring = stream_info->stream_rings[cur_stream];
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if (!cur_ring)
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goto cleanup_rings;
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@ -862,7 +866,7 @@ int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id,
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}
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/* Allocate endpoint 0 ring */
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dev->eps[0].ring = xhci_ring_alloc(xhci, 1, true, false, flags);
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dev->eps[0].ring = xhci_ring_alloc(xhci, 1, TYPE_CTRL, flags);
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if (!dev->eps[0].ring)
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goto fail;
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@ -1300,11 +1304,13 @@ int xhci_endpoint_init(struct xhci_hcd *xhci,
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struct xhci_ring *ep_ring;
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unsigned int max_packet;
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unsigned int max_burst;
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enum xhci_ring_type type;
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u32 max_esit_payload;
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ep_index = xhci_get_endpoint_index(&ep->desc);
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ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
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type = usb_endpoint_type(&ep->desc);
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/* Set up the endpoint ring */
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/*
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* Isochronous endpoint ring needs bigger size because one isoc URB
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@ -1314,10 +1320,10 @@ int xhci_endpoint_init(struct xhci_hcd *xhci,
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*/
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if (usb_endpoint_xfer_isoc(&ep->desc))
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virt_dev->eps[ep_index].new_ring =
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xhci_ring_alloc(xhci, 8, true, true, mem_flags);
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xhci_ring_alloc(xhci, 8, type, mem_flags);
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else
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virt_dev->eps[ep_index].new_ring =
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xhci_ring_alloc(xhci, 1, true, false, mem_flags);
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xhci_ring_alloc(xhci, 1, type, mem_flags);
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if (!virt_dev->eps[ep_index].new_ring) {
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/* Attempt to use the ring cache */
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if (virt_dev->num_rings_cached == 0)
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@ -1327,7 +1333,7 @@ int xhci_endpoint_init(struct xhci_hcd *xhci,
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virt_dev->ring_cache[virt_dev->num_rings_cached] = NULL;
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virt_dev->num_rings_cached--;
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xhci_reinit_cached_ring(xhci, virt_dev->eps[ep_index].new_ring,
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usb_endpoint_xfer_isoc(&ep->desc) ? true : false);
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type);
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}
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virt_dev->eps[ep_index].skip = false;
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ep_ring = virt_dev->eps[ep_index].new_ring;
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@ -2235,7 +2241,7 @@ int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
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goto fail;
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/* Set up the command ring to have one segments for now. */
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xhci->cmd_ring = xhci_ring_alloc(xhci, 1, true, false, flags);
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xhci->cmd_ring = xhci_ring_alloc(xhci, 1, TYPE_COMMAND, flags);
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if (!xhci->cmd_ring)
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goto fail;
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xhci_dbg(xhci, "Allocated command ring at %p\n", xhci->cmd_ring);
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@ -2266,7 +2272,7 @@ int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
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* the event ring segment table (ERST). Section 4.9.3.
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*/
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xhci_dbg(xhci, "// Allocating event ring\n");
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xhci->event_ring = xhci_ring_alloc(xhci, ERST_NUM_SEGS, false, false,
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xhci->event_ring = xhci_ring_alloc(xhci, ERST_NUM_SEGS, TYPE_EVENT,
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flags);
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if (!xhci->event_ring)
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goto fail;
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@ -143,7 +143,7 @@ static void next_trb(struct xhci_hcd *xhci,
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* See Cycle bit rules. SW is the consumer for the event ring only.
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* Don't make a ring full of link TRBs. That would be dumb and this would loop.
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*/
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static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer)
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static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring)
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{
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union xhci_trb *next = ++(ring->dequeue);
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unsigned long long addr;
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@ -153,7 +153,8 @@ static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer
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* the end of an event ring segment (which doesn't have link TRBS)
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*/
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while (last_trb(xhci, ring, ring->deq_seg, next)) {
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if (consumer && last_trb_on_last_seg(xhci, ring, ring->deq_seg, next)) {
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if (ring->type == TYPE_EVENT && last_trb_on_last_seg(xhci,
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ring, ring->deq_seg, next)) {
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ring->cycle_state = (ring->cycle_state ? 0 : 1);
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}
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ring->deq_seg = ring->deq_seg->next;
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@ -181,7 +182,7 @@ static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer
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* prepare_transfer()?
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*/
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static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
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bool consumer, bool more_trbs_coming, bool isoc)
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bool more_trbs_coming)
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{
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u32 chain;
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union xhci_trb *next;
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@ -195,35 +196,35 @@ static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
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* the end of an event ring segment (which doesn't have link TRBS)
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*/
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while (last_trb(xhci, ring, ring->enq_seg, next)) {
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if (!consumer) {
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if (ring != xhci->event_ring) {
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/*
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* If the caller doesn't plan on enqueueing more
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* TDs before ringing the doorbell, then we
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* don't want to give the link TRB to the
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* hardware just yet. We'll give the link TRB
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* back in prepare_ring() just before we enqueue
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* the TD at the top of the ring.
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*/
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if (!chain && !more_trbs_coming)
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break;
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if (ring->type != TYPE_EVENT) {
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/*
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* If the caller doesn't plan on enqueueing more
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* TDs before ringing the doorbell, then we
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* don't want to give the link TRB to the
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* hardware just yet. We'll give the link TRB
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* back in prepare_ring() just before we enqueue
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* the TD at the top of the ring.
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*/
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if (!chain && !more_trbs_coming)
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break;
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/* If we're not dealing with 0.95 hardware or
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* isoc rings on AMD 0.96 host,
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* carry over the chain bit of the previous TRB
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* (which may mean the chain bit is cleared).
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*/
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if (!(isoc && (xhci->quirks & XHCI_AMD_0x96_HOST))
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/* If we're not dealing with 0.95 hardware or
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* isoc rings on AMD 0.96 host,
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* carry over the chain bit of the previous TRB
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* (which may mean the chain bit is cleared).
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*/
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if (!(ring->type == TYPE_ISOC &&
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(xhci->quirks & XHCI_AMD_0x96_HOST))
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&& !xhci_link_trb_quirk(xhci)) {
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next->link.control &=
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cpu_to_le32(~TRB_CHAIN);
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next->link.control |=
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cpu_to_le32(chain);
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}
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/* Give this link TRB to the hardware */
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wmb();
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next->link.control ^= cpu_to_le32(TRB_CYCLE);
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next->link.control &=
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cpu_to_le32(~TRB_CHAIN);
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next->link.control |=
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cpu_to_le32(chain);
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}
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/* Give this link TRB to the hardware */
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wmb();
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next->link.control ^= cpu_to_le32(TRB_CYCLE);
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/* Toggle the cycle bit after the last ring segment. */
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if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
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ring->cycle_state = (ring->cycle_state ? 0 : 1);
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@ -1185,7 +1186,7 @@ static void handle_cmd_completion(struct xhci_hcd *xhci,
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xhci->error_bitmask |= 1 << 6;
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break;
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}
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inc_deq(xhci, xhci->cmd_ring, false);
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inc_deq(xhci, xhci->cmd_ring);
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}
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static void handle_vendor_event(struct xhci_hcd *xhci,
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@ -1398,7 +1399,7 @@ static void handle_port_status(struct xhci_hcd *xhci,
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cleanup:
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/* Update event ring dequeue pointer before dropping the lock */
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inc_deq(xhci, xhci->event_ring, true);
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inc_deq(xhci, xhci->event_ring);
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/* Don't make the USB core poll the roothub if we got a bad port status
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* change event. Besides, at that point we can't tell which roothub
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@ -1593,8 +1594,8 @@ static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
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} else {
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/* Update ring dequeue pointer */
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while (ep_ring->dequeue != td->last_trb)
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inc_deq(xhci, ep_ring, false);
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inc_deq(xhci, ep_ring, false);
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inc_deq(xhci, ep_ring);
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inc_deq(xhci, ep_ring);
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}
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td_cleanup:
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@ -1842,8 +1843,8 @@ static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
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/* Update ring dequeue pointer */
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while (ep_ring->dequeue != td->last_trb)
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inc_deq(xhci, ep_ring, false);
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inc_deq(xhci, ep_ring, false);
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inc_deq(xhci, ep_ring);
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inc_deq(xhci, ep_ring);
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return finish_td(xhci, td, NULL, event, ep, status, true);
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}
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@ -2230,7 +2231,7 @@ static int handle_tx_event(struct xhci_hcd *xhci,
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* Will roll back to continue process missed tds.
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*/
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if (trb_comp_code == COMP_MISSED_INT || !ep->skip) {
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inc_deq(xhci, xhci->event_ring, true);
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inc_deq(xhci, xhci->event_ring);
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}
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if (ret) {
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@ -2345,7 +2346,7 @@ static int xhci_handle_event(struct xhci_hcd *xhci)
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if (update_ptrs)
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/* Update SW event ring dequeue pointer */
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inc_deq(xhci, xhci->event_ring, true);
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inc_deq(xhci, xhci->event_ring);
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/* Are there more items on the event ring? Caller will call us again to
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* check.
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@ -2461,7 +2462,7 @@ irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd)
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* prepare_transfer()?
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*/
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static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
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bool consumer, bool more_trbs_coming, bool isoc,
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bool more_trbs_coming,
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u32 field1, u32 field2, u32 field3, u32 field4)
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{
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struct xhci_generic_trb *trb;
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@ -2471,7 +2472,7 @@ static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
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trb->field[1] = cpu_to_le32(field2);
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trb->field[2] = cpu_to_le32(field3);
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trb->field[3] = cpu_to_le32(field4);
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inc_enq(xhci, ring, consumer, more_trbs_coming, isoc);
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inc_enq(xhci, ring, more_trbs_coming);
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}
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/*
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@ -2479,7 +2480,7 @@ static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
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* FIXME allocate segments if the ring is full.
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*/
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static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
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u32 ep_state, unsigned int num_trbs, bool isoc, gfp_t mem_flags)
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u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
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{
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/* Make sure the endpoint has been added to xHC schedule */
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switch (ep_state) {
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@ -2524,8 +2525,9 @@ static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
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/* If we're not dealing with 0.95 hardware or isoc rings
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* on AMD 0.96 host, clear the chain bit.
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*/
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if (!xhci_link_trb_quirk(xhci) && !(isoc &&
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(xhci->quirks & XHCI_AMD_0x96_HOST)))
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if (!xhci_link_trb_quirk(xhci) &&
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!(ring->type == TYPE_ISOC &&
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(xhci->quirks & XHCI_AMD_0x96_HOST)))
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next->link.control &= cpu_to_le32(~TRB_CHAIN);
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else
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next->link.control |= cpu_to_le32(TRB_CHAIN);
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@ -2553,7 +2555,6 @@ static int prepare_transfer(struct xhci_hcd *xhci,
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unsigned int num_trbs,
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struct urb *urb,
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unsigned int td_index,
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bool isoc,
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gfp_t mem_flags)
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{
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int ret;
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@ -2571,7 +2572,7 @@ static int prepare_transfer(struct xhci_hcd *xhci,
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ret = prepare_ring(xhci, ep_ring,
|
||||
le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
|
||||
num_trbs, isoc, mem_flags);
|
||||
num_trbs, mem_flags);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
|
@ -2781,7 +2782,7 @@ static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
|
|||
|
||||
trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
|
||||
ep_index, urb->stream_id,
|
||||
num_trbs, urb, 0, false, mem_flags);
|
||||
num_trbs, urb, 0, mem_flags);
|
||||
if (trb_buff_len < 0)
|
||||
return trb_buff_len;
|
||||
|
||||
|
|
@ -2869,7 +2870,7 @@ static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
|
|||
more_trbs_coming = true;
|
||||
else
|
||||
more_trbs_coming = false;
|
||||
queue_trb(xhci, ep_ring, false, more_trbs_coming, false,
|
||||
queue_trb(xhci, ep_ring, more_trbs_coming,
|
||||
lower_32_bits(addr),
|
||||
upper_32_bits(addr),
|
||||
length_field,
|
||||
|
|
@ -2951,7 +2952,7 @@ int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
|
|||
|
||||
ret = prepare_transfer(xhci, xhci->devs[slot_id],
|
||||
ep_index, urb->stream_id,
|
||||
num_trbs, urb, 0, false, mem_flags);
|
||||
num_trbs, urb, 0, mem_flags);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
|
|
@ -3023,7 +3024,7 @@ int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
|
|||
more_trbs_coming = true;
|
||||
else
|
||||
more_trbs_coming = false;
|
||||
queue_trb(xhci, ep_ring, false, more_trbs_coming, false,
|
||||
queue_trb(xhci, ep_ring, more_trbs_coming,
|
||||
lower_32_bits(addr),
|
||||
upper_32_bits(addr),
|
||||
length_field,
|
||||
|
|
@ -3080,7 +3081,7 @@ int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
|
|||
num_trbs++;
|
||||
ret = prepare_transfer(xhci, xhci->devs[slot_id],
|
||||
ep_index, urb->stream_id,
|
||||
num_trbs, urb, 0, false, mem_flags);
|
||||
num_trbs, urb, 0, mem_flags);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
|
|
@ -3113,7 +3114,7 @@ int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
|
|||
}
|
||||
}
|
||||
|
||||
queue_trb(xhci, ep_ring, false, true, false,
|
||||
queue_trb(xhci, ep_ring, true,
|
||||
setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
|
||||
le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
|
||||
TRB_LEN(8) | TRB_INTR_TARGET(0),
|
||||
|
|
@ -3133,7 +3134,7 @@ int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
|
|||
if (urb->transfer_buffer_length > 0) {
|
||||
if (setup->bRequestType & USB_DIR_IN)
|
||||
field |= TRB_DIR_IN;
|
||||
queue_trb(xhci, ep_ring, false, true, false,
|
||||
queue_trb(xhci, ep_ring, true,
|
||||
lower_32_bits(urb->transfer_dma),
|
||||
upper_32_bits(urb->transfer_dma),
|
||||
length_field,
|
||||
|
|
@ -3149,7 +3150,7 @@ int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
|
|||
field = 0;
|
||||
else
|
||||
field = TRB_DIR_IN;
|
||||
queue_trb(xhci, ep_ring, false, false, false,
|
||||
queue_trb(xhci, ep_ring, false,
|
||||
0,
|
||||
0,
|
||||
TRB_INTR_TARGET(0),
|
||||
|
|
@ -3289,8 +3290,7 @@ static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
|
|||
trbs_per_td = count_isoc_trbs_needed(xhci, urb, i);
|
||||
|
||||
ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
|
||||
urb->stream_id, trbs_per_td, urb, i, true,
|
||||
mem_flags);
|
||||
urb->stream_id, trbs_per_td, urb, i, mem_flags);
|
||||
if (ret < 0) {
|
||||
if (i == 0)
|
||||
return ret;
|
||||
|
|
@ -3360,7 +3360,7 @@ static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
|
|||
remainder |
|
||||
TRB_INTR_TARGET(0);
|
||||
|
||||
queue_trb(xhci, ep_ring, false, more_trbs_coming, true,
|
||||
queue_trb(xhci, ep_ring, more_trbs_coming,
|
||||
lower_32_bits(addr),
|
||||
upper_32_bits(addr),
|
||||
length_field,
|
||||
|
|
@ -3443,7 +3443,7 @@ int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
|
|||
* Do not insert any td of the urb to the ring if the check failed.
|
||||
*/
|
||||
ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
|
||||
num_trbs, true, mem_flags);
|
||||
num_trbs, mem_flags);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
|
@ -3502,7 +3502,7 @@ static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2,
|
|||
reserved_trbs++;
|
||||
|
||||
ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
|
||||
reserved_trbs, false, GFP_ATOMIC);
|
||||
reserved_trbs, GFP_ATOMIC);
|
||||
if (ret < 0) {
|
||||
xhci_err(xhci, "ERR: No room for command on command ring\n");
|
||||
if (command_must_succeed)
|
||||
|
|
@ -3510,8 +3510,8 @@ static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2,
|
|||
"unfailable commands failed.\n");
|
||||
return ret;
|
||||
}
|
||||
queue_trb(xhci, xhci->cmd_ring, false, false, false, field1, field2,
|
||||
field3, field4 | xhci->cmd_ring->cycle_state);
|
||||
queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
|
||||
field4 | xhci->cmd_ring->cycle_state);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1250,6 +1250,16 @@ struct xhci_dequeue_state {
|
|||
int new_cycle_state;
|
||||
};
|
||||
|
||||
enum xhci_ring_type {
|
||||
TYPE_CTRL = 0,
|
||||
TYPE_ISOC,
|
||||
TYPE_BULK,
|
||||
TYPE_INTR,
|
||||
TYPE_STREAM,
|
||||
TYPE_COMMAND,
|
||||
TYPE_EVENT,
|
||||
};
|
||||
|
||||
struct xhci_ring {
|
||||
struct xhci_segment *first_seg;
|
||||
union xhci_trb *enqueue;
|
||||
|
|
@ -1266,6 +1276,7 @@ struct xhci_ring {
|
|||
*/
|
||||
u32 cycle_state;
|
||||
unsigned int stream_id;
|
||||
enum xhci_ring_type type;
|
||||
bool last_td_was_short;
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue