Au1100 FB driver uplift for 2.6.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Acked-by: Antonino Daplas <adaplas@pol.net>
This commit is contained in:
Pete Popov
Ralf Baechle
parent
172546bf60
commit
3b495f2bb7
6 changed files with 883 additions and 811 deletions
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@ -41,8 +41,42 @@ static struct platform_device au1xxx_usb_ohci_device = {
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.resource = au1xxx_usb_ohci_resources,
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};
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/*** AU1100 LCD controller ***/
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#ifdef CONFIG_FB_AU1100
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static struct resource au1100_lcd_resources[] = {
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[0] = {
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.start = LCD_PHYS_ADDR,
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.end = LCD_PHYS_ADDR + 0x800 - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = AU1100_LCD_INT,
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.end = AU1100_LCD_INT,
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.flags = IORESOURCE_IRQ,
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}
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};
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static u64 au1100_lcd_dmamask = ~(u32)0;
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static struct platform_device au1100_lcd_device = {
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.name = "au1100-lcd",
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.id = 0,
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.dev = {
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.dma_mask = &au1100_lcd_dmamask,
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.coherent_dma_mask = 0xffffffff,
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},
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.num_resources = ARRAY_SIZE(au1100_lcd_resources),
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.resource = au1100_lcd_resources,
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};
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#endif
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static struct platform_device *au1xxx_platform_devices[] __initdata = {
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&au1xxx_usb_ohci_device,
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#ifdef CONFIG_FB_AU1100
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&au1100_lcd_device,
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#endif
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};
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int au1xxx_platform_init(void)
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@ -106,8 +106,6 @@ void __init plat_setup(void)
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/*strcat(argptr, " video=au1100fb:panel:Sharp_320x240_16");*/
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#ifdef CONFIG_MIPS_HYDROGEN3
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strcat(argptr, " video=au1100fb:panel:Hydrogen_3_NEC_panel_320x240,nohwcursor");
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#else
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strcat(argptr, " video=au1100fb:panel:s10,nohwcursor");
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#endif
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}
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#endif
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@ -86,7 +86,7 @@ obj-$(CONFIG_FB_CIRRUS) += cirrusfb.o
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obj-$(CONFIG_FB_ASILIANT) += asiliantfb.o
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obj-$(CONFIG_FB_PXA) += pxafb.o
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obj-$(CONFIG_FB_W100) += w100fb.o
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obj-$(CONFIG_FB_AU1100) += au1100fb.o fbgen.o
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obj-$(CONFIG_FB_AU1100) += au1100fb.o
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obj-$(CONFIG_FB_PMAG_AA) += pmag-aa-fb.o
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obj-$(CONFIG_FB_PMAG_BA) += pmag-ba-fb.o
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obj-$(CONFIG_FB_PMAGB_B) += pmagb-b-fb.o
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File diff suppressed because it is too large
Load diff
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@ -30,352 +30,352 @@
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#ifndef _AU1100LCD_H
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#define _AU1100LCD_H
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/********************************************************************/
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#define uint32 unsigned long
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typedef volatile struct
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{
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uint32 lcd_control;
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uint32 lcd_intstatus;
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uint32 lcd_intenable;
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uint32 lcd_horztiming;
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uint32 lcd_verttiming;
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uint32 lcd_clkcontrol;
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uint32 lcd_dmaaddr0;
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uint32 lcd_dmaaddr1;
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uint32 lcd_words;
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uint32 lcd_pwmdiv;
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uint32 lcd_pwmhi;
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uint32 reserved[(0x0400-0x002C)/4];
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uint32 lcd_pallettebase[256];
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#include <asm/mach-au1x00/au1000.h>
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} AU1100_LCD;
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#define print_err(f, arg...) printk(KERN_ERR DRIVER_NAME ": " f "\n", ## arg)
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#define print_warn(f, arg...) printk(KERN_WARNING DRIVER_NAME ": " f "\n", ## arg)
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#define print_info(f, arg...) printk(KERN_INFO DRIVER_NAME ": " f "\n", ## arg)
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/********************************************************************/
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#define AU1100_LCD_ADDR 0xB5000000
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/*
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* Register bit definitions
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*/
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/* lcd_control */
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#define LCD_CONTROL_SBPPF (7<<18)
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#define LCD_CONTROL_SBPPF_655 (0<<18)
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#define LCD_CONTROL_SBPPF_565 (1<<18)
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#define LCD_CONTROL_SBPPF_556 (2<<18)
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#define LCD_CONTROL_SBPPF_1555 (3<<18)
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#define LCD_CONTROL_SBPPF_5551 (4<<18)
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#define LCD_CONTROL_WP (1<<17)
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#define LCD_CONTROL_WD (1<<16)
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#define LCD_CONTROL_C (1<<15)
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#define LCD_CONTROL_SM (3<<13)
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#define LCD_CONTROL_SM_0 (0<<13)
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#define LCD_CONTROL_SM_90 (1<<13)
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#define LCD_CONTROL_SM_180 (2<<13)
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#define LCD_CONTROL_SM_270 (3<<13)
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#define LCD_CONTROL_DB (1<<12)
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#define LCD_CONTROL_CCO (1<<11)
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#define LCD_CONTROL_DP (1<<10)
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#define LCD_CONTROL_PO (3<<8)
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#define LCD_CONTROL_PO_00 (0<<8)
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#define LCD_CONTROL_PO_01 (1<<8)
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#define LCD_CONTROL_PO_10 (2<<8)
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#define LCD_CONTROL_PO_11 (3<<8)
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#define LCD_CONTROL_MPI (1<<7)
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#define LCD_CONTROL_PT (1<<6)
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#define LCD_CONTROL_PC (1<<5)
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#define LCD_CONTROL_BPP (7<<1)
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#define LCD_CONTROL_BPP_1 (0<<1)
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#define LCD_CONTROL_BPP_2 (1<<1)
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#define LCD_CONTROL_BPP_4 (2<<1)
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#define LCD_CONTROL_BPP_8 (3<<1)
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#define LCD_CONTROL_BPP_12 (4<<1)
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#define LCD_CONTROL_BPP_16 (5<<1)
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#define LCD_CONTROL_GO (1<<0)
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/* lcd_intstatus, lcd_intenable */
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#define LCD_INT_SD (1<<7)
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#define LCD_INT_OF (1<<6)
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#define LCD_INT_UF (1<<5)
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#define LCD_INT_SA (1<<3)
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#define LCD_INT_SS (1<<2)
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#define LCD_INT_S1 (1<<1)
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#define LCD_INT_S0 (1<<0)
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/* lcd_horztiming */
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#define LCD_HORZTIMING_HN2 (255<<24)
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#define LCD_HORZTIMING_HN2_N(N) (((N)-1)<<24)
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#define LCD_HORZTIMING_HN1 (255<<16)
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#define LCD_HORZTIMING_HN1_N(N) (((N)-1)<<16)
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#define LCD_HORZTIMING_HPW (63<<10)
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#define LCD_HORZTIMING_HPW_N(N) (((N)-1)<<10)
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#define LCD_HORZTIMING_PPL (1023<<0)
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#define LCD_HORZTIMING_PPL_N(N) (((N)-1)<<0)
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/* lcd_verttiming */
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#define LCD_VERTTIMING_VN2 (255<<24)
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#define LCD_VERTTIMING_VN2_N(N) (((N)-1)<<24)
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#define LCD_VERTTIMING_VN1 (255<<16)
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#define LCD_VERTTIMING_VN1_N(N) (((N)-1)<<16)
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#define LCD_VERTTIMING_VPW (63<<10)
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#define LCD_VERTTIMING_VPW_N(N) (((N)-1)<<10)
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#define LCD_VERTTIMING_LPP (1023<<0)
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#define LCD_VERTTIMING_LPP_N(N) (((N)-1)<<0)
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/* lcd_clkcontrol */
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#define LCD_CLKCONTROL_IB (1<<18)
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#define LCD_CLKCONTROL_IC (1<<17)
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#define LCD_CLKCONTROL_IH (1<<16)
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#define LCD_CLKCONTROL_IV (1<<15)
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#define LCD_CLKCONTROL_BF (31<<10)
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#define LCD_CLKCONTROL_BF_N(N) (((N)-1)<<10)
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#define LCD_CLKCONTROL_PCD (1023<<0)
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#define LCD_CLKCONTROL_PCD_N(N) ((N)<<0)
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/* lcd_pwmdiv */
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#define LCD_PWMDIV_EN (1<<12)
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#define LCD_PWMDIV_PWMDIV (2047<<0)
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#define LCD_PWMDIV_PWMDIV_N(N) (((N)-1)<<0)
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/* lcd_pwmhi */
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#define LCD_PWMHI_PWMHI1 (2047<<12)
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#define LCD_PWMHI_PWMHI1_N(N) ((N)<<12)
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#define LCD_PWMHI_PWMHI0 (2047<<0)
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#define LCD_PWMHI_PWMHI0_N(N) ((N)<<0)
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/* lcd_pallettebase - MONOCHROME */
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#define LCD_PALLETTE_MONO_MI (15<<0)
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#define LCD_PALLETTE_MONO_MI_N(N) ((N)<<0)
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/* lcd_pallettebase - COLOR */
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#define LCD_PALLETTE_COLOR_BI (15<<8)
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#define LCD_PALLETTE_COLOR_BI_N(N) ((N)<<8)
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#define LCD_PALLETTE_COLOR_GI (15<<4)
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#define LCD_PALLETTE_COLOR_GI_N(N) ((N)<<4)
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#define LCD_PALLETTE_COLOR_RI (15<<0)
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#define LCD_PALLETTE_COLOR_RI_N(N) ((N)<<0)
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/* lcd_palletebase - COLOR TFT PALLETIZED */
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#define LCD_PALLETTE_TFT_DC (65535<<0)
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#define LCD_PALLETTE_TFT_DC_N(N) ((N)<<0)
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/********************************************************************/
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struct known_lcd_panels
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{
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uint32 xres;
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uint32 yres;
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uint32 bpp;
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unsigned char panel_name[256];
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uint32 mode_control;
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uint32 mode_horztiming;
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uint32 mode_verttiming;
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uint32 mode_clkcontrol;
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uint32 mode_pwmdiv;
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uint32 mode_pwmhi;
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uint32 mode_toyclksrc;
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uint32 mode_backlight;
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};
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#if defined(__BIG_ENDIAN)
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#define LCD_DEFAULT_PIX_FORMAT LCD_CONTROL_PO_11
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#if DEBUG
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#define print_dbg(f, arg...) printk(__FILE__ ": " f "\n", ## arg)
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#else
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#define LCD_DEFAULT_PIX_FORMAT LCD_CONTROL_PO_00
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#define print_dbg(f, arg...) do {} while (0)
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#endif
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/*
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* The fb driver assumes that AUX PLL is at 48MHz. That can
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* cover up to 800x600 resolution; if you need higher resolution,
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* you should modify the driver as needed, not just this structure.
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*/
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struct known_lcd_panels panels[] =
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{
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{ /* 0: Pb1100 LCDA: Sharp 320x240 TFT panel */
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320, /* xres */
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240, /* yres */
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16, /* bpp */
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#if defined(__BIG_ENDIAN)
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#define LCD_CONTROL_DEFAULT_PO LCD_CONTROL_PO_11
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#else
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#define LCD_CONTROL_DEFAULT_PO LCD_CONTROL_PO_00
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#endif
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#define LCD_CONTROL_DEFAULT_SBPPF LCD_CONTROL_SBPPF_565
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"Sharp_320x240_16",
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/* mode_control */
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/********************************************************************/
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/* LCD controller restrictions */
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#define AU1100_LCD_MAX_XRES 800
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#define AU1100_LCD_MAX_YRES 600
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#define AU1100_LCD_MAX_BPP 16
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#define AU1100_LCD_MAX_CLK 48000000
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#define AU1100_LCD_NBR_PALETTE_ENTRIES 256
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/* Default number of visible screen buffer to allocate */
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#define AU1100FB_NBR_VIDEO_BUFFERS 4
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/********************************************************************/
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struct au1100fb_panel
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{
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const char name[25]; /* Full name <vendor>_<model> */
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u32 control_base; /* Mode-independent control values */
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u32 clkcontrol_base; /* Panel pixclock preferences */
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u32 horztiming;
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u32 verttiming;
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u32 xres; /* Maximum horizontal resolution */
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u32 yres; /* Maximum vertical resolution */
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u32 bpp; /* Maximum depth supported */
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};
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struct au1100fb_regs
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{
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u32 lcd_control;
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u32 lcd_intstatus;
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u32 lcd_intenable;
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u32 lcd_horztiming;
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u32 lcd_verttiming;
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u32 lcd_clkcontrol;
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u32 lcd_dmaaddr0;
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u32 lcd_dmaaddr1;
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u32 lcd_words;
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u32 lcd_pwmdiv;
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u32 lcd_pwmhi;
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u32 reserved[(0x0400-0x002C)/4];
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u32 lcd_pallettebase[256];
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};
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struct au1100fb_device {
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struct fb_info info; /* FB driver info record */
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struct au1100fb_panel *panel; /* Panel connected to this device */
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struct au1100fb_regs* regs; /* Registers memory map */
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size_t regs_len;
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unsigned int regs_phys;
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unsigned char* fb_mem; /* FrameBuffer memory map */
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size_t fb_len;
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dma_addr_t fb_phys;
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};
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/********************************************************************/
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#define LCD_CONTROL (AU1100_LCD_BASE + 0x0)
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#define LCD_CONTROL_SBB_BIT 21
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#define LCD_CONTROL_SBB_MASK (0x3 << LCD_CONTROL_SBB_BIT)
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#define LCD_CONTROL_SBB_1 (0 << LCD_CONTROL_SBB_BIT)
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#define LCD_CONTROL_SBB_2 (1 << LCD_CONTROL_SBB_BIT)
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#define LCD_CONTROL_SBB_3 (2 << LCD_CONTROL_SBB_BIT)
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#define LCD_CONTROL_SBB_4 (3 << LCD_CONTROL_SBB_BIT)
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#define LCD_CONTROL_SBPPF_BIT 18
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#define LCD_CONTROL_SBPPF_MASK (0x7 << LCD_CONTROL_SBPPF_BIT)
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#define LCD_CONTROL_SBPPF_655 (0 << LCD_CONTROL_SBPPF_BIT)
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#define LCD_CONTROL_SBPPF_565 (1 << LCD_CONTROL_SBPPF_BIT)
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#define LCD_CONTROL_SBPPF_556 (2 << LCD_CONTROL_SBPPF_BIT)
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#define LCD_CONTROL_SBPPF_1555 (3 << LCD_CONTROL_SBPPF_BIT)
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#define LCD_CONTROL_SBPPF_5551 (4 << LCD_CONTROL_SBPPF_BIT)
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#define LCD_CONTROL_WP (1<<17)
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#define LCD_CONTROL_WD (1<<16)
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#define LCD_CONTROL_C (1<<15)
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#define LCD_CONTROL_SM_BIT 13
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#define LCD_CONTROL_SM_MASK (0x3 << LCD_CONTROL_SM_BIT)
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#define LCD_CONTROL_SM_0 (0 << LCD_CONTROL_SM_BIT)
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#define LCD_CONTROL_SM_90 (1 << LCD_CONTROL_SM_BIT)
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#define LCD_CONTROL_SM_180 (2 << LCD_CONTROL_SM_BIT)
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#define LCD_CONTROL_SM_270 (3 << LCD_CONTROL_SM_BIT)
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#define LCD_CONTROL_DB (1<<12)
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#define LCD_CONTROL_CCO (1<<11)
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#define LCD_CONTROL_DP (1<<10)
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#define LCD_CONTROL_PO_BIT 8
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#define LCD_CONTROL_PO_MASK (0x3 << LCD_CONTROL_PO_BIT)
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#define LCD_CONTROL_PO_00 (0 << LCD_CONTROL_PO_BIT)
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#define LCD_CONTROL_PO_01 (1 << LCD_CONTROL_PO_BIT)
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#define LCD_CONTROL_PO_10 (2 << LCD_CONTROL_PO_BIT)
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#define LCD_CONTROL_PO_11 (3 << LCD_CONTROL_PO_BIT)
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#define LCD_CONTROL_MPI (1<<7)
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#define LCD_CONTROL_PT (1<<6)
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#define LCD_CONTROL_PC (1<<5)
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#define LCD_CONTROL_BPP_BIT 1
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#define LCD_CONTROL_BPP_MASK (0x7 << LCD_CONTROL_BPP_BIT)
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#define LCD_CONTROL_BPP_1 (0 << LCD_CONTROL_BPP_BIT)
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#define LCD_CONTROL_BPP_2 (1 << LCD_CONTROL_BPP_BIT)
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#define LCD_CONTROL_BPP_4 (2 << LCD_CONTROL_BPP_BIT)
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#define LCD_CONTROL_BPP_8 (3 << LCD_CONTROL_BPP_BIT)
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#define LCD_CONTROL_BPP_12 (4 << LCD_CONTROL_BPP_BIT)
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#define LCD_CONTROL_BPP_16 (5 << LCD_CONTROL_BPP_BIT)
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#define LCD_CONTROL_GO (1<<0)
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#define LCD_INTSTATUS (AU1100_LCD_BASE + 0x4)
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#define LCD_INTENABLE (AU1100_LCD_BASE + 0x8)
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#define LCD_INT_SD (1<<7)
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#define LCD_INT_OF (1<<6)
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#define LCD_INT_UF (1<<5)
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#define LCD_INT_SA (1<<3)
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#define LCD_INT_SS (1<<2)
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#define LCD_INT_S1 (1<<1)
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#define LCD_INT_S0 (1<<0)
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#define LCD_HORZTIMING (AU1100_LCD_BASE + 0xC)
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#define LCD_HORZTIMING_HN2_BIT 24
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#define LCD_HORZTIMING_HN2_MASK (0xFF << LCD_HORZTIMING_HN2_BIT)
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#define LCD_HORZTIMING_HN2_N(N) ((((N)-1) << LCD_HORZTIMING_HN2_BIT) & LCD_HORZTIMING_HN2_MASK)
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#define LCD_HORZTIMING_HN1_BIT 16
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#define LCD_HORZTIMING_HN1_MASK (0xFF << LCD_HORZTIMING_HN1_BIT)
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#define LCD_HORZTIMING_HN1_N(N) ((((N)-1) << LCD_HORZTIMING_HN1_BIT) & LCD_HORZTIMING_HN1_MASK)
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#define LCD_HORZTIMING_HPW_BIT 10
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#define LCD_HORZTIMING_HPW_MASK (0x3F << LCD_HORZTIMING_HPW_BIT)
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#define LCD_HORZTIMING_HPW_N(N) ((((N)-1) << LCD_HORZTIMING_HPW_BIT) & LCD_HORZTIMING_HPW_MASK)
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#define LCD_HORZTIMING_PPL_BIT 0
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#define LCD_HORZTIMING_PPL_MASK (0x3FF << LCD_HORZTIMING_PPL_BIT)
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#define LCD_HORZTIMING_PPL_N(N) ((((N)-1) << LCD_HORZTIMING_PPL_BIT) & LCD_HORZTIMING_PPL_MASK)
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#define LCD_VERTTIMING (AU1100_LCD_BASE + 0x10)
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#define LCD_VERTTIMING_VN2_BIT 24
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#define LCD_VERTTIMING_VN2_MASK (0xFF << LCD_VERTTIMING_VN2_BIT)
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#define LCD_VERTTIMING_VN2_N(N) ((((N)-1) << LCD_VERTTIMING_VN2_BIT) & LCD_VERTTIMING_VN2_MASK)
|
||||
#define LCD_VERTTIMING_VN1_BIT 16
|
||||
#define LCD_VERTTIMING_VN1_MASK (0xFF << LCD_VERTTIMING_VN1_BIT)
|
||||
#define LCD_VERTTIMING_VN1_N(N) ((((N)-1) << LCD_VERTTIMING_VN1_BIT) & LCD_VERTTIMING_VN1_MASK)
|
||||
#define LCD_VERTTIMING_VPW_BIT 10
|
||||
#define LCD_VERTTIMING_VPW_MASK (0x3F << LCD_VERTTIMING_VPW_BIT)
|
||||
#define LCD_VERTTIMING_VPW_N(N) ((((N)-1) << LCD_VERTTIMING_VPW_BIT) & LCD_VERTTIMING_VPW_MASK)
|
||||
#define LCD_VERTTIMING_LPP_BIT 0
|
||||
#define LCD_VERTTIMING_LPP_MASK (0x3FF << LCD_VERTTIMING_LPP_BIT)
|
||||
#define LCD_VERTTIMING_LPP_N(N) ((((N)-1) << LCD_VERTTIMING_LPP_BIT) & LCD_VERTTIMING_LPP_MASK)
|
||||
|
||||
#define LCD_CLKCONTROL (AU1100_LCD_BASE + 0x14)
|
||||
#define LCD_CLKCONTROL_IB (1<<18)
|
||||
#define LCD_CLKCONTROL_IC (1<<17)
|
||||
#define LCD_CLKCONTROL_IH (1<<16)
|
||||
#define LCD_CLKCONTROL_IV (1<<15)
|
||||
#define LCD_CLKCONTROL_BF_BIT 10
|
||||
#define LCD_CLKCONTROL_BF_MASK (0x1F << LCD_CLKCONTROL_BF_BIT)
|
||||
#define LCD_CLKCONTROL_BF_N(N) ((((N)-1) << LCD_CLKCONTROL_BF_BIT) & LCD_CLKCONTROL_BF_MASK)
|
||||
#define LCD_CLKCONTROL_PCD_BIT 0
|
||||
#define LCD_CLKCONTROL_PCD_MASK (0x3FF << LCD_CLKCONTROL_PCD_BIT)
|
||||
#define LCD_CLKCONTROL_PCD_N(N) (((N) << LCD_CLKCONTROL_PCD_BIT) & LCD_CLKCONTROL_PCD_MASK)
|
||||
|
||||
#define LCD_DMAADDR0 (AU1100_LCD_BASE + 0x18)
|
||||
#define LCD_DMAADDR1 (AU1100_LCD_BASE + 0x1C)
|
||||
#define LCD_DMA_SA_BIT 5
|
||||
#define LCD_DMA_SA_MASK (0x7FFFFFF << LCD_DMA_SA_BIT)
|
||||
#define LCD_DMA_SA_N(N) ((N) & LCD_DMA_SA_MASK)
|
||||
|
||||
#define LCD_WORDS (AU1100_LCD_BASE + 0x20)
|
||||
#define LCD_WRD_WRDS_BIT 0
|
||||
#define LCD_WRD_WRDS_MASK (0xFFFFFFFF << LCD_WRD_WRDS_BIT)
|
||||
#define LCD_WRD_WRDS_N(N) ((((N)-1) << LCD_WRD_WRDS_BIT) & LCD_WRD_WRDS_MASK)
|
||||
|
||||
#define LCD_PWMDIV (AU1100_LCD_BASE + 0x24)
|
||||
#define LCD_PWMDIV_EN (1<<12)
|
||||
#define LCD_PWMDIV_PWMDIV_BIT 0
|
||||
#define LCD_PWMDIV_PWMDIV_MASK (0xFFF << LCD_PWMDIV_PWMDIV_BIT)
|
||||
#define LCD_PWMDIV_PWMDIV_N(N) ((((N)-1) << LCD_PWMDIV_PWMDIV_BIT) & LCD_PWMDIV_PWMDIV_MASK)
|
||||
|
||||
#define LCD_PWMHI (AU1100_LCD_BASE + 0x28)
|
||||
#define LCD_PWMHI_PWMHI1_BIT 12
|
||||
#define LCD_PWMHI_PWMHI1_MASK (0xFFF << LCD_PWMHI_PWMHI1_BIT)
|
||||
#define LCD_PWMHI_PWMHI1_N(N) (((N) << LCD_PWMHI_PWMHI1_BIT) & LCD_PWMHI_PWMHI1_MASK)
|
||||
#define LCD_PWMHI_PWMHI0_BIT 0
|
||||
#define LCD_PWMHI_PWMHI0_MASK (0xFFF << LCD_PWMHI_PWMHI0_BIT)
|
||||
#define LCD_PWMHI_PWMHI0_N(N) (((N) << LCD_PWMHI_PWMHI0_BIT) & LCD_PWMHI_PWMHI0_MASK)
|
||||
|
||||
#define LCD_PALLETTEBASE (AU1100_LCD_BASE + 0x400)
|
||||
#define LCD_PALLETTE_MONO_MI_BIT 0
|
||||
#define LCD_PALLETTE_MONO_MI_MASK (0xF << LCD_PALLETTE_MONO_MI_BIT)
|
||||
#define LCD_PALLETTE_MONO_MI_N(N) (((N)<< LCD_PALLETTE_MONO_MI_BIT) & LCD_PALLETTE_MONO_MI_MASK)
|
||||
|
||||
#define LCD_PALLETTE_COLOR_RI_BIT 8
|
||||
#define LCD_PALLETTE_COLOR_RI_MASK (0xF << LCD_PALLETTE_COLOR_RI_BIT)
|
||||
#define LCD_PALLETTE_COLOR_RI_N(N) (((N)<< LCD_PALLETTE_COLOR_RI_BIT) & LCD_PALLETTE_COLOR_RI_MASK)
|
||||
#define LCD_PALLETTE_COLOR_GI_BIT 4
|
||||
#define LCD_PALLETTE_COLOR_GI_MASK (0xF << LCD_PALLETTE_COLOR_GI_BIT)
|
||||
#define LCD_PALLETTE_COLOR_GI_N(N) (((N)<< LCD_PALLETTE_COLOR_GI_BIT) & LCD_PALLETTE_COLOR_GI_MASK)
|
||||
#define LCD_PALLETTE_COLOR_BI_BIT 0
|
||||
#define LCD_PALLETTE_COLOR_BI_MASK (0xF << LCD_PALLETTE_COLOR_BI_BIT)
|
||||
#define LCD_PALLETTE_COLOR_BI_N(N) (((N)<< LCD_PALLETTE_COLOR_BI_BIT) & LCD_PALLETTE_COLOR_BI_MASK)
|
||||
|
||||
#define LCD_PALLETTE_TFT_DC_BIT 0
|
||||
#define LCD_PALLETTE_TFT_DC_MASK (0xFFFF << LCD_PALLETTE_TFT_DC_BIT)
|
||||
#define LCD_PALLETTE_TFT_DC_N(N) (((N)<< LCD_PALLETTE_TFT_DC_BIT) & LCD_PALLETTE_TFT_DC_MASK)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
/* List of panels known to work with the AU1100 LCD controller.
|
||||
* To add a new panel, enter the same specifications as the
|
||||
* Generic_TFT one, and MAKE SURE that it doesn't conflicts
|
||||
* with the controller restrictions. Restrictions are:
|
||||
*
|
||||
* STN color panels: max_bpp <= 12
|
||||
* STN mono panels: max_bpp <= 4
|
||||
* TFT panels: max_bpp <= 16
|
||||
* max_xres <= 800
|
||||
* max_yres <= 600
|
||||
*/
|
||||
static struct au1100fb_panel known_lcd_panels[] =
|
||||
{
|
||||
/* 800x600x16bpp CRT */
|
||||
[0] = {
|
||||
.name = "CRT_800x600_16",
|
||||
.xres = 800,
|
||||
.yres = 600,
|
||||
.bpp = 16,
|
||||
.control_base = 0x0004886A |
|
||||
LCD_CONTROL_DEFAULT_PO | LCD_CONTROL_DEFAULT_SBPPF |
|
||||
LCD_CONTROL_BPP_16,
|
||||
.clkcontrol_base = 0x00020000,
|
||||
.horztiming = 0x005aff1f,
|
||||
.verttiming = 0x16000e57,
|
||||
},
|
||||
/* just the standard LCD */
|
||||
[1] = {
|
||||
.name = "WWPC LCD",
|
||||
.xres = 240,
|
||||
.yres = 320,
|
||||
.bpp = 16,
|
||||
.control_base = 0x0006806A,
|
||||
.horztiming = 0x0A1010EF,
|
||||
.verttiming = 0x0301013F,
|
||||
.clkcontrol_base = 0x00018001,
|
||||
},
|
||||
/* Sharp 320x240 TFT panel */
|
||||
[2] = {
|
||||
.name = "Sharp_LQ038Q5DR01",
|
||||
.xres = 320,
|
||||
.yres = 240,
|
||||
.bpp = 16,
|
||||
.control_base =
|
||||
( LCD_CONTROL_SBPPF_565
|
||||
/*LCD_CONTROL_WP*/
|
||||
/*LCD_CONTROL_WD*/
|
||||
| LCD_CONTROL_C
|
||||
| LCD_CONTROL_SM_0
|
||||
/*LCD_CONTROL_DB*/
|
||||
/*LCD_CONTROL_CCO*/
|
||||
/*LCD_CONTROL_DP*/
|
||||
| LCD_DEFAULT_PIX_FORMAT
|
||||
/*LCD_CONTROL_MPI*/
|
||||
| LCD_CONTROL_DEFAULT_PO
|
||||
| LCD_CONTROL_PT
|
||||
| LCD_CONTROL_PC
|
||||
| LCD_CONTROL_BPP_16 ),
|
||||
|
||||
/* mode_horztiming */
|
||||
.horztiming =
|
||||
( LCD_HORZTIMING_HN2_N(8)
|
||||
| LCD_HORZTIMING_HN1_N(60)
|
||||
| LCD_HORZTIMING_HPW_N(12)
|
||||
| LCD_HORZTIMING_PPL_N(320) ),
|
||||
|
||||
/* mode_verttiming */
|
||||
.verttiming =
|
||||
( LCD_VERTTIMING_VN2_N(5)
|
||||
| LCD_VERTTIMING_VN1_N(17)
|
||||
| LCD_VERTTIMING_VPW_N(1)
|
||||
| LCD_VERTTIMING_LPP_N(240) ),
|
||||
|
||||
/* mode_clkcontrol */
|
||||
( 0
|
||||
/*LCD_CLKCONTROL_IB*/
|
||||
/*LCD_CLKCONTROL_IC*/
|
||||
/*LCD_CLKCONTROL_IH*/
|
||||
/*LCD_CLKCONTROL_IV*/
|
||||
| LCD_CLKCONTROL_PCD_N(1) ),
|
||||
|
||||
/* mode_pwmdiv */
|
||||
0,
|
||||
|
||||
/* mode_pwmhi */
|
||||
0,
|
||||
|
||||
/* mode_toyclksrc */
|
||||
((1<<7) | (1<<6) | (1<<5)),
|
||||
|
||||
/* mode_backlight */
|
||||
6
|
||||
.clkcontrol_base = LCD_CLKCONTROL_PCD_N(1),
|
||||
},
|
||||
|
||||
{ /* 1: Pb1100 LCDC 640x480 TFT panel */
|
||||
640, /* xres */
|
||||
480, /* yres */
|
||||
16, /* bpp */
|
||||
|
||||
"Generic_640x480_16",
|
||||
|
||||
/* mode_control */
|
||||
0x004806a | LCD_DEFAULT_PIX_FORMAT,
|
||||
|
||||
/* mode_horztiming */
|
||||
0x3434d67f,
|
||||
|
||||
/* mode_verttiming */
|
||||
0x0e0e39df,
|
||||
|
||||
/* mode_clkcontrol */
|
||||
( 0
|
||||
/*LCD_CLKCONTROL_IB*/
|
||||
/*LCD_CLKCONTROL_IC*/
|
||||
/*LCD_CLKCONTROL_IH*/
|
||||
/*LCD_CLKCONTROL_IV*/
|
||||
| LCD_CLKCONTROL_PCD_N(1) ),
|
||||
|
||||
/* mode_pwmdiv */
|
||||
0,
|
||||
|
||||
/* mode_pwmhi */
|
||||
0,
|
||||
|
||||
/* mode_toyclksrc */
|
||||
((1<<7) | (1<<6) | (0<<5)),
|
||||
|
||||
/* mode_backlight */
|
||||
7
|
||||
/* Hitachi SP14Q005 and possibly others */
|
||||
[3] = {
|
||||
.name = "Hitachi_SP14Qxxx",
|
||||
.xres = 320,
|
||||
.yres = 240,
|
||||
.bpp = 4,
|
||||
.control_base =
|
||||
( LCD_CONTROL_C
|
||||
| LCD_CONTROL_BPP_4 ),
|
||||
.horztiming =
|
||||
( LCD_HORZTIMING_HN2_N(1)
|
||||
| LCD_HORZTIMING_HN1_N(1)
|
||||
| LCD_HORZTIMING_HPW_N(1)
|
||||
| LCD_HORZTIMING_PPL_N(320) ),
|
||||
.verttiming =
|
||||
( LCD_VERTTIMING_VN2_N(1)
|
||||
| LCD_VERTTIMING_VN1_N(1)
|
||||
| LCD_VERTTIMING_VPW_N(1)
|
||||
| LCD_VERTTIMING_LPP_N(240) ),
|
||||
.clkcontrol_base = LCD_CLKCONTROL_PCD_N(4),
|
||||
},
|
||||
|
||||
{ /* 2: Pb1100 LCDB 640x480 PrimeView TFT panel */
|
||||
640, /* xres */
|
||||
480, /* yres */
|
||||
16, /* bpp */
|
||||
|
||||
"PrimeView_640x480_16",
|
||||
|
||||
/* mode_control */
|
||||
0x0004886a | LCD_DEFAULT_PIX_FORMAT,
|
||||
|
||||
/* mode_horztiming */
|
||||
0x0e4bfe7f,
|
||||
|
||||
/* mode_verttiming */
|
||||
0x210805df,
|
||||
|
||||
/* mode_clkcontrol */
|
||||
0x00038001,
|
||||
|
||||
/* mode_pwmdiv */
|
||||
0,
|
||||
|
||||
/* mode_pwmhi */
|
||||
0,
|
||||
|
||||
/* mode_toyclksrc */
|
||||
((1<<7) | (1<<6) | (0<<5)),
|
||||
|
||||
/* mode_backlight */
|
||||
7
|
||||
/* Generic 640x480 TFT panel */
|
||||
[4] = {
|
||||
.name = "TFT_640x480_16",
|
||||
.xres = 640,
|
||||
.yres = 480,
|
||||
.bpp = 16,
|
||||
.control_base = 0x004806a | LCD_CONTROL_DEFAULT_PO,
|
||||
.horztiming = 0x3434d67f,
|
||||
.verttiming = 0x0e0e39df,
|
||||
.clkcontrol_base = LCD_CLKCONTROL_PCD_N(1),
|
||||
},
|
||||
|
||||
{ /* 3: Pb1100 800x600x16bpp NEON CRT */
|
||||
800, /* xres */
|
||||
600, /* yres */
|
||||
16, /* bpp */
|
||||
|
||||
"NEON_800x600_16",
|
||||
|
||||
/* mode_control */
|
||||
0x0004886A | LCD_DEFAULT_PIX_FORMAT,
|
||||
|
||||
/* mode_horztiming */
|
||||
0x005AFF1F,
|
||||
|
||||
/* mode_verttiming */
|
||||
0x16000E57,
|
||||
|
||||
/* mode_clkcontrol */
|
||||
0x00020000,
|
||||
|
||||
/* mode_pwmdiv */
|
||||
0,
|
||||
|
||||
/* mode_pwmhi */
|
||||
0,
|
||||
|
||||
/* mode_toyclksrc */
|
||||
((1<<7) | (1<<6) | (0<<5)),
|
||||
|
||||
/* mode_backlight */
|
||||
7
|
||||
},
|
||||
|
||||
{ /* 4: Pb1100 640x480x16bpp NEON CRT */
|
||||
640, /* xres */
|
||||
480, /* yres */
|
||||
16, /* bpp */
|
||||
|
||||
"NEON_640x480_16",
|
||||
|
||||
/* mode_control */
|
||||
0x0004886A | LCD_DEFAULT_PIX_FORMAT,
|
||||
|
||||
/* mode_horztiming */
|
||||
0x0052E27F,
|
||||
|
||||
/* mode_verttiming */
|
||||
0x18000DDF,
|
||||
|
||||
/* mode_clkcontrol */
|
||||
0x00020000,
|
||||
|
||||
/* mode_pwmdiv */
|
||||
0,
|
||||
|
||||
/* mode_pwmhi */
|
||||
0,
|
||||
|
||||
/* mode_toyclksrc */
|
||||
((1<<7) | (1<<6) | (0<<5)),
|
||||
|
||||
/* mode_backlight */
|
||||
7
|
||||
/* Pb1100 LCDB 640x480 PrimeView TFT panel */
|
||||
[5] = {
|
||||
.name = "PrimeView_640x480_16",
|
||||
.xres = 640,
|
||||
.yres = 480,
|
||||
.bpp = 16,
|
||||
.control_base = 0x0004886a | LCD_CONTROL_DEFAULT_PO,
|
||||
.horztiming = 0x0e4bfe7f,
|
||||
.verttiming = 0x210805df,
|
||||
.clkcontrol_base = 0x00038001,
|
||||
},
|
||||
};
|
||||
|
||||
struct au1100fb_drv_info {
|
||||
int panel_idx;
|
||||
char *opt_mode;
|
||||
};
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
/* Inline helpers */
|
||||
|
||||
#define panel_is_dual(panel) (panel->control_base & LCD_CONTROL_DP)
|
||||
#define panel_is_active(panel)(panel->control_base & LCD_CONTROL_PT)
|
||||
#define panel_is_color(panel) (panel->control_base & LCD_CONTROL_PC)
|
||||
#define panel_swap_rgb(panel) (panel->control_base & LCD_CONTROL_CCO)
|
||||
|
||||
#endif /* _AU1100LCD_H */
|
||||
|
|
|
|||
|
|
@ -1647,6 +1647,12 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
|
|||
#define SYS_CS_MI2_MASK (0x7<<SYS_CS_MI2_BIT)
|
||||
#define SYS_CS_DI2 (1<<16)
|
||||
#define SYS_CS_CI2 (1<<15)
|
||||
#ifdef CONFIG_SOC_AU1100
|
||||
#define SYS_CS_ML_BIT 7
|
||||
#define SYS_CS_ML_MASK (0x7<<SYS_CS_ML_BIT)
|
||||
#define SYS_CS_DL (1<<6)
|
||||
#define SYS_CS_CL (1<<5)
|
||||
#else
|
||||
#define SYS_CS_MUH_BIT 12
|
||||
#define SYS_CS_MUH_MASK (0x7<<SYS_CS_MUH_BIT)
|
||||
#define SYS_CS_DUH (1<<11)
|
||||
|
|
@ -1655,6 +1661,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
|
|||
#define SYS_CS_MUD_MASK (0x7<<SYS_CS_MUD_BIT)
|
||||
#define SYS_CS_DUD (1<<6)
|
||||
#define SYS_CS_CUD (1<<5)
|
||||
#endif
|
||||
#define SYS_CS_MIR_BIT 2
|
||||
#define SYS_CS_MIR_MASK (0x7<<SYS_CS_MIR_BIT)
|
||||
#define SYS_CS_DIR (1<<1)
|
||||
|
|
|
|||
Loading…
Reference in a new issue