intelfb: fixup p calculation
This fixes up the p calculation of p1 and p2 for the i9xx chipsets. This seems to work a lot better for lower pixel clocks.. Signed-off-by: Dave Airlie <airlied@linux.ie>
This commit is contained in:
Dave Airlie
parent
46f60b8e67
commit
3aff13cfb8
4 changed files with 137 additions and 84 deletions
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@ -286,7 +286,7 @@ struct intelfb_info {
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int pll_index;
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};
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#define IS_I9xx(dinfo) (((dinfo)->chipset == INTEL_915G)||(dinfo->chipset == INTEL_915GM)||((dinfo)->chipset == INTEL_945G)||(dinfo->chipset==INTEL_945GM))
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#define IS_I9XX(dinfo) (((dinfo)->chipset == INTEL_915G)||(dinfo->chipset == INTEL_915GM)||((dinfo)->chipset == INTEL_945G)||(dinfo->chipset==INTEL_945GM))
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/*** function prototypes ***/
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@ -1480,7 +1480,7 @@ intelfb_cursor(struct fb_info *info, struct fb_cursor *cursor)
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intelfbhw_cursor_hide(dinfo);
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/* If XFree killed the cursor - restore it */
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physical = (dinfo->mobile || IS_I9xx(dinfo)) ? dinfo->cursor.physical :
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physical = (dinfo->mobile || IS_I9XX(dinfo)) ? dinfo->cursor.physical :
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(dinfo->cursor.offset << 12);
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if (INREG(CURSOR_A_BASEADDR) != physical) {
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@ -47,8 +47,8 @@ struct pll_min_max {
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int min_n, max_n;
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int min_p, max_p;
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int min_p1, max_p1;
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int min_vco_freq, max_vco_freq;
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int p_transition_clock;
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int min_vco, max_vco;
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int p_transition_clk, ref_clk;
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int p_inc_lo, p_inc_hi;
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};
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@ -57,8 +57,8 @@ struct pll_min_max {
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#define PLLS_MAX 2
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static struct pll_min_max plls[PLLS_MAX] = {
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{ 108, 140, 18, 26, 6, 16, 3, 16, 4, 128, 0, 31, 930000, 1400000, 165000, 4, 22 }, //I8xx
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{ 75, 120, 10, 20, 5, 9, 4, 7, 5, 80, 1, 8, 930000, 2800000, 200000, 10, 5 } //I9xx
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{ 108, 140, 18, 26, 6, 16, 3, 16, 4, 128, 0, 31, 930000, 1400000, 165000, 48000, 4, 22 }, //I8xx
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{ 75, 120, 10, 20, 5, 9, 4, 7, 5, 80, 1, 8, 930000, 2800000, 200000, 96000, 10, 5 } //I9xx
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};
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int
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@ -570,21 +570,26 @@ static int calc_vclock3(int index, int m, int n, int p)
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{
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if (p == 0 || n == 0)
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return 0;
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return PLL_REFCLK * m / n / p;
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return plls[index].ref_clk * m / n / p;
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}
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static int calc_vclock(int index, int m1, int m2, int n, int p1, int p2)
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static int calc_vclock(int index, int m1, int m2, int n, int p1, int p2, int lvds)
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{
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int p2_val;
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switch(index)
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{
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case PLLS_I9xx:
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if (p1 == 0)
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return 0;
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return ((PLL_REFCLK * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) /
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((p1)) * (p2 ? 10 : 5)));
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if (lvds)
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p2_val = p2 ? 7 : 14;
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else
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p2_val = p2 ? 5 : 10;
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return ((plls[index].ref_clk * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) /
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((p1)) * (p2_val)));
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case PLLS_I8xx:
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default:
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return ((PLL_REFCLK * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) /
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return ((plls[index].ref_clk * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) /
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((p1+2) * (1 << (p2 + 1)))));
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}
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}
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@ -596,7 +601,7 @@ intelfbhw_print_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw)
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int i, m1, m2, n, p1, p2;
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int index = dinfo->pll_index;
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DBG_MSG("intelfbhw_print_hw_state\n");
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if (!hw || !dinfo)
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return;
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/* Read in as much of the HW state as possible. */
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@ -611,12 +616,14 @@ intelfbhw_print_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw)
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p1 = 0;
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else
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p1 = (hw->vga_pd >> VGAPD_0_P1_SHIFT) & DPLL_P1_MASK;
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p2 = (hw->vga_pd >> VGAPD_0_P2_SHIFT) & DPLL_P2_MASK;
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printk(" VGA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
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m1, m2, n, p1, p2);
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printk(" VGA0: clock is %d\n",
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calc_vclock(index, m1, m2, n, p1, p2));
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calc_vclock(index, m1, m2, n, p1, p2, 0));
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n = (hw->vga1_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
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m1 = (hw->vga1_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
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m2 = (hw->vga1_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
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@ -627,39 +634,96 @@ intelfbhw_print_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw)
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p2 = (hw->vga_pd >> VGAPD_1_P2_SHIFT) & DPLL_P2_MASK;
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printk(" VGA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
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m1, m2, n, p1, p2);
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printk(" VGA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2));
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printk(" VGA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2, 0));
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printk(" DPLL_A: 0x%08x\n", hw->dpll_a);
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printk(" DPLL_B: 0x%08x\n", hw->dpll_b);
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printk(" FPA0: 0x%08x\n", hw->fpa0);
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printk(" FPA1: 0x%08x\n", hw->fpa1);
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printk(" FPB0: 0x%08x\n", hw->fpb0);
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printk(" FPB1: 0x%08x\n", hw->fpb1);
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n = (hw->fpa0 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
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m1 = (hw->fpa0 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
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m2 = (hw->fpa0 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
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if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
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p1 = 0;
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else
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p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
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p2 = (hw->dpll_a >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
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if (IS_I9XX(dinfo)) {
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int tmpp1;
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if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
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p1 = 0;
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else
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p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & 0xff;
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tmpp1 = p1;
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switch (tmpp1)
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{
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case 0x1: p1 = 1; break;
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case 0x2: p1 = 2; break;
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case 0x4: p1 = 3; break;
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case 0x8: p1 = 4; break;
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case 0x10: p1 = 5; break;
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case 0x20: p1 = 6; break;
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case 0x40: p1 = 7; break;
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case 0x80: p1 = 8; break;
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default: break;
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}
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p2 = (hw->dpll_a >> DPLL_I9XX_P2_SHIFT) & DPLL_P2_MASK;
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} else {
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if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
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p1 = 0;
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else
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p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
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p2 = (hw->dpll_a >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
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}
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printk(" PLLA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
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m1, m2, n, p1, p2);
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printk(" PLLA0: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2));
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printk(" PLLA0: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2, 0));
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n = (hw->fpa1 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
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m1 = (hw->fpa1 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
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m2 = (hw->fpa1 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
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if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
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p1 = 0;
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else
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p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
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p2 = (hw->dpll_a >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
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if (IS_I9XX(dinfo)) {
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int tmpp1;
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if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
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p1 = 0;
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else
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p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & 0xff;
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tmpp1 = p1;
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switch (tmpp1)
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{
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case 0x1: p1 = 1; break;
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case 0x2: p1 = 2; break;
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case 0x4: p1 = 3; break;
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case 0x8: p1 = 4; break;
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case 0x10: p1 = 5; break;
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case 0x20: p1 = 6; break;
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case 0x40: p1 = 7; break;
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case 0x80: p1 = 8; break;
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default: break;
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}
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p2 = (hw->dpll_a >> DPLL_I9XX_P2_SHIFT) & DPLL_P2_MASK;
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} else {
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if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
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p1 = 0;
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else
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p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
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p2 = (hw->dpll_a >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
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}
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printk(" PLLA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
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m1, m2, n, p1, p2);
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printk(" PLLA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2));
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printk(" PLLA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2, 0));
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#if 0
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printk(" PALETTE_A:\n");
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for (i = 0; i < PALETTE_8_ENTRIES)
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@ -767,7 +831,7 @@ splitm(int index, unsigned int m, unsigned int *retm1, unsigned int *retm2)
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/* no point optimising too much - brute force m */
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for (m1 = plls[index].min_m1; m1 < plls[index].max_m1+1; m1++) {
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for (m2 = plls[index].min_m2; m2 < plls[index].max_m2+1; m2++) {
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testm = ( 5 * ( m1 + 2 )) + (m2 + 2);
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testm = (5 * (m1 + 2)) + (m2 + 2);
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if (testm == m) {
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*retm1 = (unsigned int)m1;
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*retm2 = (unsigned int)m2;
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@ -785,21 +849,11 @@ splitp(int index, unsigned int p, unsigned int *retp1, unsigned int *retp2)
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int p1, p2;
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if (index == PLLS_I9xx) {
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switch (p) {
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case 10:
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p1 = 2;
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p2 = 0;
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break;
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case 20:
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p1 = 1;
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p2 = 0;
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break;
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default:
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p1 = (p / 10) + 1;
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p2 = 0;
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break;
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}
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p2 = 0; // for now
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p1 = p / (p2 ? 5 : 10);
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*retp1 = (unsigned int)p1;
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*retp2 = (unsigned int)p2;
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return 0;
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@ -844,13 +898,13 @@ calc_pll_params(int index, int clock, u32 *retm1, u32 *retm2, u32 *retn, u32 *re
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DBG_MSG("Clock is %d\n", clock);
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div_max = plls[index].max_vco_freq / clock;
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div_max = plls[index].max_vco / clock;
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if (index == PLLS_I9xx)
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div_min = 5;
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else
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div_min = ROUND_UP_TO(plls[index].min_vco_freq, clock) / clock;
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div_min = ROUND_UP_TO(plls[index].min_vco, clock) / clock;
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if (clock <= plls[index].p_transition_clock)
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if (clock <= plls[index].p_transition_clk)
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p_inc = plls[index].p_inc_lo;
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else
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p_inc = plls[index].p_inc_hi;
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@ -861,15 +915,6 @@ calc_pll_params(int index, int clock, u32 *retm1, u32 *retm2, u32 *retn, u32 *re
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if (p_max > plls[index].max_p)
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p_max = plls[index].max_p;
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if (clock < PLL_REFCLK && index == PLLS_I9xx) {
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p_min = 10;
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p_max = 20;
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/* this makes 640x480 work it really shouldn't
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- SOMEONE WITHOUT DOCS WOZ HERE */
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if (clock < 30000)
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clock *= 4;
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}
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DBG_MSG("p range is %d-%d (%d)\n", p_min, p_max, p_inc);
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p = p_min;
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@ -883,7 +928,7 @@ calc_pll_params(int index, int clock, u32 *retm1, u32 *retm2, u32 *retn, u32 *re
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f_vco = clock * p;
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do {
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m = ROUND_UP_TO(f_vco * n, PLL_REFCLK) / PLL_REFCLK;
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m = ROUND_UP_TO(f_vco * n, plls[index].ref_clk) / plls[index].ref_clk;
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if (m < plls[index].min_m)
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m = plls[index].min_m + 1;
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if (m > plls[index].max_m)
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@ -899,7 +944,7 @@ calc_pll_params(int index, int clock, u32 *retm1, u32 *retm2, u32 *retn, u32 *re
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f_err = clock - f_out;
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else/* slightly bias the error for bigger clocks */
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f_err = f_out - clock + 1;
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if (f_err < err_best) {
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m_best = m;
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n_best = n;
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@ -928,14 +973,14 @@ calc_pll_params(int index, int clock, u32 *retm1, u32 *retm2, u32 *retn, u32 *re
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"f: %d (%d), VCO: %d\n",
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m, m1, m2, n, n1, p, p1, p2,
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calc_vclock3(index, m, n, p),
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calc_vclock(index, m1, m2, n1, p1, p2),
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calc_vclock(index, m1, m2, n1, p1, p2, 0),
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calc_vclock3(index, m, n, p) * p);
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*retm1 = m1;
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*retm2 = m2;
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*retn = n1;
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*retp1 = p1;
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*retp2 = p2;
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*retclock = calc_vclock(index, m1, m2, n1, p1, p2);
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*retclock = calc_vclock(index, m1, m2, n1, p1, p2, 0);
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return 0;
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}
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@ -1032,7 +1077,7 @@ intelfbhw_mode_to_hw(struct intelfb_info *dinfo, struct intelfb_hwstate *hw,
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/* Desired clock in kHz */
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clock_target = 1000000000 / var->pixclock;
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if (calc_pll_params(dinfo->pll_index, clock_target, &m1, &m2,
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if (calc_pll_params(dinfo->pll_index, clock_target, &m1, &m2,
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&n, &p1, &p2, &clock)) {
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WRN_MSG("calc_pll_params failed\n");
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return 1;
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@ -1053,7 +1098,14 @@ intelfbhw_mode_to_hw(struct intelfb_info *dinfo, struct intelfb_hwstate *hw,
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*dpll &= ~DPLL_P1_FORCE_DIV2;
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*dpll &= ~((DPLL_P2_MASK << DPLL_P2_SHIFT) |
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(DPLL_P1_MASK << DPLL_P1_SHIFT));
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*dpll |= (p2 << DPLL_P2_SHIFT) | (p1 << DPLL_P1_SHIFT);
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if (IS_I9XX(dinfo)) {
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*dpll |= (p2 << DPLL_I9XX_P2_SHIFT);
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*dpll |= (1 << (p1 - 1)) << DPLL_P1_SHIFT;
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} else {
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*dpll |= (p2 << DPLL_P2_SHIFT) | (p1 << DPLL_P1_SHIFT);
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}
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*fp0 = (n << FP_N_DIVISOR_SHIFT) |
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(m1 << FP_M1_DIVISOR_SHIFT) |
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(m2 << FP_M2_DIVISOR_SHIFT);
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@ -1264,19 +1316,19 @@ intelfbhw_program_mode(struct intelfb_info *dinfo,
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tmp = INREG(pipe_conf_reg);
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tmp &= ~PIPECONF_ENABLE;
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OUTREG(pipe_conf_reg, tmp);
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count = 0;
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do {
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tmp_val[count%3] = INREG(0x70000);
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if ((tmp_val[0] == tmp_val[1]) && (tmp_val[1]==tmp_val[2]))
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break;
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count++;
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udelay(1);
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if (count % 200 == 0) {
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tmp = INREG(pipe_conf_reg);
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tmp &= ~PIPECONF_ENABLE;
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OUTREG(pipe_conf_reg, tmp);
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}
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tmp_val[count%3] = INREG(0x70000);
|
||||
if ((tmp_val[0] == tmp_val[1]) && (tmp_val[1]==tmp_val[2]))
|
||||
break;
|
||||
count++;
|
||||
udelay(1);
|
||||
if (count % 200 == 0) {
|
||||
tmp = INREG(pipe_conf_reg);
|
||||
tmp &= ~PIPECONF_ENABLE;
|
||||
OUTREG(pipe_conf_reg, tmp);
|
||||
}
|
||||
} while(count < 2000);
|
||||
|
||||
OUTREG(ADPA, INREG(ADPA) & ~ADPA_DAC_ENABLE);
|
||||
|
|
@ -1289,7 +1341,7 @@ intelfbhw_program_mode(struct intelfb_info *dinfo,
|
|||
tmp &= ~DISPPLANE_PLANE_ENABLE;
|
||||
OUTREG(DSPBCNTR, tmp);
|
||||
|
||||
/* Wait for vblank. For now, just wait for a 50Hz cycle (20ms)) */
|
||||
/* Wait for vblank. For now, just wait for a 50Hz cycle (20ms)) */
|
||||
mdelay(20);
|
||||
|
||||
/* Disable Sync */
|
||||
|
|
@ -1359,7 +1411,7 @@ intelfbhw_program_mode(struct intelfb_info *dinfo,
|
|||
OUTREG(DSPACNTR,
|
||||
hw->disp_a_ctrl|DISPPLANE_PLANE_ENABLE);
|
||||
mdelay(1);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
OUTREG(DSPACNTR, hw->disp_a_ctrl & ~DISPPLANE_PLANE_ENABLE);
|
||||
|
|
@ -1744,7 +1796,7 @@ intelfbhw_cursor_init(struct intelfb_info *dinfo)
|
|||
DBG_MSG("intelfbhw_cursor_init\n");
|
||||
#endif
|
||||
|
||||
if (dinfo->mobile || IS_I9xx(dinfo)) {
|
||||
if (dinfo->mobile || IS_I9XX(dinfo)) {
|
||||
if (!dinfo->cursor.physical)
|
||||
return;
|
||||
tmp = INREG(CURSOR_A_CONTROL);
|
||||
|
|
@ -1777,7 +1829,7 @@ intelfbhw_cursor_hide(struct intelfb_info *dinfo)
|
|||
#endif
|
||||
|
||||
dinfo->cursor_on = 0;
|
||||
if (dinfo->mobile || IS_I9xx(dinfo)) {
|
||||
if (dinfo->mobile || IS_I9XX(dinfo)) {
|
||||
if (!dinfo->cursor.physical)
|
||||
return;
|
||||
tmp = INREG(CURSOR_A_CONTROL);
|
||||
|
|
@ -1807,7 +1859,7 @@ intelfbhw_cursor_show(struct intelfb_info *dinfo)
|
|||
if (dinfo->cursor_blanked)
|
||||
return;
|
||||
|
||||
if (dinfo->mobile || IS_I9xx(dinfo)) {
|
||||
if (dinfo->mobile || IS_I9XX(dinfo)) {
|
||||
if (!dinfo->cursor.physical)
|
||||
return;
|
||||
tmp = INREG(CURSOR_A_CONTROL);
|
||||
|
|
@ -1833,8 +1885,8 @@ intelfbhw_cursor_setpos(struct intelfb_info *dinfo, int x, int y)
|
|||
#endif
|
||||
|
||||
/*
|
||||
* Sets the position. The coordinates are assumed to already
|
||||
* have any offset adjusted. Assume that the cursor is never
|
||||
* Sets the position. The coordinates are assumed to already
|
||||
* have any offset adjusted. Assume that the cursor is never
|
||||
* completely off-screen, and that x, y are always >= 0.
|
||||
*/
|
||||
|
||||
|
|
@ -1842,7 +1894,7 @@ intelfbhw_cursor_setpos(struct intelfb_info *dinfo, int x, int y)
|
|||
((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
|
||||
OUTREG(CURSOR_A_POSITION, tmp);
|
||||
|
||||
if (IS_I9xx(dinfo)) {
|
||||
if (IS_I9XX(dinfo)) {
|
||||
OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -133,6 +133,7 @@
|
|||
#define DPLL_VGA_MODE_DISABLE (1 << 28)
|
||||
#define DPLL_P2_MASK 1
|
||||
#define DPLL_P2_SHIFT 23
|
||||
#define DPLL_I9XX_P2_SHIFT 24
|
||||
#define DPLL_P1_FORCE_DIV2 (1 << 21)
|
||||
#define DPLL_P1_MASK 0x1f
|
||||
#define DPLL_P1_SHIFT 16
|
||||
|
|
|
|||
Loading…
Reference in a new issue