powerpc: GE Fanuc's FPGA based PIC controller on the SBC610
Support for the SBC610 VPX Single Board Computer from GE Fanuc (PowerPC MPC8641D). A number of MPC8641D based route interrupts for on-board interrupts through a FPGA based interrupt controller, which is chained with the MPC8641D's mpic. This patch provides a basic driver to allow basic routing of interrupts to the mpic. Signed-off-by: Martyn Welch <martyn.welch@gefanuc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Martyn Welch
Kumar Gala
parent
92ae954046
commit
3a47024791
5 changed files with 327 additions and 6 deletions
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@ -67,6 +67,35 @@
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reg = <0x0 0x40000000>; // set by uboot
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};
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localbus@fef05000 {
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#address-cells = <2>;
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#size-cells = <1>;
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compatible = "fsl,mpc8641-localbus", "simple-bus";
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reg = <0xf8005000 0x1000>;
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interrupts = <19 2>;
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interrupt-parent = <&mpic>;
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ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
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1 0 0xe8000000 0x08000000 // Paged Flash 0
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2 0 0xe0000000 0x08000000 // Paged Flash 1
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3 0 0xfc100000 0x00020000 // NVRAM
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4 0 0xfc000000 0x00008000 // FPGA
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5 0 0xfc008000 0x00008000 // AFIX FPGA
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6 0 0xfd000000 0x00800000 // IO FPGA (8-bit)
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7 0 0xfd800000 0x00800000>; // IO FPGA (32-bit)
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gef_pic: pic@4,4000 {
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "gef,fpga-pic";
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reg = <0x4 0x4000 0x20>;
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interrupts = <0x8
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0x9>;
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interrupt-parent = <&mpic>;
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};
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};
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soc@fef00000 {
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#address-cells = <1>;
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#size-cells = <1>;
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@ -150,13 +179,13 @@
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reg = <0x24520 0x20>;
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phy0: ethernet-phy@0 {
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interrupt-parent = <&mpic>;
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interrupts = <0x0 0x1>;
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interrupt-parent = <&gef_pic>;
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interrupts = <0x9 0x4>;
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reg = <1>;
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};
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phy2: ethernet-phy@2 {
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interrupt-parent = <&mpic>;
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interrupts = <0x0 0x1>;
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interrupt-parent = <&gef_pic>;
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interrupts = <0x8 0x4>;
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reg = <3>;
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};
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};
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@ -7,4 +7,4 @@ obj-$(CONFIG_SMP) += mpc86xx_smp.o
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obj-$(CONFIG_MPC8641_HPCN) += mpc86xx_hpcn.o
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obj-$(CONFIG_SBC8641D) += sbc8641d.o
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obj-$(CONFIG_MPC8610_HPCD) += mpc8610_hpcd.o
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obj-$(CONFIG_GEF_SBC610) += gef_sbc610.o
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obj-$(CONFIG_GEF_SBC610) += gef_sbc610.o gef_pic.o
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258
arch/powerpc/platforms/86xx/gef_pic.c
Normal file
258
arch/powerpc/platforms/86xx/gef_pic.c
Normal file
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@ -0,0 +1,258 @@
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/*
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* Interrupt handling for GE Fanuc's FPGA based PIC
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*
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* Author: Martyn Welch <martyn.welch@gefanuc.com>
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*
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* 2008 (c) GE Fanuc Intelligent Platforms Embedded Systems, Inc.
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include <linux/stddef.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/spinlock.h>
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#include <asm/byteorder.h>
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#include <asm/io.h>
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#include <asm/prom.h>
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#include <asm/irq.h>
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#include "gef_pic.h"
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#define DEBUG
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#undef DEBUG
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#ifdef DEBUG
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#define DBG(fmt...) do { printk(KERN_DEBUG "gef_pic: " fmt); } while (0)
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#else
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#define DBG(fmt...) do { } while (0)
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#endif
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#define GEF_PIC_NUM_IRQS 32
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/* Interrupt Controller Interface Registers */
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#define GEF_PIC_INTR_STATUS 0x0000
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#define GEF_PIC_INTR_MASK(cpu) (0x0010 + (0x4 * cpu))
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#define GEF_PIC_CPU0_INTR_MASK GEF_PIC_INTR_MASK(0)
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#define GEF_PIC_CPU1_INTR_MASK GEF_PIC_INTR_MASK(1)
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#define GEF_PIC_MCP_MASK(cpu) (0x0018 + (0x4 * cpu))
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#define GEF_PIC_CPU0_MCP_MASK GEF_PIC_MCP_MASK(0)
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#define GEF_PIC_CPU1_MCP_MASK GEF_PIC_MCP_MASK(1)
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#define gef_irq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq)
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static DEFINE_SPINLOCK(gef_pic_lock);
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static void __iomem *gef_pic_irq_reg_base;
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static struct irq_host *gef_pic_irq_host;
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static int gef_pic_cascade_irq;
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/*
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* Interrupt Controller Handling
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*
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* The interrupt controller handles interrupts for most on board interrupts,
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* apart from PCI interrupts. For example on SBC610:
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*
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* 17:31 RO Reserved
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* 16 RO PCI Express Doorbell 3 Status
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* 15 RO PCI Express Doorbell 2 Status
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* 14 RO PCI Express Doorbell 1 Status
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* 13 RO PCI Express Doorbell 0 Status
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* 12 RO Real Time Clock Interrupt Status
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* 11 RO Temperature Interrupt Status
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* 10 RO Temperature Critical Interrupt Status
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* 9 RO Ethernet PHY1 Interrupt Status
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* 8 RO Ethernet PHY3 Interrupt Status
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* 7 RO PEX8548 Interrupt Status
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* 6 RO Reserved
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* 5 RO Watchdog 0 Interrupt Status
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* 4 RO Watchdog 1 Interrupt Status
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* 3 RO AXIS Message FIFO A Interrupt Status
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* 2 RO AXIS Message FIFO B Interrupt Status
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* 1 RO AXIS Message FIFO C Interrupt Status
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* 0 RO AXIS Message FIFO D Interrupt Status
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*
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* Interrupts can be forwarded to one of two output lines. Nothing
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* clever is done, so if the masks are incorrectly set, a single input
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* interrupt could generate interrupts on both output lines!
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*
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* The dual lines are there to allow the chained interrupts to be easily
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* passed into two different cores. We currently do not use this functionality
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* in this driver.
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*
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* Controller can also be configured to generate Machine checks (MCP), again on
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* two lines, to be attached to two different cores. It is suggested that these
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* should be masked out.
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*/
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void gef_pic_cascade(unsigned int irq, struct irq_desc *desc)
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{
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unsigned int cascade_irq;
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/*
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* See if we actually have an interrupt, call generic handling code if
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* we do.
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*/
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cascade_irq = gef_pic_get_irq();
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if (cascade_irq != NO_IRQ)
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generic_handle_irq(cascade_irq);
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desc->chip->eoi(irq);
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}
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static void gef_pic_mask(unsigned int virq)
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{
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unsigned long flags;
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unsigned int hwirq;
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u32 mask;
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hwirq = gef_irq_to_hw(virq);
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spin_lock_irqsave(&gef_pic_lock, flags);
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mask = in_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0));
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mask &= ~(1 << hwirq);
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out_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0), mask);
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spin_unlock_irqrestore(&gef_pic_lock, flags);
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}
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static void gef_pic_mask_ack(unsigned int virq)
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{
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/* Don't think we actually have to do anything to ack an interrupt,
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* we just need to clear down the devices interrupt and it will go away
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*/
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gef_pic_mask(virq);
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}
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static void gef_pic_unmask(unsigned int virq)
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{
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unsigned long flags;
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unsigned int hwirq;
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u32 mask;
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hwirq = gef_irq_to_hw(virq);
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spin_lock_irqsave(&gef_pic_lock, flags);
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mask = in_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0));
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mask |= (1 << hwirq);
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out_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0), mask);
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spin_unlock_irqrestore(&gef_pic_lock, flags);
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}
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static struct irq_chip gef_pic_chip = {
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.typename = "gefp",
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.mask = gef_pic_mask,
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.mask_ack = gef_pic_mask_ack,
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.unmask = gef_pic_unmask,
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};
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/* When an interrupt is being configured, this call allows some flexibilty
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* in deciding which irq_chip structure is used
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*/
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static int gef_pic_host_map(struct irq_host *h, unsigned int virq,
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irq_hw_number_t hwirq)
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{
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/* All interrupts are LEVEL sensitive */
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get_irq_desc(virq)->status |= IRQ_LEVEL;
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set_irq_chip_and_handler(virq, &gef_pic_chip, handle_level_irq);
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return 0;
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}
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static int gef_pic_host_xlate(struct irq_host *h, struct device_node *ct,
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u32 *intspec, unsigned int intsize,
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irq_hw_number_t *out_hwirq, unsigned int *out_flags)
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{
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*out_hwirq = intspec[0];
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if (intsize > 1)
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*out_flags = intspec[1];
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else
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*out_flags = IRQ_TYPE_LEVEL_HIGH;
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return 0;
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}
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static struct irq_host_ops gef_pic_host_ops = {
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.map = gef_pic_host_map,
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.xlate = gef_pic_host_xlate,
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};
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/*
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* Initialisation of PIC, this should be called in BSP
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*/
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void __init gef_pic_init(struct device_node *np)
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{
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unsigned long flags;
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/* Map the devices registers into memory */
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gef_pic_irq_reg_base = of_iomap(np, 0);
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spin_lock_irqsave(&gef_pic_lock, flags);
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/* Initialise everything as masked. */
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out_be32(gef_pic_irq_reg_base + GEF_PIC_CPU0_INTR_MASK, 0);
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out_be32(gef_pic_irq_reg_base + GEF_PIC_CPU1_INTR_MASK, 0);
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out_be32(gef_pic_irq_reg_base + GEF_PIC_CPU0_MCP_MASK, 0);
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out_be32(gef_pic_irq_reg_base + GEF_PIC_CPU1_MCP_MASK, 0);
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spin_unlock_irqrestore(&gef_pic_lock, flags);
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/* Map controller */
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gef_pic_cascade_irq = irq_of_parse_and_map(np, 0);
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if (gef_pic_cascade_irq == NO_IRQ) {
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printk(KERN_ERR "SBC610: failed to map cascade interrupt");
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return;
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}
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/* Setup an irq_host structure */
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gef_pic_irq_host = irq_alloc_host(np, IRQ_HOST_MAP_LINEAR,
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GEF_PIC_NUM_IRQS,
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&gef_pic_host_ops, NO_IRQ);
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if (gef_pic_irq_host == NULL)
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return;
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/* Chain with parent controller */
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set_irq_chained_handler(gef_pic_cascade_irq, gef_pic_cascade);
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}
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/*
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* This is called when we receive an interrupt with apparently comes from this
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* chip - check, returning the highest interrupt generated or return NO_IRQ
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*/
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unsigned int gef_pic_get_irq(void)
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{
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u32 cause, mask, active;
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unsigned int virq = NO_IRQ;
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int hwirq;
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cause = in_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_STATUS);
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mask = in_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0));
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active = cause & mask;
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if (active) {
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for (hwirq = GEF_PIC_NUM_IRQS - 1; hwirq > -1; hwirq--) {
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if (active & (0x1 << hwirq))
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break;
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}
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virq = irq_linear_revmap(gef_pic_irq_host,
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(irq_hw_number_t)hwirq);
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}
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return virq;
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}
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11
arch/powerpc/platforms/86xx/gef_pic.h
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11
arch/powerpc/platforms/86xx/gef_pic.h
Normal file
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@ -0,0 +1,11 @@
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#ifndef __GEF_PIC_H__
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#define __GEF_PIC_H__
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#include <linux/init.h>
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void gef_pic_cascade(unsigned int, struct irq_desc *);
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unsigned int gef_pic_get_irq(void);
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void gef_pic_init(struct device_node *);
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#endif /* __GEF_PIC_H__ */
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@ -39,6 +39,7 @@
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#include <sysdev/fsl_soc.h>
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#include "mpc86xx.h"
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#include "gef_pic.h"
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#undef DEBUG
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@ -48,6 +49,28 @@
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#define DBG (fmt...) do { } while (0)
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#endif
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void __iomem *sbc610_regs;
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static void __init gef_sbc610_init_irq(void)
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{
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struct device_node *cascade_node = NULL;
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mpc86xx_init_irq();
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/*
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* There is a simple interrupt handler in the main FPGA, this needs
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* to be cascaded into the MPIC
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*/
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cascade_node = of_find_compatible_node(NULL, NULL, "gef,fpga-pic");
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if (!cascade_node) {
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printk(KERN_WARNING "SBC610: No FPGA PIC\n");
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return;
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}
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gef_pic_init(cascade_node);
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of_node_put(cascade_node);
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}
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static void __init gef_sbc610_setup_arch(void)
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{
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#ifdef CONFIG_PCI
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@ -145,7 +168,7 @@ define_machine(gef_sbc610) {
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.name = "GE Fanuc SBC610",
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.probe = gef_sbc610_probe,
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.setup_arch = gef_sbc610_setup_arch,
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.init_IRQ = mpc86xx_init_irq,
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.init_IRQ = gef_sbc610_init_irq,
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.show_cpuinfo = gef_sbc610_show_cpuinfo,
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.get_irq = mpic_get_irq,
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.restart = fsl_rstcr_restart,
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