OMAP3: PM: Fix for MPU power domain MEM BANK position
MPU power domain bank 0 bits are displayed in position of bank 1 in PWRSTS and PREPWRSTS registers. So read them from correct position Signed-off-by: Thara Gopinath <thara@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
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3 changed files with 11 additions and 1 deletions
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@ -983,6 +983,9 @@ int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
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if (pwrdm->banks < (bank + 1))
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return -EEXIST;
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if (pwrdm->flags & PWRDM_HAS_MPU_QUIRK)
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bank = 1;
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/*
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* The register bit names below may not correspond to the
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* actual names of the bits in each powerdomain's register,
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@ -1030,6 +1033,9 @@ int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
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if (pwrdm->banks < (bank + 1))
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return -EEXIST;
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if (pwrdm->flags & PWRDM_HAS_MPU_QUIRK)
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bank = 1;
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/*
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* The register bit names below may not correspond to the
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* actual names of the bits in each powerdomain's register,
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@ -190,6 +190,7 @@ static struct powerdomain mpu_34xx_pwrdm = {
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.wkdep_srcs = mpu_34xx_wkdeps,
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.pwrsts = PWRSTS_OFF_RET_ON,
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.pwrsts_logic_ret = PWRSTS_OFF_RET,
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.flags = PWRDM_HAS_MPU_QUIRK,
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.banks = 1,
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.pwrsts_mem_ret = {
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[0] = PWRSTS_OFF_RET,
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@ -42,7 +42,10 @@
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/* Powerdomain flags */
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#define PWRDM_HAS_HDWR_SAR (1 << 0) /* hardware save-and-restore support */
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#define PWRDM_HAS_MPU_QUIRK (1 << 1) /* MPU pwr domain has MEM bank 0 bits
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* in MEM bank 1 position. This is
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* true for OMAP3430
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*/
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/*
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* Number of memory banks that are power-controllable. On OMAP3430, the
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