crypto: talitos - chain in buffered data for ahash on SEC1
SEC1 doesn't support S/G in descriptors so for hash operations, the CPU has to build a buffer containing the buffered block and the incoming data. This generates a lot of memory copies which represents more than 50% of CPU time of a md5sum operation as shown below with a 'perf record'. |--86.24%-- kcapi_md_digest | | | |--86.18%-- _kcapi_common_vmsplice_chunk_fd | | | | | |--83.68%-- splice | | | | | | | |--83.59%-- ret_from_syscall | | | | | | | | | |--83.52%-- sys_splice | | | | | | | | | | | |--83.49%-- splice_from_pipe | | | | | | | | | | | | | |--83.04%-- __splice_from_pipe | | | | | | | | | | | | | | | |--80.67%-- pipe_to_sendpage | | | | | | | | | | | | | | | | | |--78.25%-- hash_sendpage | | | | | | | | | | | | | | | | | | | |--60.08%-- ahash_process_req | | | | | | | | | | | | | | | | | | | | | |--56.36%-- sg_copy_buffer | | | | | | | | | | | | | | | | | | | | | | | |--55.29%-- memcpy | | | | | | | | | | | | However, unlike SEC2+, SEC1 offers the possibility to chain descriptors. It is therefore possible to build a first descriptor pointing to the buffered data and a second descriptor pointing to the incoming data, hence avoiding the memory copy to a single buffer. With this patch, the time necessary for a md5sum on a 90Mbytes file is approximately 3 seconds. Without the patch it takes 6 seconds. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
LEROY Christophe
Herbert Xu
parent
49f9783b0c
commit
37b5e8897e
2 changed files with 127 additions and 13 deletions
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@ -160,6 +160,10 @@ static int reset_channel(struct device *dev, int ch)
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/* set 36-bit addressing, done writeback enable and done IRQ enable */
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setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, TALITOS_CCCR_LO_EAE |
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TALITOS_CCCR_LO_CDWE | TALITOS_CCCR_LO_CDIE);
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/* enable chaining descriptors */
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if (is_sec1)
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setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO,
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TALITOS_CCCR_LO_NE);
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/* and ICCR writeback, if available */
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if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
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@ -333,7 +337,12 @@ static void flush_channel(struct device *dev, int ch, int error, int reset_ch)
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/* descriptors with their done bits set don't get the error */
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rmb();
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hdr = is_sec1 ? request->desc->hdr1 : request->desc->hdr;
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if (!is_sec1)
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hdr = request->desc->hdr;
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else if (request->desc->next_desc)
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hdr = (request->desc + 1)->hdr1;
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else
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hdr = request->desc->hdr1;
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if ((hdr & DESC_HDR_DONE) == DESC_HDR_DONE)
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status = 0;
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@ -454,7 +463,8 @@ static u32 current_desc_hdr(struct device *dev, int ch)
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tail = priv->chan[ch].tail;
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iter = tail;
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while (priv->chan[ch].fifo[iter].dma_desc != cur_desc) {
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while (priv->chan[ch].fifo[iter].dma_desc != cur_desc &&
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priv->chan[ch].fifo[iter].desc->next_desc != cur_desc) {
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iter = (iter + 1) & (priv->fifo_len - 1);
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if (iter == tail) {
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dev_err(dev, "couldn't locate current descriptor\n");
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@ -462,6 +472,9 @@ static u32 current_desc_hdr(struct device *dev, int ch)
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}
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}
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if (priv->chan[ch].fifo[iter].desc->next_desc == cur_desc)
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return (priv->chan[ch].fifo[iter].desc + 1)->hdr;
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return priv->chan[ch].fifo[iter].desc->hdr;
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}
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@ -819,6 +832,7 @@ struct talitos_ctx {
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unsigned int keylen;
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unsigned int enckeylen;
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unsigned int authkeylen;
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dma_addr_t dma_buf;
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dma_addr_t dma_hw_context;
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};
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@ -1380,6 +1394,10 @@ static struct talitos_edesc *talitos_edesc_alloc(struct device *dev,
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alloc_len += icv_stashing ? authsize : 0;
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}
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/* if its a ahash, add space for a second desc next to the first one */
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if (is_sec1 && !dst)
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alloc_len += sizeof(struct talitos_desc);
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edesc = kmalloc(alloc_len, GFP_DMA | flags);
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if (!edesc) {
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dev_err(dev, "could not allocate edescriptor\n");
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@ -1392,11 +1410,15 @@ static struct talitos_edesc *talitos_edesc_alloc(struct device *dev,
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edesc->dst_nents = dst_nents;
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edesc->iv_dma = iv_dma;
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edesc->dma_len = dma_len;
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if (dma_len)
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edesc->dma_link_tbl = dma_map_single(dev, &edesc->link_tbl[0],
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if (dma_len) {
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void *addr = &edesc->link_tbl[0];
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if (is_sec1 && !dst)
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addr += sizeof(struct talitos_desc);
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edesc->dma_link_tbl = dma_map_single(dev, addr,
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edesc->dma_len,
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DMA_BIDIRECTIONAL);
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}
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return edesc;
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error_sg:
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if (iv_dma)
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@ -1671,6 +1693,9 @@ static void common_nonsnoop_hash_unmap(struct device *dev,
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dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
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DMA_BIDIRECTIONAL);
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if (edesc->desc.next_desc)
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dma_unmap_single(dev, be32_to_cpu(edesc->desc.next_desc),
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TALITOS_DESC_SIZE, DMA_BIDIRECTIONAL);
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}
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static void ahash_done(struct device *dev,
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@ -1717,6 +1742,7 @@ static void talitos_handle_buggy_hash(struct talitos_ctx *ctx,
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static int common_nonsnoop_hash(struct talitos_edesc *edesc,
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struct ahash_request *areq, unsigned int length,
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unsigned int offset,
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void (*callback) (struct device *dev,
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struct talitos_desc *desc,
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void *context, int error))
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@ -1748,19 +1774,29 @@ static int common_nonsnoop_hash(struct talitos_edesc *edesc,
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to_talitos_ptr(&desc->ptr[2], ctx->dma_key, ctx->keylen,
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is_sec1);
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if (is_sec1 && req_ctx->nbuf)
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length -= req_ctx->nbuf;
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sg_count = edesc->src_nents ?: 1;
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if (is_sec1 && sg_count > 1)
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sg_copy_to_buffer(req_ctx->psrc, sg_count, edesc->buf, length);
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else
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sg_pcopy_to_buffer(req_ctx->psrc, sg_count,
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edesc->buf + sizeof(struct talitos_desc),
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length, req_ctx->nbuf);
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else if (length)
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sg_count = dma_map_sg(dev, req_ctx->psrc, sg_count,
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DMA_TO_DEVICE);
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/*
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* data in
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*/
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sg_count = talitos_sg_map(dev, req_ctx->psrc, length, edesc,
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&desc->ptr[3], sg_count, 0, 0);
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if (sg_count > 1)
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sync_needed = true;
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if (is_sec1 && req_ctx->nbuf) {
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to_talitos_ptr(&desc->ptr[3], ctx->dma_buf, req_ctx->nbuf,
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is_sec1);
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} else {
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sg_count = talitos_sg_map(dev, req_ctx->psrc, length, edesc,
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&desc->ptr[3], sg_count, offset, 0);
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if (sg_count > 1)
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sync_needed = true;
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}
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/* fifth DWORD empty */
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@ -1778,6 +1814,36 @@ static int common_nonsnoop_hash(struct talitos_edesc *edesc,
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if (is_sec1 && from_talitos_ptr_len(&desc->ptr[3], true) == 0)
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talitos_handle_buggy_hash(ctx, edesc, &desc->ptr[3]);
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if (is_sec1 && req_ctx->nbuf && length) {
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struct talitos_desc *desc2 = desc + 1;
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dma_addr_t next_desc;
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memset(desc2, 0, sizeof(*desc2));
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desc2->hdr = desc->hdr;
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desc2->hdr &= ~DESC_HDR_MODE0_MDEU_INIT;
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desc2->hdr1 = desc2->hdr;
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desc->hdr &= ~DESC_HDR_MODE0_MDEU_PAD;
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desc->hdr |= DESC_HDR_MODE0_MDEU_CONT;
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desc->hdr &= ~DESC_HDR_DONE_NOTIFY;
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to_talitos_ptr(&desc2->ptr[1], ctx->dma_hw_context,
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req_ctx->hw_context_size, is_sec1);
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copy_talitos_ptr(&desc2->ptr[2], &desc->ptr[2], is_sec1);
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sg_count = talitos_sg_map(dev, req_ctx->psrc, length, edesc,
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&desc2->ptr[3], sg_count, offset, 0);
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if (sg_count > 1)
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sync_needed = true;
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copy_talitos_ptr(&desc2->ptr[5], &desc->ptr[5], is_sec1);
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if (req_ctx->last)
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to_talitos_ptr(&desc->ptr[5], ctx->dma_hw_context,
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req_ctx->hw_context_size, is_sec1);
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next_desc = dma_map_single(dev, &desc2->hdr1, TALITOS_DESC_SIZE,
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DMA_BIDIRECTIONAL);
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desc->next_desc = cpu_to_be32(next_desc);
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}
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if (sync_needed)
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dma_sync_single_for_device(dev, edesc->dma_link_tbl,
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edesc->dma_len, DMA_BIDIRECTIONAL);
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@ -1796,6 +1862,11 @@ static struct talitos_edesc *ahash_edesc_alloc(struct ahash_request *areq,
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struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
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struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
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struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
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struct talitos_private *priv = dev_get_drvdata(ctx->dev);
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bool is_sec1 = has_ftr_sec1(priv);
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if (is_sec1)
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nbytes -= req_ctx->nbuf;
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return talitos_edesc_alloc(ctx->dev, req_ctx->psrc, NULL, NULL, 0,
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nbytes, 0, 0, 0, areq->base.flags, false);
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@ -1808,6 +1879,8 @@ static int ahash_init(struct ahash_request *areq)
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struct device *dev = ctx->dev;
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struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
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unsigned int size;
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struct talitos_private *priv = dev_get_drvdata(dev);
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bool is_sec1 = has_ftr_sec1(priv);
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/* Initialize the context */
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req_ctx->nbuf = 0;
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@ -1823,6 +1896,13 @@ static int ahash_init(struct ahash_request *areq)
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DMA_BIDIRECTIONAL);
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ctx->dma_hw_context = dma_map_single(dev, req_ctx->hw_context, size,
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DMA_BIDIRECTIONAL);
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if (ctx->dma_buf)
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dma_unmap_single(dev, ctx->dma_buf, sizeof(req_ctx->buf),
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DMA_TO_DEVICE);
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if (is_sec1)
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ctx->dma_buf = dma_map_single(dev, req_ctx->buf,
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sizeof(req_ctx->buf),
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DMA_TO_DEVICE);
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return 0;
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}
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@ -1871,6 +1951,10 @@ static int ahash_process_req(struct ahash_request *areq, unsigned int nbytes)
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unsigned int to_hash_later;
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unsigned int nsg;
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int nents;
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struct device *dev = ctx->dev;
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struct talitos_private *priv = dev_get_drvdata(dev);
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bool is_sec1 = has_ftr_sec1(priv);
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int offset = 0;
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if (!req_ctx->last && (nbytes + req_ctx->nbuf <= blocksize)) {
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/* Buffer up to one whole block */
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@ -1901,13 +1985,27 @@ static int ahash_process_req(struct ahash_request *areq, unsigned int nbytes)
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}
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/* Chain in any previously buffered data */
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if (req_ctx->nbuf) {
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if (!is_sec1 && req_ctx->nbuf) {
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nsg = (req_ctx->nbuf < nbytes_to_hash) ? 2 : 1;
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sg_init_table(req_ctx->bufsl, nsg);
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sg_set_buf(req_ctx->bufsl, req_ctx->buf, req_ctx->nbuf);
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if (nsg > 1)
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sg_chain(req_ctx->bufsl, 2, areq->src);
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req_ctx->psrc = req_ctx->bufsl;
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} else if (is_sec1 && req_ctx->nbuf && req_ctx->nbuf < blocksize) {
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if (nbytes_to_hash > blocksize)
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offset = blocksize - req_ctx->nbuf;
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else
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offset = nbytes_to_hash - req_ctx->nbuf;
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nents = sg_nents_for_len(areq->src, offset);
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if (nents < 0) {
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dev_err(ctx->dev, "Invalid number of src SG.\n");
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return nents;
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}
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sg_copy_to_buffer(areq->src, nents,
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req_ctx->buf + req_ctx->nbuf, offset);
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req_ctx->nbuf += offset;
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req_ctx->psrc = areq->src;
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} else
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req_ctx->psrc = areq->src;
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@ -1940,6 +2038,9 @@ static int ahash_process_req(struct ahash_request *areq, unsigned int nbytes)
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/* request SEC to INIT hash. */
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if (req_ctx->first && !req_ctx->swinit)
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edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_INIT;
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if (is_sec1)
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dma_sync_single_for_device(dev, ctx->dma_buf,
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req_ctx->nbuf, DMA_TO_DEVICE);
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/* When the tfm context has a keylen, it's an HMAC.
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* A first or last (ie. not middle) descriptor must request HMAC.
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@ -1947,7 +2048,7 @@ static int ahash_process_req(struct ahash_request *areq, unsigned int nbytes)
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if (ctx->keylen && (req_ctx->first || req_ctx->last))
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edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_HMAC;
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return common_nonsnoop_hash(edesc, areq, nbytes_to_hash,
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return common_nonsnoop_hash(edesc, areq, nbytes_to_hash, offset,
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ahash_done);
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}
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@ -2019,6 +2120,8 @@ static int ahash_import(struct ahash_request *areq, const void *in)
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unsigned int size;
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struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
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struct device *dev = ctx->dev;
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struct talitos_private *priv = dev_get_drvdata(dev);
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bool is_sec1 = has_ftr_sec1(priv);
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memset(req_ctx, 0, sizeof(*req_ctx));
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size = (crypto_ahash_digestsize(tfm) <= SHA256_DIGEST_SIZE)
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@ -2032,7 +2135,14 @@ static int ahash_import(struct ahash_request *areq, const void *in)
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memcpy(req_ctx->hw_context, export->hw_context, size);
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ctx->dma_hw_context = dma_map_single(dev, req_ctx->hw_context, size,
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DMA_BIDIRECTIONAL);
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if (ctx->dma_buf)
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dma_unmap_single(dev, ctx->dma_buf, sizeof(req_ctx->buf),
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DMA_TO_DEVICE);
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memcpy(req_ctx->buf, export->buf, export->nbuf);
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if (is_sec1)
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ctx->dma_buf = dma_map_single(dev, req_ctx->buf,
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sizeof(req_ctx->buf),
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DMA_TO_DEVICE);
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req_ctx->swinit = export->swinit;
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req_ctx->first = export->first;
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req_ctx->last = export->last;
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@ -2986,6 +3096,9 @@ static void talitos_cra_exit_ahash(struct crypto_tfm *tfm)
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if (ctx->dma_hw_context)
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dma_unmap_single(dev, ctx->dma_hw_context, size,
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DMA_BIDIRECTIONAL);
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if (ctx->dma_buf)
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dma_unmap_single(dev, ctx->dma_buf, HASH_MAX_BLOCK_SIZE,
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DMA_TO_DEVICE);
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}
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/*
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@ -236,6 +236,7 @@ static inline bool has_ftr_sec1(struct talitos_private *priv)
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#define TALITOS_CCCR_LO_IWSE 0x80 /* chan. ICCR writeback enab. */
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#define TALITOS_CCCR_LO_EAE 0x20 /* extended address enable */
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#define TALITOS_CCCR_LO_CDWE 0x10 /* chan. done writeback enab. */
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#define TALITOS_CCCR_LO_NE 0x8 /* fetch next descriptor enab. */
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#define TALITOS_CCCR_LO_NT 0x4 /* notification type */
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#define TALITOS_CCCR_LO_CDIE 0x2 /* channel done IRQ enable */
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#define TALITOS1_CCCR_LO_RESET 0x1 /* channel reset on SEC1 */
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