[PATCH] bnx2: update nvram code for 5708
Update bnx2 nvram code with support for 5708. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Michael Chan
John W. Linville
parent
12d30d89e5
commit
371377091d
2 changed files with 87 additions and 23 deletions
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@ -79,38 +79,88 @@ static struct pci_device_id bnx2_pci_tbl[] = {
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static struct flash_spec flash_table[] =
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{
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/* Slow EEPROM */
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{0x00000000, 0x40030380, 0x009f0081, 0xa184a053, 0xaf000400,
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{0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
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1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
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SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
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"EEPROM - slow"},
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/* Fast EEPROM */
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{0x02000000, 0x62008380, 0x009f0081, 0xa184a053, 0xaf000400,
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1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
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SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
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"EEPROM - fast"},
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/* ATMEL AT45DB011B (buffered flash) */
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{0x02000003, 0x6e008173, 0x00570081, 0x68848353, 0xaf000400,
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1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
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BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
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"Buffered flash"},
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/* Saifun SA25F005 (non-buffered flash) */
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/* strap, cfg1, & write1 need updates */
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{0x01000003, 0x5f008081, 0x00050081, 0x03840253, 0xaf020406,
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/* Expansion entry 0001 */
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{0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
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0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
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SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
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"Non-buffered flash (64kB)"},
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SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
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"Entry 0001"},
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/* Saifun SA25F010 (non-buffered flash) */
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/* strap, cfg1, & write1 need updates */
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{0x00000001, 0x47008081, 0x00050081, 0x03840253, 0xaf020406,
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{0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
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0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
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SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
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"Non-buffered flash (128kB)"},
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/* Saifun SA25F020 (non-buffered flash) */
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/* strap, cfg1, & write1 need updates */
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{0x00000003, 0x4f008081, 0x00050081, 0x03840253, 0xaf020406,
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{0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
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0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
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SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
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"Non-buffered flash (256kB)"},
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/* Expansion entry 0100 */
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{0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
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0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
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SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
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"Entry 0100"},
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/* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
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{0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
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0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
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ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
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"Entry 0101: ST M45PE10 (128kB non-bufferred)"},
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/* Entry 0110: ST M45PE20 (non-buffered flash)*/
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{0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
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0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
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ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
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"Entry 0110: ST M45PE20 (256kB non-bufferred)"},
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/* Saifun SA25F005 (non-buffered flash) */
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/* strap, cfg1, & write1 need updates */
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{0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
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0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
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SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
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"Non-buffered flash (64kB)"},
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/* Fast EEPROM */
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{0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
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1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
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SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
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"EEPROM - fast"},
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/* Expansion entry 1001 */
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{0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
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0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
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SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
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"Entry 1001"},
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/* Expansion entry 1010 */
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{0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
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0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
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SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
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"Entry 1010"},
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/* ATMEL AT45DB011B (buffered flash) */
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{0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
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1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
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BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
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"Buffered flash (128kB)"},
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/* Expansion entry 1100 */
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{0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
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0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
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SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
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"Entry 1100"},
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/* Expansion entry 1101 */
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{0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
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0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
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SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
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"Entry 1101"},
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/* Ateml Expansion entry 1110 */
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{0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
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1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
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BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
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"Entry 1110 (Atmel)"},
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/* ATMEL AT45DB021B (buffered flash) */
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{0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
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1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
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BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
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"Buffered flash (256kB)"},
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};
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MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
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@ -2529,21 +2579,27 @@ bnx2_init_nvram(struct bnx2 *bp)
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/* Flash interface has been reconfigured */
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for (j = 0, flash = &flash_table[0]; j < entry_count;
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j++, flash++) {
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if (val == flash->config1) {
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j++, flash++) {
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if ((val & FLASH_BACKUP_STRAP_MASK) ==
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(flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
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bp->flash_info = flash;
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break;
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}
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}
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}
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else {
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u32 mask;
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/* Not yet been reconfigured */
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if (val & (1 << 23))
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mask = FLASH_BACKUP_STRAP_MASK;
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else
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mask = FLASH_STRAP_MASK;
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for (j = 0, flash = &flash_table[0]; j < entry_count;
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j++, flash++) {
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if ((val & FLASH_STRAP_MASK) == flash->strapping) {
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if ((val & mask) == (flash->strapping & mask)) {
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bp->flash_info = flash;
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/* Request access to the flash interface. */
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@ -3847,7 +3847,7 @@ struct sw_bd {
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#define BUFFERED_FLASH_PHY_PAGE_SIZE (1 << BUFFERED_FLASH_PAGE_BITS)
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#define BUFFERED_FLASH_BYTE_ADDR_MASK (BUFFERED_FLASH_PHY_PAGE_SIZE-1)
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#define BUFFERED_FLASH_PAGE_SIZE 264
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#define BUFFERED_FLASH_TOTAL_SIZE 131072
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#define BUFFERED_FLASH_TOTAL_SIZE 0x21000
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#define SAIFUN_FLASH_PAGE_BITS 8
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#define SAIFUN_FLASH_PHY_PAGE_SIZE (1 << SAIFUN_FLASH_PAGE_BITS)
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@ -3855,6 +3855,12 @@ struct sw_bd {
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#define SAIFUN_FLASH_PAGE_SIZE 256
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#define SAIFUN_FLASH_BASE_TOTAL_SIZE 65536
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#define ST_MICRO_FLASH_PAGE_BITS 8
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#define ST_MICRO_FLASH_PHY_PAGE_SIZE (1 << ST_MICRO_FLASH_PAGE_BITS)
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#define ST_MICRO_FLASH_BYTE_ADDR_MASK (ST_MICRO_FLASH_PHY_PAGE_SIZE-1)
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#define ST_MICRO_FLASH_PAGE_SIZE 256
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#define ST_MICRO_FLASH_BASE_TOTAL_SIZE 65536
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#define NVRAM_TIMEOUT_COUNT 30000
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@ -3863,6 +3869,8 @@ struct sw_bd {
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BNX2_NVM_CFG1_PROTECT_MODE | \
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BNX2_NVM_CFG1_FLASH_SIZE)
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#define FLASH_BACKUP_STRAP_MASK (0xf << 26)
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struct flash_spec {
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u32 strapping;
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u32 config1;
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