sh: Switch SH-5 to use CONFIG_PAGE_OFFSET.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
parent
6deb6f9129
commit
36763b22be
5 changed files with 20 additions and 19 deletions
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@ -85,7 +85,7 @@ KBUILD_IMAGE := arch/sh/boot/zImage
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ifdef CONFIG_SUPERH32
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LDFLAGS_vmlinux += -e _stext
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else
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LDFLAGS_vmlinux += --defsym phys_stext=_stext-$(CONFIG_CACHED_MEMORY_OFFSET) \
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LDFLAGS_vmlinux += --defsym phys_stext=_stext-$(CONFIG_PAGE_OFFSET) \
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--defsym phys_stext_shmedia=phys_stext+1 \
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-e phys_stext_shmedia
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endif
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@ -432,7 +432,7 @@ reset_or_panic:
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synco /* TAKum03020 (but probably a good idea anyway.) */
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putcon SP, DCR
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/* First save r0-1 and tr0, as we need to use these */
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movi resvec_save_area-CONFIG_CACHED_MEMORY_OFFSET, SP
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movi resvec_save_area-CONFIG_PAGE_OFFSET, SP
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st.q SP, 0, r0
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st.q SP, 8, r1
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gettr tr0, r0
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@ -442,7 +442,7 @@ reset_or_panic:
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getcon EXPEVT, r0
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movi RESET_CAUSE, r1
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sub r1, r0, r1 /* r1=0 if reset */
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movi _stext-CONFIG_CACHED_MEMORY_OFFSET, r0
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movi _stext-CONFIG_PAGE_OFFSET, r0
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ori r0, 1, r0
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ptabs r0, tr0
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beqi r1, 0, tr0 /* Jump to start address if reset */
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@ -454,7 +454,7 @@ reset_or_panic:
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beqi r1, 0, tr0 /* jump if single step */
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/* Now jump to where we save the registers. */
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movi panic_stash_regs-CONFIG_CACHED_MEMORY_OFFSET, r1
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movi panic_stash_regs-CONFIG_PAGE_OFFSET, r1
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ptabs r1, tr0
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blink tr0, r63
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@ -490,7 +490,7 @@ debug_exception:
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*/
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putcon SP, DCR
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/* Save SSR & SPC, together with R0 & R1, as we need to use 2 regs. */
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movi resvec_save_area-CONFIG_CACHED_MEMORY_OFFSET, SP
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movi resvec_save_area-CONFIG_PAGE_OFFSET, SP
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/* With the MMU off, we are bypassing the cache, so purge any
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* data that will be made stale by the following stores.
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@ -558,7 +558,7 @@ debug_interrupt:
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/* Save original stack pointer into KCR1 */
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synco
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putcon SP, KCR1
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movi resvec_save_area-CONFIG_CACHED_MEMORY_OFFSET, SP
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movi resvec_save_area-CONFIG_PAGE_OFFSET, SP
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ocbp SP, 0
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ocbp SP, 32
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synco
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@ -607,7 +607,7 @@ debug_interrupt:
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movi EVENT_FAULT_NOT_TLB, r4
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or SP, ZERO, r5
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movi CONFIG_CACHED_MEMORY_OFFSET, r6
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movi CONFIG_PAGE_OFFSET, r6
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add r6, r5, r5
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getcon KCR1, SP
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@ -1366,7 +1366,7 @@ route_to_panic_handler:
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last-chance debugging, e.g. if no output wants to go to the console.
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*/
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movi panic_handler - CONFIG_CACHED_MEMORY_OFFSET, r1
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movi panic_handler - CONFIG_PAGE_OFFSET, r1
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ptabs r1, tr0
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pta 1f, tr1
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gettr tr1, r0
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@ -1408,7 +1408,7 @@ peek_real_address_q:
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andc r1, r36, r1 /* turn sr.mmu off in real mode section */
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putcon r1, ssr
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movi .peek0 - CONFIG_CACHED_MEMORY_OFFSET, r36 /* real mode target address */
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movi .peek0 - CONFIG_PAGE_OFFSET, r36 /* real mode target address */
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movi 1f, r37 /* virtual mode return addr */
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putcon r36, spc
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@ -1457,7 +1457,7 @@ poke_real_address_q:
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andc r1, r36, r1 /* turn sr.mmu off in real mode section */
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putcon r1, ssr
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movi .poke0-CONFIG_CACHED_MEMORY_OFFSET, r36 /* real mode target address */
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movi .poke0-CONFIG_PAGE_OFFSET, r36 /* real mode target address */
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movi 1f, r37 /* virtual mode return addr */
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putcon r36, spc
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@ -1954,7 +1954,7 @@ panic_stash_regs:
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getcon SSR,r3
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getcon EXPEVT,r4
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/* Prepare to jump to C - physical address */
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movi panic_handler-CONFIG_CACHED_MEMORY_OFFSET, r1
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movi panic_handler-CONFIG_PAGE_OFFSET, r1
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ori r1, 1, r1
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ptabs r1, tr0
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getcon DCR, SP
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@ -2055,7 +2055,7 @@ trap_init:
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andi r19, -4, r19 /* reset MMUOFF + reserved */
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/* For RESVEC exceptions we force the MMU off, which means we need the
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physical address. */
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movi LRESVEC_block-CONFIG_CACHED_MEMORY_OFFSET, r20
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movi LRESVEC_block-CONFIG_PAGE_OFFSET, r20
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andi r20, -4, r20 /* reset reserved */
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ori r20, 1, r20 /* set MMUOFF */
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putcon r19, VBR
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@ -38,9 +38,9 @@
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#define MMUDR_END DTLB_LAST_VAR_UNRESTRICTED+TLB_STEP
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#define MMUDR_STEP TLB_STEP
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/* Safety check : CONFIG_CACHED_MEMORY_OFFSET has to be a multiple of 512Mb */
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#if (CONFIG_CACHED_MEMORY_OFFSET & ((1UL<<29)-1))
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#error "CONFIG_CACHED_MEMORY_OFFSET must be a multiple of 512Mb"
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/* Safety check : CONFIG_PAGE_OFFSET has to be a multiple of 512Mb */
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#if (CONFIG_PAGE_OFFSET & ((1UL<<29)-1))
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#error "CONFIG_PAGE_OFFSET must be a multiple of 512Mb"
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#endif
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/*
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@ -49,7 +49,7 @@
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/* Deal safely with the case where the base of RAM is not 512Mb aligned */
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#define ALIGN_512M_MASK (0xffffffffe0000000)
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#define ALIGNED_EFFECTIVE ((CONFIG_CACHED_MEMORY_OFFSET + CONFIG_MEMORY_START) & ALIGN_512M_MASK)
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#define ALIGNED_EFFECTIVE ((CONFIG_PAGE_OFFSET + CONFIG_MEMORY_START) & ALIGN_512M_MASK)
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#define ALIGNED_PHYSICAL (CONFIG_MEMORY_START & ALIGN_512M_MASK)
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#define MMUIR_TEXT_H (0x0000000000000003 | ALIGNED_EFFECTIVE)
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@ -24,7 +24,7 @@
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#include <asm/cache.h>
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#include <asm/thread_info.h>
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#define LOAD_OFFSET CONFIG_CACHED_MEMORY_OFFSET
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#define LOAD_OFFSET CONFIG_PAGE_OFFSET
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#include <asm-generic/vmlinux.lds.h>
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OUTPUT_ARCH(sh:sh5)
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@ -34,7 +34,7 @@ OUTPUT_ARCH(sh:sh5)
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ENTRY(__start)
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SECTIONS
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{
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. = CONFIG_CACHED_MEMORY_OFFSET + CONFIG_MEMORY_START + PAGE_SIZE;
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. = CONFIG_PAGE_OFFSET + CONFIG_MEMORY_START + PAGE_SIZE;
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_text = .; /* Text and read-only data */
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.empty_zero_page : C_PHYS(.empty_zero_page) {
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@ -17,7 +17,8 @@ config MMU
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config PAGE_OFFSET
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hex
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default "0x80000000" if MMU
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default "0x80000000" if MMU && SUPERH32
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default "0x20000000" if MMU && SUPERH64
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default "0x00000000"
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config MEMORY_START
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