Merge branch 'drm-fixes-3.6' of git://people.freedesktop.org/~agd5f/linux into drm-fixes
Alex writes: This is the current set of radeon fixes for 3.6. Two small fixes: - fix the fence issues introduced in 3.5 with 64-bit fences - PLL fix for multiple DP heads * 'drm-fixes-3.6' of git://people.freedesktop.org/~agd5f/linux: drm/radeon: make 64bit fences more robust v3 drm/radeon: rework pll selection (v3)
This commit is contained in:
Dave Airlie
commit
363fca8225
2 changed files with 134 additions and 37 deletions
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@ -1479,14 +1479,98 @@ static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
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}
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}
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/**
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* radeon_get_pll_use_mask - look up a mask of which pplls are in use
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*
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* @crtc: drm crtc
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*
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* Returns the mask of which PPLLs (Pixel PLLs) are in use.
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*/
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static u32 radeon_get_pll_use_mask(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_crtc *test_crtc;
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struct radeon_crtc *radeon_test_crtc;
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u32 pll_in_use = 0;
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list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
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if (crtc == test_crtc)
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continue;
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radeon_test_crtc = to_radeon_crtc(test_crtc);
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if (radeon_test_crtc->pll_id != ATOM_PPLL_INVALID)
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pll_in_use |= (1 << radeon_test_crtc->pll_id);
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}
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return pll_in_use;
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}
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/**
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* radeon_get_shared_dp_ppll - return the PPLL used by another crtc for DP
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*
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* @crtc: drm crtc
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*
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* Returns the PPLL (Pixel PLL) used by another crtc/encoder which is
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* also in DP mode. For DP, a single PPLL can be used for all DP
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* crtcs/encoders.
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*/
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static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_encoder *test_encoder;
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struct radeon_crtc *radeon_test_crtc;
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list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
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if (test_encoder->crtc && (test_encoder->crtc != crtc)) {
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if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) {
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/* for DP use the same PLL for all */
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radeon_test_crtc = to_radeon_crtc(test_encoder->crtc);
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if (radeon_test_crtc->pll_id != ATOM_PPLL_INVALID)
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return radeon_test_crtc->pll_id;
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}
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}
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}
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return ATOM_PPLL_INVALID;
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}
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/**
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* radeon_atom_pick_pll - Allocate a PPLL for use by the crtc.
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*
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* @crtc: drm crtc
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*
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* Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
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* a single PPLL can be used for all DP crtcs/encoders. For non-DP
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* monitors a dedicated PPLL must be used. If a particular board has
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* an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
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* as there is no need to program the PLL itself. If we are not able to
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* allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
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* avoid messing up an existing monitor.
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*
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* Asic specific PLL information
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*
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* DCE 6.1
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* - PPLL2 is only available to UNIPHYA (both DP and non-DP)
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* - PPLL0, PPLL1 are available for UNIPHYB/C/D/E/F (both DP and non-DP)
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*
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* DCE 6.0
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* - PPLL0 is available to all UNIPHY (DP only)
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* - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
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*
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* DCE 5.0
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* - DCPLL is available to all UNIPHY (DP only)
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* - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
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*
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* DCE 3.0/4.0/4.1
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* - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
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*
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*/
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static int radeon_atom_pick_pll(struct drm_crtc *crtc)
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{
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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struct drm_device *dev = crtc->dev;
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struct radeon_device *rdev = dev->dev_private;
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struct drm_encoder *test_encoder;
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struct drm_crtc *test_crtc;
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uint32_t pll_in_use = 0;
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u32 pll_in_use;
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int pll;
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if (ASIC_IS_DCE61(rdev)) {
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list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
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@ -1498,32 +1582,40 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
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if ((test_radeon_encoder->encoder_id ==
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ENCODER_OBJECT_ID_INTERNAL_UNIPHY) &&
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(dig->linkb == false)) /* UNIPHY A uses PPLL2 */
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(dig->linkb == false))
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/* UNIPHY A uses PPLL2 */
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return ATOM_PPLL2;
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else if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) {
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/* UNIPHY B/C/D/E/F */
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if (rdev->clock.dp_extclk)
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/* skip PPLL programming if using ext clock */
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return ATOM_PPLL_INVALID;
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else {
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/* use the same PPLL for all DP monitors */
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pll = radeon_get_shared_dp_ppll(crtc);
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if (pll != ATOM_PPLL_INVALID)
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return pll;
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}
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}
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break;
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}
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}
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/* UNIPHY B/C/D/E/F */
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list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
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struct radeon_crtc *radeon_test_crtc;
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if (crtc == test_crtc)
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continue;
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radeon_test_crtc = to_radeon_crtc(test_crtc);
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if ((radeon_test_crtc->pll_id == ATOM_PPLL0) ||
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(radeon_test_crtc->pll_id == ATOM_PPLL1))
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pll_in_use |= (1 << radeon_test_crtc->pll_id);
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}
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if (!(pll_in_use & 4))
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pll_in_use = radeon_get_pll_use_mask(crtc);
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if (!(pll_in_use & (1 << ATOM_PPLL0)))
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return ATOM_PPLL0;
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return ATOM_PPLL1;
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if (!(pll_in_use & (1 << ATOM_PPLL1)))
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return ATOM_PPLL1;
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DRM_ERROR("unable to allocate a PPLL\n");
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return ATOM_PPLL_INVALID;
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} else if (ASIC_IS_DCE4(rdev)) {
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list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
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if (test_encoder->crtc && (test_encoder->crtc == crtc)) {
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/* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock,
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* depending on the asic:
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* DCE4: PPLL or ext clock
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* DCE5: DCPLL or ext clock
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* DCE5: PPLL, DCPLL, or ext clock
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* DCE6: PPLL, PPLL0, or ext clock
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*
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* Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip
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* PPLL/DCPLL programming and only program the DP DTO for the
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@ -1531,31 +1623,34 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
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*/
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if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) {
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if (rdev->clock.dp_extclk)
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/* skip PPLL programming if using ext clock */
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return ATOM_PPLL_INVALID;
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else if (ASIC_IS_DCE6(rdev))
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/* use PPLL0 for all DP */
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return ATOM_PPLL0;
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else if (ASIC_IS_DCE5(rdev))
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/* use DCPLL for all DP */
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return ATOM_DCPLL;
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else {
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/* use the same PPLL for all DP monitors */
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pll = radeon_get_shared_dp_ppll(crtc);
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if (pll != ATOM_PPLL_INVALID)
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return pll;
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}
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}
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break;
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}
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}
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/* otherwise, pick one of the plls */
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list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
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struct radeon_crtc *radeon_test_crtc;
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if (crtc == test_crtc)
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continue;
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radeon_test_crtc = to_radeon_crtc(test_crtc);
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if ((radeon_test_crtc->pll_id >= ATOM_PPLL1) &&
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(radeon_test_crtc->pll_id <= ATOM_PPLL2))
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pll_in_use |= (1 << radeon_test_crtc->pll_id);
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}
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if (!(pll_in_use & 1))
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/* all other cases */
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pll_in_use = radeon_get_pll_use_mask(crtc);
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if (!(pll_in_use & (1 << ATOM_PPLL2)))
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return ATOM_PPLL2;
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if (!(pll_in_use & (1 << ATOM_PPLL1)))
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return ATOM_PPLL1;
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return ATOM_PPLL2;
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DRM_ERROR("unable to allocate a PPLL\n");
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return ATOM_PPLL_INVALID;
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} else
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/* use PPLL1 or PPLL2 */
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return radeon_crtc->crtc_id;
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}
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@ -1697,7 +1792,7 @@ static void atombios_crtc_disable(struct drm_crtc *crtc)
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break;
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}
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done:
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radeon_crtc->pll_id = -1;
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radeon_crtc->pll_id = ATOM_PPLL_INVALID;
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}
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static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
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@ -1746,6 +1841,6 @@ void radeon_atombios_init_crtc(struct drm_device *dev,
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else
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radeon_crtc->crtc_offset = 0;
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}
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radeon_crtc->pll_id = -1;
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radeon_crtc->pll_id = ATOM_PPLL_INVALID;
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drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
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}
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@ -131,7 +131,7 @@ int radeon_fence_emit(struct radeon_device *rdev,
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*/
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void radeon_fence_process(struct radeon_device *rdev, int ring)
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{
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uint64_t seq, last_seq;
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uint64_t seq, last_seq, last_emitted;
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unsigned count_loop = 0;
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bool wake = false;
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@ -158,13 +158,15 @@ void radeon_fence_process(struct radeon_device *rdev, int ring)
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*/
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last_seq = atomic64_read(&rdev->fence_drv[ring].last_seq);
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do {
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last_emitted = rdev->fence_drv[ring].sync_seq[ring];
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seq = radeon_fence_read(rdev, ring);
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seq |= last_seq & 0xffffffff00000000LL;
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if (seq < last_seq) {
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seq += 0x100000000LL;
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seq &= 0xffffffff;
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seq |= last_emitted & 0xffffffff00000000LL;
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}
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if (seq == last_seq) {
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if (seq <= last_seq || seq > last_emitted) {
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break;
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}
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/* If we loop over we don't want to return without
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