[ARM] 4595/1: ns9xxx: define registers as void __iomem * instead of volatile u32
As a consequence registers are now accessed with __raw_{read,write}[bl].
Signed-off-by: Uwe Kleine-König <ukleinek@informatik.uni-freiburg.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Uwe Kleine-König
Russell King
parent
c54ecb2481
commit
361c7ad607
8 changed files with 92 additions and 74 deletions
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@ -45,7 +45,13 @@ static void a9m9750dev_fpga_ack_irq(unsigned int irq)
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static void a9m9750dev_fpga_mask_irq(unsigned int irq)
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{
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FPGA_IER &= ~(1 << (irq - FPGA_IRQ(0)));
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u8 ier;
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ier = __raw_readb(FPGA_IER);
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ier &= ~(1 << (irq - FPGA_IRQ(0)));
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__raw_writeb(ier, FPGA_IER);
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}
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static void a9m9750dev_fpga_maskack_irq(unsigned int irq)
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@ -56,7 +62,13 @@ static void a9m9750dev_fpga_maskack_irq(unsigned int irq)
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static void a9m9750dev_fpga_unmask_irq(unsigned int irq)
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{
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FPGA_IER |= 1 << (irq - FPGA_IRQ(0));
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u8 ier;
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ier = __raw_readb(FPGA_IER);
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ier |= 1 << (irq - FPGA_IRQ(0));
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__raw_writeb(ier, FPGA_IER);
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}
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static struct irq_chip a9m9750dev_fpga_chip = {
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@ -69,7 +81,7 @@ static struct irq_chip a9m9750dev_fpga_chip = {
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static void a9m9750dev_fpga_demux_handler(unsigned int irq,
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struct irq_desc *desc)
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{
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int stat = FPGA_ISR;
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u8 stat = __raw_readb(FPGA_ISR);
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desc->chip->mask_ack(irq);
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@ -89,7 +101,7 @@ static void a9m9750dev_fpga_demux_handler(unsigned int irq,
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void __init board_a9m9750dev_init_irq(void)
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{
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u32 reg;
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u32 eic;
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int i;
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if (gpio_request(11, "board a9m9750dev extirq2") == 0)
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@ -105,10 +117,10 @@ void __init board_a9m9750dev_init_irq(void)
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}
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/* IRQ_EXT2: level sensitive + active low */
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reg = SYS_EIC(2);
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REGSET(reg, SYS_EIC, PLTY, AL);
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REGSET(reg, SYS_EIC, LVEDG, LEVEL);
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SYS_EIC(2) = reg;
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eic = __raw_readl(SYS_EIC(2));
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REGSET(eic, SYS_EIC, PLTY, AL);
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REGSET(eic, SYS_EIC, LVEDG, LEVEL);
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__raw_writel(eic, SYS_EIC(2));
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set_irq_chained_handler(IRQ_EXT2,
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a9m9750dev_fpga_demux_handler);
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@ -172,17 +184,18 @@ void __init board_a9m9750dev_init_machine(void)
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u32 reg;
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/* setup static CS0: memory base ... */
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REGSETIM(SYS_SMCSSMB(0), SYS_SMCSSMB, CSxB,
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NS9XXX_CSxSTAT_PHYS(0) >> 12);
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reg = __raw_readl(SYS_SMCSSMB(0));
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REGSETIM(reg, SYS_SMCSSMB, CSxB, NS9XXX_CSxSTAT_PHYS(0) >> 12);
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__raw_writel(reg, SYS_SMCSSMB(0));
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/* ... and mask */
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reg = SYS_SMCSSMM(0);
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reg = __raw_readl(SYS_SMCSSMM(0));
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REGSETIM(reg, SYS_SMCSSMM, CSxM, 0xfffff);
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REGSET(reg, SYS_SMCSSMM, CSEx, EN);
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SYS_SMCSSMM(0) = reg;
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__raw_writel(reg, SYS_SMCSSMM(0));
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/* setup static CS0: memory configuration */
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reg = MEM_SMC(0);
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reg = __raw_readl(MEM_SMC(0));
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REGSET(reg, MEM_SMC, PSMC, OFF);
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REGSET(reg, MEM_SMC, BSMC, OFF);
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REGSET(reg, MEM_SMC, EW, OFF);
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@ -190,13 +203,13 @@ void __init board_a9m9750dev_init_machine(void)
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REGSET(reg, MEM_SMC, PC, AL);
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REGSET(reg, MEM_SMC, PM, DIS);
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REGSET(reg, MEM_SMC, MW, 8);
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MEM_SMC(0) = reg;
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__raw_writel(reg, MEM_SMC(0));
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/* setup static CS0: timing */
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MEM_SMWED(0) = 0x2;
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MEM_SMOED(0) = 0x2;
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MEM_SMRD(0) = 0x6;
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MEM_SMWD(0) = 0x6;
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__raw_writel(0x2, MEM_SMWED(0));
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__raw_writel(0x2, MEM_SMOED(0));
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__raw_writel(0x6, MEM_SMRD(0));
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__raw_writel(0x6, MEM_SMWD(0));
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platform_add_devices(board_a9m9750dev_devices,
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ARRAY_SIZE(board_a9m9750dev_devices));
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@ -16,6 +16,7 @@
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#include <asm/arch-ns9xxx/gpio.h>
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#include <asm/arch-ns9xxx/processor.h>
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#include <asm/arch-ns9xxx/regs-bbu.h>
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#include <asm/io.h>
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#include <asm/bug.h>
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#include <asm/types.h>
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#include <asm/bitops.h>
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@ -47,38 +48,38 @@ static inline int ns9xxx_valid_gpio(unsigned gpio)
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BUG();
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}
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static inline volatile u32 *ns9xxx_gpio_get_gconfaddr(unsigned gpio)
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static inline void __iomem *ns9xxx_gpio_get_gconfaddr(unsigned gpio)
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{
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if (gpio < 56)
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return &BBU_GCONFb1(gpio / 8);
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return BBU_GCONFb1(gpio / 8);
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else
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/*
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* this could be optimised away on
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* ns9750 only builds, but it isn't ...
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*/
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return &BBU_GCONFb2((gpio - 56) / 8);
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return BBU_GCONFb2((gpio - 56) / 8);
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}
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static inline volatile u32 *ns9xxx_gpio_get_gctrladdr(unsigned gpio)
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static inline void __iomem *ns9xxx_gpio_get_gctrladdr(unsigned gpio)
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{
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if (gpio < 32)
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return &BBU_GCTRL1;
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return BBU_GCTRL1;
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else if (gpio < 64)
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return &BBU_GCTRL2;
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return BBU_GCTRL2;
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else
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/* this could be optimised away on ns9750 only builds */
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return &BBU_GCTRL3;
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return BBU_GCTRL3;
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}
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static inline volatile u32 *ns9xxx_gpio_get_gstataddr(unsigned gpio)
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static inline void __iomem *ns9xxx_gpio_get_gstataddr(unsigned gpio)
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{
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if (gpio < 32)
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return &BBU_GSTAT1;
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return BBU_GSTAT1;
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else if (gpio < 64)
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return &BBU_GSTAT2;
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return BBU_GSTAT2;
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else
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/* this could be optimised away on ns9750 only builds */
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return &BBU_GSTAT3;
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return BBU_GSTAT3;
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}
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int gpio_request(unsigned gpio, const char *label)
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@ -105,17 +106,17 @@ EXPORT_SYMBOL(gpio_free);
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*/
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static int __ns9xxx_gpio_configure(unsigned gpio, int dir, int inv, int func)
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{
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volatile u32 *conf = ns9xxx_gpio_get_gconfaddr(gpio);
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void __iomem *conf = ns9xxx_gpio_get_gconfaddr(gpio);
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u32 confval;
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unsigned long flags;
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spin_lock_irqsave(&gpio_lock, flags);
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confval = *conf;
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confval = __raw_readl(conf);
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REGSETIM_IDX(confval, BBU_GCONFx, DIR, gpio & 7, dir);
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REGSETIM_IDX(confval, BBU_GCONFx, INV, gpio & 7, inv);
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REGSETIM_IDX(confval, BBU_GCONFx, FUNC, gpio & 7, func);
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*conf = confval;
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__raw_writel(confval, conf);
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spin_unlock_irqrestore(&gpio_lock, flags);
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@ -158,10 +159,10 @@ EXPORT_SYMBOL(gpio_direction_output);
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int gpio_get_value(unsigned gpio)
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{
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volatile u32 *stat = ns9xxx_gpio_get_gstataddr(gpio);
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void __iomem *stat = ns9xxx_gpio_get_gstataddr(gpio);
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int ret;
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ret = 1 & (*stat >> (gpio & 31));
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ret = 1 & (__raw_readl(stat) >> (gpio & 31));
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return ret;
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}
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@ -169,15 +170,20 @@ EXPORT_SYMBOL(gpio_get_value);
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void gpio_set_value(unsigned gpio, int value)
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{
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volatile u32 *ctrl = ns9xxx_gpio_get_gctrladdr(gpio);
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void __iomem *ctrl = ns9xxx_gpio_get_gctrladdr(gpio);
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u32 ctrlval;
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unsigned long flags;
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spin_lock_irqsave(&gpio_lock, flags);
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ctrlval = __raw_readl(ctrl);
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if (value)
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*ctrl |= 1 << (gpio & 31);
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ctrlval |= 1 << (gpio & 31);
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else
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*ctrl &= ~(1 << (gpio & 31));
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ctrlval &= ~(1 << (gpio & 31));
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__raw_writel(ctrlval, ctrl);
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spin_unlock_irqrestore(&gpio_lock, flags);
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}
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@ -9,6 +9,7 @@
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* the Free Software Foundation.
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*/
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#include <linux/interrupt.h>
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#include <asm/io.h>
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#include <asm/mach/irq.h>
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#include <asm/mach-types.h>
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#include <asm/arch-ns9xxx/regs-sys.h>
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@ -20,12 +21,14 @@
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static void ns9xxx_mask_irq(unsigned int irq)
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{
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/* XXX: better use cpp symbols */
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SYS_IC(irq / 4) &= ~(1 << (7 + 8 * (3 - (irq & 3))));
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u32 ic = __raw_readl(SYS_IC(irq / 4));
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ic &= ~(1 << (7 + 8 * (3 - (irq & 3))));
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__raw_writel(ic, SYS_IC(irq / 4));
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}
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static void ns9xxx_ack_irq(unsigned int irq)
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{
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SYS_ISRADDR = 0;
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__raw_writel(0, SYS_ISRADDR);
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}
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static void ns9xxx_maskack_irq(unsigned int irq)
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@ -37,7 +40,9 @@ static void ns9xxx_maskack_irq(unsigned int irq)
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static void ns9xxx_unmask_irq(unsigned int irq)
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{
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/* XXX: better use cpp symbols */
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SYS_IC(irq / 4) |= 1 << (7 + 8 * (3 - (irq & 3)));
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u32 ic = __raw_readl(SYS_IC(irq / 4));
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ic |= 1 << (7 + 8 * (3 - (irq & 3)));
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__raw_writel(ic, SYS_IC(irq / 4));
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}
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static struct irq_chip ns9xxx_chip = {
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@ -53,14 +58,14 @@ void __init ns9xxx_init_irq(void)
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/* disable all IRQs */
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for (i = 0; i < 8; ++i)
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SYS_IC(i) = (4 * i) << 24 | (4 * i + 1) << 16 |
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(4 * i + 2) << 8 | (4 * i + 3);
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__raw_writel((4 * i) << 24 | (4 * i + 1) << 16 |
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(4 * i + 2) << 8 | (4 * i + 3), SYS_IC(i));
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/* simple interrupt prio table:
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* prio(x) < prio(y) <=> x < y
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*/
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for (i = 0; i < 32; ++i)
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SYS_IVA(i) = i;
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__raw_writel(i, SYS_IVA(i));
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for (i = IRQ_WATCHDOG; i <= IRQ_EXT3; ++i) {
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set_irq_chip(i, &ns9xxx_chip);
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@ -27,7 +27,7 @@ static u32 latch;
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static cycle_t ns9xxx_clocksource_read(void)
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{
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return SYS_TR(TIMER_CLOCKSOURCE);
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return __raw_readl(SYS_TR(TIMER_CLOCKSOURCE));
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}
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static struct clocksource ns9xxx_clocksource = {
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@ -42,11 +42,11 @@ static struct clocksource ns9xxx_clocksource = {
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static void ns9xxx_clockevent_setmode(enum clock_event_mode mode,
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struct clock_event_device *clk)
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{
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u32 tc = SYS_TC(TIMER_CLOCKEVENT);
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u32 tc = __raw_readl(SYS_TC(TIMER_CLOCKEVENT));
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switch(mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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SYS_TRC(TIMER_CLOCKEVENT) = latch;
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__raw_writel(latch, SYS_TRC(TIMER_CLOCKEVENT));
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REGSET(tc, SYS_TCx, REN, EN);
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REGSET(tc, SYS_TCx, INTS, EN);
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REGSET(tc, SYS_TCx, TEN, EN);
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@ -66,24 +66,24 @@ static void ns9xxx_clockevent_setmode(enum clock_event_mode mode,
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break;
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}
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SYS_TC(TIMER_CLOCKEVENT) = tc;
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__raw_writel(tc, SYS_TC(TIMER_CLOCKEVENT));
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}
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static int ns9xxx_clockevent_setnextevent(unsigned long evt,
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struct clock_event_device *clk)
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{
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u32 tc = SYS_TC(TIMER_CLOCKEVENT);
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u32 tc = __raw_readl(SYS_TC(TIMER_CLOCKEVENT));
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if (REGGET(tc, SYS_TCx, TEN)) {
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REGSET(tc, SYS_TCx, TEN, DIS);
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SYS_TC(TIMER_CLOCKEVENT) = tc;
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__raw_writel(tc, SYS_TC(TIMER_CLOCKEVENT));
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}
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REGSET(tc, SYS_TCx, TEN, EN);
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SYS_TRC(TIMER_CLOCKEVENT) = evt;
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__raw_writel(evt, SYS_TRC(TIMER_CLOCKEVENT));
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SYS_TC(TIMER_CLOCKEVENT) = tc;
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__raw_writel(tc, SYS_TC(TIMER_CLOCKEVENT));
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return 0;
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}
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@ -104,15 +104,15 @@ static irqreturn_t ns9xxx_clockevent_handler(int irq, void *dev_id)
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struct clock_event_device *evt = &ns9xxx_clockevent_device;
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/* clear irq */
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tc = SYS_TC(timerno);
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tc = __raw_readl(SYS_TC(timerno));
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if (REGGET(tc, SYS_TCx, REN) == SYS_TCx_REN_DIS) {
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REGSET(tc, SYS_TCx, TEN, DIS);
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SYS_TC(timerno) = tc;
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__raw_writel(tc, SYS_TC(timerno));
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}
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REGSET(tc, SYS_TCx, INTC, SET);
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SYS_TC(timerno) = tc;
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__raw_writel(tc, SYS_TC(timerno));
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REGSET(tc, SYS_TCx, INTC, UNSET);
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SYS_TC(timerno) = tc;
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__raw_writel(tc, SYS_TC(timerno));
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evt->event_handler(evt);
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@ -129,13 +129,13 @@ static void __init ns9xxx_timer_init(void)
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{
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int tc;
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tc = SYS_TC(TIMER_CLOCKSOURCE);
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tc = __raw_readl(SYS_TC(TIMER_CLOCKSOURCE));
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if (REGGET(tc, SYS_TCx, TEN)) {
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REGSET(tc, SYS_TCx, TEN, DIS);
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SYS_TC(TIMER_CLOCKSOURCE) = tc;
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__raw_writel(tc, SYS_TC(TIMER_CLOCKSOURCE));
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}
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SYS_TRC(TIMER_CLOCKSOURCE) = 0;
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__raw_writel(0, SYS_TRC(TIMER_CLOCKSOURCE));
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REGSET(tc, SYS_TCx, TEN, EN);
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REGSET(tc, SYS_TCx, TDBG, STOP);
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@ -146,7 +146,7 @@ static void __init ns9xxx_timer_init(void)
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REGSET(tc, SYS_TCx, TSZ, 32);
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REGSET(tc, SYS_TCx, REN, EN);
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SYS_TC(TIMER_CLOCKSOURCE) = tc;
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__raw_writel(tc, SYS_TC(TIMER_CLOCKSOURCE));
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ns9xxx_clocksource.mult = clocksource_hz2mult(ns9xxx_cpuclock(),
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ns9xxx_clocksource.shift);
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@ -155,7 +155,7 @@ static void __init ns9xxx_timer_init(void)
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latch = SH_DIV(ns9xxx_cpuclock(), HZ, 0);
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tc = SYS_TC(TIMER_CLOCKEVENT);
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tc = __raw_readl(SYS_TC(TIMER_CLOCKEVENT));
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REGSET(tc, SYS_TCx, TEN, DIS);
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REGSET(tc, SYS_TCx, TDBG, STOP);
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REGSET(tc, SYS_TCx, TLCS, CPU);
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@ -164,7 +164,7 @@ static void __init ns9xxx_timer_init(void)
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REGSET(tc, SYS_TCx, UDS, DOWN);
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REGSET(tc, SYS_TCx, TSZ, 32);
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REGSET(tc, SYS_TCx, REN, EN);
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SYS_TC(TIMER_CLOCKEVENT) = tc;
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__raw_writel(tc, SYS_TC(TIMER_CLOCKEVENT));
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ns9xxx_clockevent_device.mult = div_sc(ns9xxx_cpuclock(),
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NSEC_PER_SEC, ns9xxx_clockevent_device.shift);
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@ -19,7 +19,7 @@
|
|||
static inline u32 ns9xxx_systemclock(void) __attribute__((const));
|
||||
static inline u32 ns9xxx_systemclock(void)
|
||||
{
|
||||
u32 pll = SYS_PLL;
|
||||
u32 pll = __raw_readl(SYS_PLL);
|
||||
|
||||
/*
|
||||
* The system clock should be a multiple of HZ * TIMERCLOCKSELECT (in
|
||||
|
|
|
|||
|
|
@ -35,11 +35,8 @@
|
|||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
# define __REG(x) (*((volatile u32 *)io_p2v((x))))
|
||||
# define __REG2(x, y) (*((volatile u32 *)io_p2v((x)) + (y)))
|
||||
|
||||
# define __REGB(x) (*((volatile u8 *)io_p2v((x))))
|
||||
# define __REGB2(x) (*((volatile u8 *)io_p2v((x)) + (y)))
|
||||
# define __REG(x) ((void __iomem __force *)io_p2v((x)))
|
||||
# define __REG2(x, y) ((void __iomem __force *)(io_p2v((x)) + 4 * (y)))
|
||||
|
||||
# define __REGSET(var, field, value) \
|
||||
((var) = (((var) & ~((field) & ~(value))) | (value)))
|
||||
|
|
@ -77,9 +74,6 @@
|
|||
# define __REG(x) io_p2v(x)
|
||||
# define __REG2(x, y) io_p2v((x) + (y))
|
||||
|
||||
# define __REGB(x) __REG((x))
|
||||
# define __REGB2(x, y) __REG2((x), (y))
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* ifndef __ASM_ARCH_HARDWARE_H */
|
||||
|
|
|
|||
|
|
@ -18,7 +18,7 @@
|
|||
#define FPGA_UARTC_BASE io_p2v(NS9XXX_CSxSTAT_PHYS(0) + 0x10)
|
||||
#define FPGA_UARTD_BASE io_p2v(NS9XXX_CSxSTAT_PHYS(0) + 0x18)
|
||||
|
||||
#define FPGA_IER __REGB(NS9XXX_CSxSTAT_PHYS(0) + 0x50)
|
||||
#define FPGA_ISR __REGB(NS9XXX_CSxSTAT_PHYS(0) + 0x60)
|
||||
#define FPGA_IER __REG(NS9XXX_CSxSTAT_PHYS(0) + 0x50)
|
||||
#define FPGA_ISR __REG(NS9XXX_CSxSTAT_PHYS(0) + 0x60)
|
||||
|
||||
#endif /* ifndef __ASM_ARCH_REGSBOARDA9M9750_H */
|
||||
|
|
|
|||
|
|
@ -24,9 +24,9 @@ static inline void arch_reset(char mode)
|
|||
{
|
||||
u32 reg;
|
||||
|
||||
reg = SYS_PLL >> 16;
|
||||
reg = __raw_readl(SYS_PLL) >> 16;
|
||||
REGSET(reg, SYS_PLL, SWC, YES);
|
||||
SYS_PLL = reg;
|
||||
__raw_writel(reg, SYS_PLL);
|
||||
|
||||
BUG();
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in a new issue