clk: tegra: fix pllre initilization
The PLLRE flags weren't set correctly. Fixed in this patch. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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1 changed files with 1 additions and 2 deletions
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@ -1409,7 +1409,7 @@ struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
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struct tegra_clk_pll *pll;
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struct clk *clk;
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pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
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pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_LOCK_MISC;
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pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
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freq_table, lock);
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if (IS_ERR(pll))
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@ -1436,7 +1436,6 @@ struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
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val &= ~BIT(29);
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pll_writel_misc(val, pll);
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pll_flags |= TEGRA_PLL_LOCK_MISC;
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clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
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&tegra_clk_pllre_ops);
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if (IS_ERR(clk))
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