mmc: sdhci-pxav3: Add base clock quirk
Enable the quirk SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN since SD_CAPABILITIES_1[15:8](BASE_FREQ) can't get correct base clock value. It returns a fixed pre-set value like 200 on some sdhci-pxav3 based platforms like MMP3 while return 0 on the other sdhci-pxav3 based platforms. So we enable the quirk and get the base clock via function get_max_clock. Also add get_max_clock. Reported-by: Philip Rakity <prakity@marvell.com> Reviewed-by: Philip Rakity <prakity@Marvell.com> Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com> Signed-off-by: Kevin Liu <kliu5@marvell.com> Signed-off-by: Chris Ball <cjb@laptop.org>
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1 changed files with 10 additions and 1 deletions
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@ -163,10 +163,18 @@ static int pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs)
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return 0;
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}
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static u32 pxav3_get_max_clock(struct sdhci_host *host)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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return clk_get_rate(pltfm_host->clk);
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}
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static struct sdhci_ops pxav3_sdhci_ops = {
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.platform_reset_exit = pxav3_set_private_registers,
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.set_uhs_signaling = pxav3_set_uhs_signaling,
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.platform_send_init_74_clocks = pxav3_gen_init_74_clocks,
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.get_max_clock = pxav3_get_max_clock,
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};
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#ifdef CONFIG_OF
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@ -249,7 +257,8 @@ static int __devinit sdhci_pxav3_probe(struct platform_device *pdev)
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host->quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
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| SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
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| SDHCI_QUIRK_32BIT_ADMA_SIZE;
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| SDHCI_QUIRK_32BIT_ADMA_SIZE
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| SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN;
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/* enable 1/8V DDR capable */
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host->mmc->caps |= MMC_CAP_1_8V_DDR;
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