ARM: 7298/1: realview: fix mapping of MPCore private memory region
Since commit 0536bdf33f
(ARM: move iotable mappings within
the vmalloc region), the RealView PB11MP cannot boot anymore.
This is caused by the way the mappings are described on this
platform (define replaced by hex values for clarity):
{ /* GIC CPU interface mapping */
.virtual = IO_ADDRESS(0x1F000100),
.pfn = __phys_to_pfn(0x1F000100),
.length = SZ_4K,
.type = MT_DEVICE,
}, { /* GIC distributor mapping */
.virtual = IO_ADDRESS(0x1F001000),
.pfn = __phys_to_pfn(0x1F001000),
.length = SZ_4K,
.type = MT_DEVICE,
}
The first mapping ends up reserving two pages, and clashes with
the second one, which triggers a BUG_ON in vm_area_add_early().
In order to solve this problem, treat the MPCore private memory
region (containing the SCU, the GIC and the TWD) as a single region,
as described in the TRM:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0360f/CACGDJJC.html
The EB11MP is converted the same way, even if it manages to avoid
the problem.
Tested on both PB11MP and EB11MP.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
parent
171cf94ccb
commit
34ae6c96a6
4 changed files with 19 additions and 25 deletions
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@ -47,21 +47,23 @@
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#define REALVIEW_EB_USB_BASE 0x4F000000 /* USB */
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#ifdef CONFIG_REALVIEW_EB_ARM11MP_REVB
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#define REALVIEW_EB11MP_SCU_BASE 0x10100000 /* SCU registers */
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#define REALVIEW_EB11MP_GIC_CPU_BASE 0x10100100 /* Generic interrupt controller CPU interface */
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#define REALVIEW_EB11MP_TWD_BASE 0x10100600
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#define REALVIEW_EB11MP_GIC_DIST_BASE 0x10101000 /* Generic interrupt controller distributor */
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#define REALVIEW_EB11MP_PRIV_MEM_BASE 0x1F000000
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#define REALVIEW_EB11MP_L220_BASE 0x10102000 /* L220 registers */
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#define REALVIEW_EB11MP_SYS_PLD_CTRL1 0xD8 /* Register offset for MPCore sysctl */
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#else
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#define REALVIEW_EB11MP_SCU_BASE 0x1F000000 /* SCU registers */
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#define REALVIEW_EB11MP_GIC_CPU_BASE 0x1F000100 /* Generic interrupt controller CPU interface */
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#define REALVIEW_EB11MP_TWD_BASE 0x1F000600
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#define REALVIEW_EB11MP_GIC_DIST_BASE 0x1F001000 /* Generic interrupt controller distributor */
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#define REALVIEW_EB11MP_PRIV_MEM_BASE 0x1F000000
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#define REALVIEW_EB11MP_L220_BASE 0x1F002000 /* L220 registers */
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#define REALVIEW_EB11MP_SYS_PLD_CTRL1 0x74 /* Register offset for MPCore sysctl */
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#endif
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#define REALVIEW_EB11MP_PRIV_MEM_SIZE SZ_8K
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#define REALVIEW_EB11MP_PRIV_MEM_OFF(x) (REALVIEW_EB11MP_PRIV_MEM_BASE + (x))
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#define REALVIEW_EB11MP_SCU_BASE REALVIEW_EB11MP_PRIV_MEM_OFF(0) /* SCU registers */
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#define REALVIEW_EB11MP_GIC_CPU_BASE REALVIEW_EB11MP_PRIV_MEM_OFF(0x0100) /* Generic interrupt controller CPU interface */
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#define REALVIEW_EB11MP_TWD_BASE REALVIEW_EB11MP_PRIV_MEM_OFF(0x0600)
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#define REALVIEW_EB11MP_GIC_DIST_BASE REALVIEW_EB11MP_PRIV_MEM_OFF(0x1000) /* Generic interrupt controller distributor */
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/*
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* Core tile identification (REALVIEW_SYS_PROCID)
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*/
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@ -75,6 +75,8 @@
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/*
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* Testchip peripheral and fpga gic regions
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*/
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#define REALVIEW_TC11MP_PRIV_MEM_BASE 0x1F000000
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#define REALVIEW_TC11MP_PRIV_MEM_SIZE SZ_8K
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#define REALVIEW_TC11MP_SCU_BASE 0x1F000000 /* IRQ, Test chip */
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#define REALVIEW_TC11MP_GIC_CPU_BASE 0x1F000100 /* Test chip interrupt controller CPU interface */
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#define REALVIEW_TC11MP_TWD_BASE 0x1F000600
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@ -91,14 +91,9 @@ static struct map_desc realview_eb_io_desc[] __initdata = {
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static struct map_desc realview_eb11mp_io_desc[] __initdata = {
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{
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.virtual = IO_ADDRESS(REALVIEW_EB11MP_SCU_BASE),
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.pfn = __phys_to_pfn(REALVIEW_EB11MP_SCU_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = IO_ADDRESS(REALVIEW_EB11MP_GIC_DIST_BASE),
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.pfn = __phys_to_pfn(REALVIEW_EB11MP_GIC_DIST_BASE),
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.length = SZ_4K,
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.virtual = IO_ADDRESS(REALVIEW_EB11MP_PRIV_MEM_BASE),
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.pfn = __phys_to_pfn(REALVIEW_EB11MP_PRIV_MEM_BASE),
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.length = REALVIEW_EB11MP_PRIV_MEM_SIZE,
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.type = MT_DEVICE,
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}, {
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.virtual = IO_ADDRESS(REALVIEW_EB11MP_L220_BASE),
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@ -64,15 +64,10 @@ static struct map_desc realview_pb11mp_io_desc[] __initdata = {
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.pfn = __phys_to_pfn(REALVIEW_PB11MP_GIC_DIST_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = IO_ADDRESS(REALVIEW_TC11MP_GIC_CPU_BASE),
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.pfn = __phys_to_pfn(REALVIEW_TC11MP_GIC_CPU_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = IO_ADDRESS(REALVIEW_TC11MP_GIC_DIST_BASE),
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.pfn = __phys_to_pfn(REALVIEW_TC11MP_GIC_DIST_BASE),
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.length = SZ_4K,
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}, { /* Maps the SCU, GIC CPU interface, TWD, GIC DIST */
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.virtual = IO_ADDRESS(REALVIEW_TC11MP_PRIV_MEM_BASE),
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.pfn = __phys_to_pfn(REALVIEW_TC11MP_PRIV_MEM_BASE),
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.length = REALVIEW_TC11MP_PRIV_MEM_SIZE,
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.type = MT_DEVICE,
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}, {
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.virtual = IO_ADDRESS(REALVIEW_SCTL_BASE),
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