Gross macro abuse. Get rid of gpreg_t, vaddr_t, REG_TO_VA and
VA_TO_REG. Who ever wrote this apparently did enjoy the C Puzzle Book. ISBN 0201604612, a little old but still fun reading for the next blackout ;) Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle
parent
0bd5d2e9ec
commit
333d1f6794
3 changed files with 31 additions and 37 deletions
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@ -196,7 +196,7 @@ static int isBranchInstr(mips_instruction * i)
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static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx)
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{
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mips_instruction ir;
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vaddr_t emulpc, contpc;
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void * emulpc, *contpc;
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unsigned int cond;
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if (get_user(ir, (mips_instruction *) xcp->cp0_epc)) {
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@ -221,12 +221,12 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx)
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* Linux MIPS branch emulator operates on context, updating the
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* cp0_epc.
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*/
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emulpc = REG_TO_VA(xcp->cp0_epc + 4); /* Snapshot emulation target */
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emulpc = (void *) (xcp->cp0_epc + 4); /* Snapshot emulation target */
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if (__compute_return_epc(xcp)) {
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#ifdef CP1DBG
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printk("failed to emulate branch at %p\n",
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REG_TO_VA(xcp->cp0_epc));
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(void *) (xcp->cp0_epc));
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#endif
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return SIGILL;
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}
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@ -235,13 +235,12 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx)
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return SIGBUS;
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}
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/* __compute_return_epc() will have updated cp0_epc */
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contpc = REG_TO_VA xcp->cp0_epc;
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contpc = (void *) xcp->cp0_epc;
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/* In order not to confuse ptrace() et al, tweak context */
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xcp->cp0_epc = VA_TO_REG emulpc - 4;
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}
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else {
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emulpc = REG_TO_VA xcp->cp0_epc;
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contpc = REG_TO_VA(xcp->cp0_epc + 4);
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xcp->cp0_epc = (unsigned long) emulpc - 4;
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} else {
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emulpc = (void *) xcp->cp0_epc;
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contpc = (void *) (xcp->cp0_epc + 4);
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}
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emul:
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@ -249,7 +248,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx)
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switch (MIPSInst_OPCODE(ir)) {
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#ifndef SINGLE_ONLY_FPU
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case ldc1_op:{
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u64 *va = REG_TO_VA(xcp->regs[MIPSInst_RS(ir)] +
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u64 *va = (void *) (xcp->regs[MIPSInst_RS(ir)] +
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MIPSInst_SIMM(ir));
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u64 val;
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@ -263,7 +262,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx)
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}
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case sdc1_op:{
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u64 *va = REG_TO_VA(xcp->regs[MIPSInst_RS(ir)] +
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u64 *va = (void *) (xcp->regs[MIPSInst_RS(ir)] +
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MIPSInst_SIMM(ir));
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u64 val;
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@ -278,7 +277,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx)
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#endif
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case lwc1_op:{
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u32 *va = REG_TO_VA(xcp->regs[MIPSInst_RS(ir)] +
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u32 *va = (void *) (xcp->regs[MIPSInst_RS(ir)] +
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MIPSInst_SIMM(ir));
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u32 val;
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@ -298,7 +297,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx)
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}
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case swc1_op:{
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u32 *va = REG_TO_VA(xcp->regs[MIPSInst_RS(ir)] +
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u32 *va = (void *) (xcp->regs[MIPSInst_RS(ir)] +
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MIPSInst_SIMM(ir));
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u32 val;
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@ -371,7 +370,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx)
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value = ctx->fcr31;
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#ifdef CSRTRACE
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printk("%p gpr[%d]<-csr=%08x\n",
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REG_TO_VA(xcp->cp0_epc),
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(void *) (xcp->cp0_epc),
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MIPSInst_RT(ir), value);
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#endif
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}
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@ -398,7 +397,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx)
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if (MIPSInst_RD(ir) == FPCREG_CSR) {
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#ifdef CSRTRACE
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printk("%p gpr[%d]->csr=%08x\n",
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REG_TO_VA(xcp->cp0_epc),
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(void *) (xcp->cp0_epc),
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MIPSInst_RT(ir), value);
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#endif
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ctx->fcr31 = value;
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@ -445,12 +444,12 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx)
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* instruction
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*/
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xcp->cp0_epc += 4;
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contpc = REG_TO_VA
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contpc = (void *)
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(xcp->cp0_epc +
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(MIPSInst_SIMM(ir) << 2));
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if (get_user(ir, (mips_instruction *)
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REG_TO_VA xcp->cp0_epc)) {
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(void *) xcp->cp0_epc)) {
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fpuemuprivate.stats.errors++;
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return SIGBUS;
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}
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@ -480,7 +479,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx)
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* Single step the non-cp1
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* instruction in the dslot
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*/
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return mips_dsemul(xcp, ir, VA_TO_REG contpc);
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return mips_dsemul(xcp, ir, (unsigned long) contpc);
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}
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else {
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/* branch not taken */
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@ -539,8 +538,9 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx)
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}
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/* we did it !! */
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xcp->cp0_epc = VA_TO_REG(contpc);
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xcp->cp0_epc = (unsigned long) contpc;
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xcp->cp0_cause &= ~CAUSEF_BD;
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return 0;
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}
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@ -628,7 +628,7 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
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switch (MIPSInst_FUNC(ir)) {
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case lwxc1_op:
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va = REG_TO_VA(xcp->regs[MIPSInst_FR(ir)] +
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va = (void *) (xcp->regs[MIPSInst_FR(ir)] +
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xcp->regs[MIPSInst_FT(ir)]);
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fpuemuprivate.stats.loads++;
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@ -648,7 +648,7 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
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break;
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case swxc1_op:
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va = REG_TO_VA(xcp->regs[MIPSInst_FR(ir)] +
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va = (void *) (xcp->regs[MIPSInst_FR(ir)] +
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xcp->regs[MIPSInst_FT(ir)]);
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fpuemuprivate.stats.stores++;
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@ -724,7 +724,7 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
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switch (MIPSInst_FUNC(ir)) {
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case ldxc1_op:
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va = REG_TO_VA(xcp->regs[MIPSInst_FR(ir)] +
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va = (void *) (xcp->regs[MIPSInst_FR(ir)] +
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xcp->regs[MIPSInst_FT(ir)]);
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fpuemuprivate.stats.loads++;
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@ -736,7 +736,7 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
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break;
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case sdxc1_op:
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va = REG_TO_VA(xcp->regs[MIPSInst_FR(ir)] +
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va = (void *) (xcp->regs[MIPSInst_FR(ir)] +
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xcp->regs[MIPSInst_FT(ir)]);
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fpuemuprivate.stats.stores++;
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@ -1282,7 +1282,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
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int fpu_emulator_cop1Handler(int xcptno, struct pt_regs *xcp,
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struct mips_fpu_soft_struct *ctx)
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{
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gpreg_t oldepc, prevepc;
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unsigned long oldepc, prevepc;
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mips_instruction insn;
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int sig = 0;
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@ -49,10 +49,10 @@ struct emuframe {
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mips_instruction emul;
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mips_instruction badinst;
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mips_instruction cookie;
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gpreg_t epc;
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unsigned long epc;
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};
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int mips_dsemul(struct pt_regs *regs, mips_instruction ir, gpreg_t cpc)
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int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc)
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{
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extern asmlinkage void handle_dsemulret(void);
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mips_instruction *dsemul_insns;
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@ -88,7 +88,7 @@ int mips_dsemul(struct pt_regs *regs, mips_instruction ir, gpreg_t cpc)
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*/
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/* Ensure that the two instructions are in the same cache line */
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dsemul_insns = (mips_instruction *) REG_TO_VA ((regs->regs[29] - sizeof(struct emuframe)) & ~0x7);
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dsemul_insns = (mips_instruction *) ((regs->regs[29] - sizeof(struct emuframe)) & ~0x7);
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fr = (struct emuframe *) dsemul_insns;
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/* Verify that the stack pointer is not competely insane */
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@ -105,7 +105,7 @@ int mips_dsemul(struct pt_regs *regs, mips_instruction ir, gpreg_t cpc)
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return SIGBUS;
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}
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regs->cp0_epc = VA_TO_REG & fr->emul;
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regs->cp0_epc = (unsigned long) &fr->emul;
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flush_cache_sigtramp((unsigned long)&fr->badinst);
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@ -115,7 +115,7 @@ int mips_dsemul(struct pt_regs *regs, mips_instruction ir, gpreg_t cpc)
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int do_dsemulret(struct pt_regs *xcp)
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{
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struct emuframe *fr;
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gpreg_t epc;
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unsigned long epc;
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u32 insn, cookie;
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int err = 0;
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@ -1,11 +1,5 @@
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typedef long gpreg_t;
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typedef void *vaddr_t;
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#define REG_TO_VA (vaddr_t)
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#define VA_TO_REG (gpreg_t)
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int mips_dsemul(struct pt_regs *regs, mips_instruction ir, gpreg_t cpc);
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int do_dsemulret(struct pt_regs *xcp);
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extern int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc);
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extern int do_dsemulret(struct pt_regs *xcp);
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/* Instruction which will always cause an address error */
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#define AdELOAD 0x8c000001 /* lw $0,1($0) */
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