Revert "cxl: Add cxl_slot_is_supported API"
Remove abandonned capi support for the Mellanox CX4.
This reverts commit 4e56f858bd
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Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Acked-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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2 changed files with 0 additions and 52 deletions
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@ -1808,43 +1808,6 @@ int cxl_slot_is_switched(struct pci_dev *dev)
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return (depth > CXL_MAX_PCIEX_PARENT);
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}
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bool cxl_slot_is_supported(struct pci_dev *dev, int flags)
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{
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if (!cpu_has_feature(CPU_FTR_HVMODE))
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return false;
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if ((flags & CXL_SLOT_FLAG_DMA) && (!pvr_version_is(PVR_POWER8NVL))) {
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/*
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* CAPP DMA mode is technically supported on regular P8, but
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* will EEH if the card attempts to access memory < 4GB, which
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* we cannot realistically avoid. We might be able to work
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* around the issue, but until then return unsupported:
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*/
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return false;
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}
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if (cxl_slot_is_switched(dev))
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return false;
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/*
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* XXX: This gets a little tricky on regular P8 (not POWER8NVL) since
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* the CAPP can be connected to PHB 0, 1 or 2 on a first come first
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* served basis, which is racy to check from here. If we need to
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* support this in future we might need to consider having this
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* function effectively reserve it ahead of time.
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*
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* Currently, the only user of this API is the Mellanox CX4, which is
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* only supported on P8NVL due to the above mentioned limitation of
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* CAPP DMA mode and therefore does not need to worry about this. If the
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* issue with CAPP DMA mode is later worked around on P8 we might need
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* to revisit this.
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*/
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return true;
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}
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EXPORT_SYMBOL_GPL(cxl_slot_is_supported);
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static int cxl_probe(struct pci_dev *dev, const struct pci_device_id *id)
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{
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struct cxl *adapter;
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@ -24,21 +24,6 @@
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* generic PCI API. This API is agnostic to the actual AFU.
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*/
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#define CXL_SLOT_FLAG_DMA 0x1
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/*
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* Checks if the given card is in a cxl capable slot. Pass CXL_SLOT_FLAG_DMA if
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* the card requires CAPP DMA mode to also check if the system supports it.
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* This is intended to be used by bi-modal devices to determine if they can use
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* cxl mode or if they should continue running in PCI mode.
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*
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* Note that this only checks if the slot is cxl capable - it does not
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* currently check if the CAPP is currently available for chips where it can be
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* assigned to different PHBs on a first come first serve basis (i.e. P8)
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*/
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bool cxl_slot_is_supported(struct pci_dev *dev, int flags);
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/* Get the AFU associated with a pci_dev */
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struct cxl_afu *cxl_pci_to_afu(struct pci_dev *dev);
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