ARM: sa11x0/pxa: convert OS timer registers to IOMEM
Make the OS timer registers have IOMEM like properities so they can be passed to readl_relaxed/writel_relaxed() et.al. rather than being straight volatile dereferences. Add linux/io.h includes where required. linux/io.h includes added to arch/arm/mach-sa1100/cpu-sa1100.c, arch/arm/mach-sa1100/jornada720_ssp.c, arch/arm/mach-sa1100/leds-lart.c drivers/input/touchscreen/jornada720_ts.c, drivers/pcmcia/sa1100_shannon.c from Arnd. This fixes these warnings: arch/arm/mach-sa1100/time.c: In function 'sa1100_timer_init': arch/arm/mach-sa1100/time.c:104: warning: passing argument 1 of 'clocksource_mmio_init' discards qualifiers from pointer target type arch/arm/mach-pxa/time.c: In function 'pxa_timer_init': arch/arm/mach-pxa/time.c:126: warning: passing argument 1 of 'clocksource_mmio_init' discards qualifiers from pointer target type Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
parent
bcccc50ce8
commit
3169663ac5
19 changed files with 97 additions and 82 deletions
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@ -7,17 +7,17 @@
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* OS Timer & Match Registers
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*/
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#define OSMR0 __REG(0x40A00000) /* */
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#define OSMR1 __REG(0x40A00004) /* */
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#define OSMR2 __REG(0x40A00008) /* */
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#define OSMR3 __REG(0x40A0000C) /* */
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#define OSMR4 __REG(0x40A00080) /* */
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#define OSCR __REG(0x40A00010) /* OS Timer Counter Register */
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#define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register */
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#define OMCR4 __REG(0x40A000C0) /* */
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#define OSSR __REG(0x40A00014) /* OS Timer Status Register */
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#define OWER __REG(0x40A00018) /* OS Timer Watchdog Enable Register */
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#define OIER __REG(0x40A0001C) /* OS Timer Interrupt Enable Register */
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#define OSMR0 io_p2v(0x40A00000) /* */
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#define OSMR1 io_p2v(0x40A00004) /* */
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#define OSMR2 io_p2v(0x40A00008) /* */
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#define OSMR3 io_p2v(0x40A0000C) /* */
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#define OSMR4 io_p2v(0x40A00080) /* */
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#define OSCR io_p2v(0x40A00010) /* OS Timer Counter Register */
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#define OSCR4 io_p2v(0x40A00040) /* OS Timer Counter Register */
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#define OMCR4 io_p2v(0x40A000C0) /* */
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#define OSSR io_p2v(0x40A00014) /* OS Timer Status Register */
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#define OWER io_p2v(0x40A00018) /* OS Timer Watchdog Enable Register */
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#define OIER io_p2v(0x40A0001C) /* OS Timer Interrupt Enable Register */
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#define OSSR_M3 (1 << 3) /* Match status channel 3 */
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#define OSSR_M2 (1 << 2) /* Match status channel 2 */
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@ -77,9 +77,10 @@ static void do_gpio_reset(void)
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static void do_hw_reset(void)
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{
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/* Initialize the watchdog and let it fire */
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OWER = OWER_WME;
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OSSR = OSSR_M3;
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OSMR3 = OSCR + 368640; /* ... in 100 ms */
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writel_relaxed(OWER_WME, OWER);
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writel_relaxed(OSSR_M3, OSSR);
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/* ... in 100 ms */
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writel_relaxed(readl_relaxed(OSCR) + 368640, OSMR3);
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}
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void pxa_restart(char mode, const char *cmd)
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@ -35,7 +35,7 @@
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static u32 notrace pxa_read_sched_clock(void)
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{
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return OSCR;
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return readl_relaxed(OSCR);
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}
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@ -47,8 +47,8 @@ pxa_ost0_interrupt(int irq, void *dev_id)
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struct clock_event_device *c = dev_id;
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/* Disarm the compare/match, signal the event. */
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OIER &= ~OIER_E0;
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OSSR = OSSR_M0;
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writel_relaxed(readl_relaxed(OIER) & ~OIER_E0, OIER);
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writel_relaxed(OSSR_M0, OSSR);
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c->event_handler(c);
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return IRQ_HANDLED;
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@ -59,10 +59,10 @@ pxa_osmr0_set_next_event(unsigned long delta, struct clock_event_device *dev)
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{
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unsigned long next, oscr;
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OIER |= OIER_E0;
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next = OSCR + delta;
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OSMR0 = next;
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oscr = OSCR;
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writel_relaxed(readl_relaxed(OIER) | OIER_E0, OIER);
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next = readl_relaxed(OSCR) + delta;
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writel_relaxed(next, OSMR0);
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oscr = readl_relaxed(OSCR);
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return (signed)(next - oscr) <= MIN_OSCR_DELTA ? -ETIME : 0;
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}
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@ -72,15 +72,15 @@ pxa_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *dev)
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{
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switch (mode) {
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case CLOCK_EVT_MODE_ONESHOT:
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OIER &= ~OIER_E0;
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OSSR = OSSR_M0;
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writel_relaxed(readl_relaxed(OIER) & ~OIER_E0, OIER);
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writel_relaxed(OSSR_M0, OSSR);
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break;
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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/* initializing, released, or preparing for suspend */
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OIER &= ~OIER_E0;
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OSSR = OSSR_M0;
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writel_relaxed(readl_relaxed(OIER) & ~OIER_E0, OIER);
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writel_relaxed(OSSR_M0, OSSR);
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break;
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case CLOCK_EVT_MODE_RESUME:
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@ -108,8 +108,8 @@ static void __init pxa_timer_init(void)
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{
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unsigned long clock_tick_rate = get_clock_tick_rate();
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OIER = 0;
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OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3;
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writel_relaxed(0, OIER);
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writel_relaxed(OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3, OSSR);
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setup_sched_clock(pxa_read_sched_clock, 32, clock_tick_rate);
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@ -122,7 +122,7 @@ static void __init pxa_timer_init(void)
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setup_irq(IRQ_OST0, &pxa_ost0_irq);
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clocksource_mmio_init(&OSCR, "oscr0", clock_tick_rate, 200, 32,
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clocksource_mmio_init(OSCR, "oscr0", clock_tick_rate, 200, 32,
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clocksource_mmio_readl_up);
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clockevents_register_device(&ckevt_pxa_osmr0);
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}
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@ -132,12 +132,12 @@ static unsigned long osmr[4], oier, oscr;
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static void pxa_timer_suspend(void)
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{
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osmr[0] = OSMR0;
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osmr[1] = OSMR1;
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osmr[2] = OSMR2;
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osmr[3] = OSMR3;
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oier = OIER;
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oscr = OSCR;
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osmr[0] = readl_relaxed(OSMR0);
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osmr[1] = readl_relaxed(OSMR1);
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osmr[2] = readl_relaxed(OSMR2);
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osmr[3] = readl_relaxed(OSMR3);
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oier = readl_relaxed(OIER);
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oscr = readl_relaxed(OSCR);
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}
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static void pxa_timer_resume(void)
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@ -151,12 +151,12 @@ static void pxa_timer_resume(void)
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if (osmr[0] - oscr < MIN_OSCR_DELTA)
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osmr[0] += MIN_OSCR_DELTA;
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OSMR0 = osmr[0];
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OSMR1 = osmr[1];
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OSMR2 = osmr[2];
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OSMR3 = osmr[3];
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OIER = oier;
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OSCR = oscr;
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writel_relaxed(osmr[0], OSMR0);
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writel_relaxed(osmr[1], OSMR1);
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writel_relaxed(osmr[2], OSMR2);
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writel_relaxed(osmr[3], OSMR3);
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writel_relaxed(oier, OIER);
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writel_relaxed(oscr, OSCR);
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}
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#else
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#define pxa_timer_suspend NULL
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@ -362,7 +362,7 @@ static void __init assabet_init(void)
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static void __init map_sa1100_gpio_regs( void )
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{
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unsigned long phys = __PREG(GPLR) & PMD_MASK;
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unsigned long virt = io_p2v(phys);
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unsigned long virt = (unsigned long)io_p2v(phys);
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int prot = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_DOMAIN(DOMAIN_IO);
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pmd_t *pmd;
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@ -87,6 +87,7 @@
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/cpufreq.h>
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#include <linux/io.h>
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#include <asm/cputype.h>
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@ -19,6 +19,7 @@
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#include <linux/cpufreq.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/moduleparam.h>
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#include <linux/types.h>
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@ -830,14 +830,14 @@
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* (read/write).
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*/
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#define OSMR0 __REG(0x90000000) /* OS timer Match Reg. 0 */
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#define OSMR1 __REG(0x90000004) /* OS timer Match Reg. 1 */
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#define OSMR2 __REG(0x90000008) /* OS timer Match Reg. 2 */
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#define OSMR3 __REG(0x9000000c) /* OS timer Match Reg. 3 */
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#define OSCR __REG(0x90000010) /* OS timer Counter Reg. */
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#define OSSR __REG(0x90000014 ) /* OS timer Status Reg. */
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#define OWER __REG(0x90000018 ) /* OS timer Watch-dog Enable Reg. */
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#define OIER __REG(0x9000001C ) /* OS timer Interrupt Enable Reg. */
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#define OSMR0 io_p2v(0x90000000) /* OS timer Match Reg. 0 */
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#define OSMR1 io_p2v(0x90000004) /* OS timer Match Reg. 1 */
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#define OSMR2 io_p2v(0x90000008) /* OS timer Match Reg. 2 */
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#define OSMR3 io_p2v(0x9000000c) /* OS timer Match Reg. 3 */
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#define OSCR io_p2v(0x90000010) /* OS timer Counter Reg. */
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#define OSSR io_p2v(0x90000014) /* OS timer Status Reg. */
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#define OWER io_p2v(0x90000018) /* OS timer Watch-dog Enable Reg. */
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#define OIER io_p2v(0x9000001C) /* OS timer Interrupt Enable Reg. */
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#define OSSR_M(Nb) /* Match detected [0..3] */ \
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(0x00000001 << (Nb))
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@ -24,6 +24,7 @@
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#ifndef __ASM_ARCH_SA1100_GPIO_H
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#define __ASM_ARCH_SA1100_GPIO_H
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#include <linux/io.h>
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#include <mach/hardware.h>
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#include <asm/irq.h>
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#include <asm-generic/gpio.h>
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@ -32,7 +32,7 @@
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#define PIO_START 0x80000000 /* physical start of IO space */
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#define io_p2v( x ) \
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( (((x)&0x00ffffff) | (((x)&0x30000000)>>VIO_SHIFT)) + VIO_BASE )
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IOMEM( (((x)&0x00ffffff) | (((x)&0x30000000)>>VIO_SHIFT)) + VIO_BASE )
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#define io_v2p( x ) \
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( (((x)&0x00ffffff) | (((x)&(0x30000000>>VIO_SHIFT))<<VIO_SHIFT)) + PIO_START )
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#define CPU_SA1110_ID (0x6901b110)
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#define CPU_SA1110_MASK (0xfffffff0)
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#define __MREG(x) IOMEM(io_p2v(x))
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#ifndef __ASSEMBLY__
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#include <asm/cputype.h>
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#define cpu_is_sa1100() ((read_cpuid_id() & CPU_SA1100_MASK) == CPU_SA1100_ID)
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#define cpu_is_sa1110() ((read_cpuid_id() & CPU_SA1110_MASK) == CPU_SA1110_ID)
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# define __REG(x) (*((volatile unsigned long *)io_p2v(x)))
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# define __REG(x) (*((volatile unsigned long __iomem *)io_p2v(x)))
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# define __PREG(x) (io_v2p((unsigned long)&(x)))
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static inline unsigned long get_clock_tick_rate(void)
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@ -8,6 +8,8 @@
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#include "hardware.h"
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#define IOMEM(x) (x)
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/*
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* The following code assumes the serial port has already been
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* initialized by the bootloader. We search for the first enabled
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@ -12,6 +12,7 @@
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/ioport.h>
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#include <linux/syscore_ops.h>
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@ -18,6 +18,7 @@
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/sched.h>
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#include <linux/io.h>
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#include <mach/hardware.h>
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#include <mach/jornada720.h>
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@ -4,6 +4,7 @@
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* Author: ???
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*/
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#include <linux/init.h>
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#include <linux/io.h>
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#include <mach/hardware.h>
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#include <asm/leds.h>
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@ -10,6 +10,7 @@
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* pace of the LED.
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*/
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#include <linux/init.h>
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#include <linux/io.h>
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#include <mach/hardware.h>
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#include <asm/leds.h>
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* Storage is local on the stack now.
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*/
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/suspend.h>
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#include <linux/errno.h>
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#include <linux/time.h>
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static u32 notrace sa1100_read_sched_clock(void)
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{
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return OSCR;
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return readl_relaxed(OSCR);
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}
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#define MIN_OSCR_DELTA 2
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struct clock_event_device *c = dev_id;
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/* Disarm the compare/match, signal the event. */
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OIER &= ~OIER_E0;
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OSSR = OSSR_M0;
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writel_relaxed(readl_relaxed(OIER) & ~OIER_E0, OIER);
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writel_relaxed(OSSR_M0, OSSR);
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c->event_handler(c);
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return IRQ_HANDLED;
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{
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unsigned long next, oscr;
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OIER |= OIER_E0;
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next = OSCR + delta;
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OSMR0 = next;
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oscr = OSCR;
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writel_relaxed(readl_relaxed(OIER) | OIER_E0, OIER);
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next = readl_relaxed(OSCR) + delta;
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writel_relaxed(next, OSMR0);
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oscr = readl_relaxed(OSCR);
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return (signed)(next - oscr) <= MIN_OSCR_DELTA ? -ETIME : 0;
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}
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@ -59,8 +59,8 @@ sa1100_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *c)
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case CLOCK_EVT_MODE_ONESHOT:
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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OIER &= ~OIER_E0;
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OSSR = OSSR_M0;
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writel_relaxed(readl_relaxed(OIER) & ~OIER_E0, OIER);
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writel_relaxed(OSSR_M0, OSSR);
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break;
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case CLOCK_EVT_MODE_RESUME:
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@ -86,8 +86,8 @@ static struct irqaction sa1100_timer_irq = {
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static void __init sa1100_timer_init(void)
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{
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OIER = 0;
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OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3;
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writel_relaxed(0, OIER);
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writel_relaxed(OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3, OSSR);
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setup_sched_clock(sa1100_read_sched_clock, 32, 3686400);
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@ -100,7 +100,7 @@ static void __init sa1100_timer_init(void)
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setup_irq(IRQ_OST0, &sa1100_timer_irq);
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clocksource_mmio_init(&OSCR, "oscr", CLOCK_TICK_RATE, 200, 32,
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clocksource_mmio_init(OSCR, "oscr", CLOCK_TICK_RATE, 200, 32,
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clocksource_mmio_readl_up);
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clockevents_register_device(&ckevt_sa1100_osmr0);
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}
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@ -110,26 +110,26 @@ unsigned long osmr[4], oier;
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static void sa1100_timer_suspend(void)
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{
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osmr[0] = OSMR0;
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osmr[1] = OSMR1;
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osmr[2] = OSMR2;
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osmr[3] = OSMR3;
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oier = OIER;
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osmr[0] = readl_relaxed(OSMR0);
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osmr[1] = readl_relaxed(OSMR1);
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osmr[2] = readl_relaxed(OSMR2);
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osmr[3] = readl_relaxed(OSMR3);
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oier = readl_relaxed(OIER);
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}
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static void sa1100_timer_resume(void)
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{
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OSSR = 0x0f;
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OSMR0 = osmr[0];
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OSMR1 = osmr[1];
|
||||
OSMR2 = osmr[2];
|
||||
OSMR3 = osmr[3];
|
||||
OIER = oier;
|
||||
writel_relaxed(0x0f, OSSR);
|
||||
writel_relaxed(osmr[0], OSMR0);
|
||||
writel_relaxed(osmr[1], OSMR1);
|
||||
writel_relaxed(osmr[2], OSMR2);
|
||||
writel_relaxed(osmr[3], OSMR3);
|
||||
writel_relaxed(oier, OIER);
|
||||
|
||||
/*
|
||||
* OSMR0 is the system timer: make sure OSCR is sufficiently behind
|
||||
*/
|
||||
OSCR = OSMR0 - LATCH;
|
||||
writel_relaxed(OSMR0 - LATCH, OSCR);
|
||||
}
|
||||
#else
|
||||
#define sa1100_timer_suspend NULL
|
||||
|
|
|
@ -19,6 +19,7 @@
|
|||
#include <linux/interrupt.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/jornada720.h>
|
||||
|
|
|
@ -8,6 +8,7 @@
|
|||
#include <linux/kernel.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <asm/mach-types.h>
|
||||
|
|
|
@ -54,10 +54,10 @@ static int sa1100dog_open(struct inode *inode, struct file *file)
|
|||
return -EBUSY;
|
||||
|
||||
/* Activate SA1100 Watchdog timer */
|
||||
OSMR3 = OSCR + pre_margin;
|
||||
OSSR = OSSR_M3;
|
||||
OWER = OWER_WME;
|
||||
OIER |= OIER_E3;
|
||||
writel_relaxed(readl_relaxed(OSCR) + pre_margin, OSMR3);
|
||||
writel_relaxed(OSSR_M3, OSSR);
|
||||
writel_relaxed(OWER_WME, OWER);
|
||||
writel_relaxed(readl_relaxed(OIER) | OIER_E3, OIER);
|
||||
return nonseekable_open(inode, file);
|
||||
}
|
||||
|
||||
|
@ -80,7 +80,7 @@ static ssize_t sa1100dog_write(struct file *file, const char __user *data,
|
|||
{
|
||||
if (len)
|
||||
/* Refresh OSMR3 timer. */
|
||||
OSMR3 = OSCR + pre_margin;
|
||||
writel_relaxed(readl_relaxed(OSCR) + pre_margin, OSMR3);
|
||||
return len;
|
||||
}
|
||||
|
||||
|
@ -114,7 +114,7 @@ static long sa1100dog_ioctl(struct file *file, unsigned int cmd,
|
|||
break;
|
||||
|
||||
case WDIOC_KEEPALIVE:
|
||||
OSMR3 = OSCR + pre_margin;
|
||||
writel_relaxed(readl_relaxed(OSCR) + pre_margin, OSMR3);
|
||||
ret = 0;
|
||||
break;
|
||||
|
||||
|
@ -129,7 +129,7 @@ static long sa1100dog_ioctl(struct file *file, unsigned int cmd,
|
|||
}
|
||||
|
||||
pre_margin = oscr_freq * time;
|
||||
OSMR3 = OSCR + pre_margin;
|
||||
writel_relaxed(readl_relaxed(OSCR) + pre_margin, OSMR3);
|
||||
/*fall through*/
|
||||
|
||||
case WDIOC_GETTIMEOUT:
|
||||
|
|
Loading…
Reference in a new issue