x86, hpet: Restrict read back to affected ATI chipsets
After programming the HPET, we do a readback as a workaround for ATI/SBx00 chipsets as a synchronization. Unfortunately this triggers an erratum in newer ICH chipsets (ICH9+) where reading the comparator immediately after the write returns the old value. Furthermore, as always, I/O reads are bad for performance. Therefore, restrict the readback to the chipsets that need it, or, for debugging purposes, when we are running with hpet=verbose. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Venkatesh Pallipadi <venki@google.com> LKML-Reference: <20100225185348.GA9674@linux-os.sc.intel.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
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3 changed files with 23 additions and 12 deletions
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@ -68,6 +68,7 @@ extern unsigned long force_hpet_address;
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extern u8 hpet_blockid;
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extern u8 hpet_blockid;
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extern int hpet_force_user;
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extern int hpet_force_user;
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extern u8 hpet_msi_disable;
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extern u8 hpet_msi_disable;
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extern u8 hpet_readback_cmp;
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extern int is_hpet_enabled(void);
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extern int is_hpet_enabled(void);
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extern int hpet_enable(void);
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extern int hpet_enable(void);
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extern void hpet_disable(void);
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extern void hpet_disable(void);
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@ -36,6 +36,7 @@
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unsigned long hpet_address;
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unsigned long hpet_address;
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u8 hpet_blockid; /* OS timer block num */
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u8 hpet_blockid; /* OS timer block num */
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u8 hpet_msi_disable;
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u8 hpet_msi_disable;
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u8 hpet_readback_cmp;
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#ifdef CONFIG_PCI_MSI
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#ifdef CONFIG_PCI_MSI
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static unsigned long hpet_num_timers;
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static unsigned long hpet_num_timers;
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@ -395,19 +396,23 @@ static int hpet_next_event(unsigned long delta,
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* at that point and we would wait for the next hpet interrupt
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* at that point and we would wait for the next hpet interrupt
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* forever. We found out that reading the CMP register back
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* forever. We found out that reading the CMP register back
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* forces the transfer so we can rely on the comparison with
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* forces the transfer so we can rely on the comparison with
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* the counter register below. If the read back from the
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* the counter register below.
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* compare register does not match the value we programmed
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*
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* then we might have a real hardware problem. We can not do
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* That works fine on those ATI chipsets, but on newer Intel
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* much about it here, but at least alert the user/admin with
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* chipsets (ICH9...) this triggers due to an erratum: Reading
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* a prominent warning.
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* the comparator immediately following a write is returning
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* An erratum on some chipsets (ICH9,..), results in comparator read
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* the old value.
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* immediately following a write returning old value. Workaround
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*
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* for this is to read this value second time, when first
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* We restrict the read back to the affected ATI chipsets (set
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* read returns old value.
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* by quirks) and also run it with hpet=verbose for debugging
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* purposes.
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*/
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*/
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if (unlikely((u32)hpet_readl(HPET_Tn_CMP(timer)) != cnt)) {
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if (hpet_readback_cmp || hpet_verbose) {
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WARN_ONCE(hpet_readl(HPET_Tn_CMP(timer)) != cnt,
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u32 cmp = hpet_readl(HPET_Tn_CMP(timer));
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KERN_WARNING "hpet: compare register read back failed.\n");
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if (cmp != cnt)
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printk_once(KERN_WARNING
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"hpet: compare register read back failed.\n");
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}
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}
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return (s32)(hpet_readl(HPET_COUNTER) - cnt) >= 0 ? -ETIME : 0;
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return (s32)(hpet_readl(HPET_COUNTER) - cnt) >= 0 ? -ETIME : 0;
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@ -495,10 +495,15 @@ void force_hpet_resume(void)
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/*
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/*
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* HPET MSI on some boards (ATI SB700/SB800) has side effect on
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* HPET MSI on some boards (ATI SB700/SB800) has side effect on
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* floppy DMA. Disable HPET MSI on such platforms.
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* floppy DMA. Disable HPET MSI on such platforms.
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*
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* Also force the read back of the CMP register in hpet_next_event()
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* to work around the problem that the CMP register write seems to be
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* delayed. See hpet_next_event() for details.
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*/
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*/
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static void force_disable_hpet_msi(struct pci_dev *unused)
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static void force_disable_hpet_msi(struct pci_dev *unused)
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{
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{
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hpet_msi_disable = 1;
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hpet_msi_disable = 1;
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hpet_readback_cmp = 1;
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}
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
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