cxgb4: DB Drop Recovery for RDMA and LLD queues
recover LLD EQs for DB drop interrupts. This includes adding a new db_lock, a spin lock disabling BH too, used by the recovery thread and the ring_tx_db() paths to allow db drop recovery. Clean up initial DB avoidance code. Add read_eq_indices() - this allows the LLD to use the PCIe mw to efficiently read hw eq contexts. Add cxgb4_sync_txq_pidx() - called by iw_cxgb4 to sync up the sw/hw pidx value. Add flush_eq_cache() and cxgb4_flush_eq_cache(). This allows iw_cxgb4 to flush the sge eq context cache before beginning db drop recovery. Add module parameter, dbfoifo_int_thresh, to allow tuning the db interrupt threshold value. Add dbfifo_int_thresh to cxgb4_lld_info so iw_cxgb4 knows the threshold. Add module parameter, dbfoifo_drain_delay, to allow tuning the amount of time delay between DB FULL and EMPTY upcalls to iw_cxgb4. Signed-off-by: Vipul Pandya <vipul@chelsio.com> Signed-off-by: Steve Wise <swise@opengridcomputing.com> Signed-off-by: Roland Dreier <roland@purestorage.com>
This commit is contained in:
Vipul Pandya
Roland Dreier
parent
8caa1e8446
commit
3069ee9bc4
6 changed files with 280 additions and 42 deletions
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@ -51,6 +51,8 @@
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#define FW_VERSION_MINOR 1
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#define FW_VERSION_MICRO 0
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#define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__)
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enum {
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MAX_NPORTS = 4, /* max # of ports */
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SERNUM_LEN = 24, /* Serial # length */
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@ -64,6 +66,15 @@ enum {
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MEM_MC
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};
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enum {
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MEMWIN0_APERTURE = 65536,
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MEMWIN0_BASE = 0x30000,
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MEMWIN1_APERTURE = 32768,
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MEMWIN1_BASE = 0x28000,
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MEMWIN2_APERTURE = 2048,
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MEMWIN2_BASE = 0x1b800,
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};
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enum dev_master {
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MASTER_CANT,
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MASTER_MAY,
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@ -403,6 +414,9 @@ struct sge_txq {
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struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */
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struct sge_qstat *stat; /* queue status entry */
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dma_addr_t phys_addr; /* physical address of the ring */
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spinlock_t db_lock;
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int db_disabled;
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unsigned short db_pidx;
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};
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struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */
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@ -475,6 +489,7 @@ struct adapter {
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void __iomem *regs;
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struct pci_dev *pdev;
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struct device *pdev_dev;
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unsigned int mbox;
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unsigned int fn;
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unsigned int flags;
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@ -607,6 +622,7 @@ irqreturn_t t4_sge_intr_msix(int irq, void *cookie);
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void t4_sge_init(struct adapter *adap);
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void t4_sge_start(struct adapter *adap);
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void t4_sge_stop(struct adapter *adap);
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extern int dbfifo_int_thresh;
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#define for_each_port(adapter, iter) \
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for (iter = 0; iter < (adapter)->params.nports; ++iter)
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@ -148,15 +148,6 @@ static unsigned int pfvfres_pmask(struct adapter *adapter,
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}
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#endif
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enum {
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MEMWIN0_APERTURE = 65536,
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MEMWIN0_BASE = 0x30000,
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MEMWIN1_APERTURE = 32768,
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MEMWIN1_BASE = 0x28000,
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MEMWIN2_APERTURE = 2048,
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MEMWIN2_BASE = 0x1b800,
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};
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enum {
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MAX_TXQ_ENTRIES = 16384,
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MAX_CTRL_TXQ_ENTRIES = 1024,
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@ -371,6 +362,15 @@ static int set_addr_filters(const struct net_device *dev, bool sleep)
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uhash | mhash, sleep);
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}
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int dbfifo_int_thresh = 10; /* 10 == 640 entry threshold */
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module_param(dbfifo_int_thresh, int, 0644);
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MODULE_PARM_DESC(dbfifo_int_thresh, "doorbell fifo interrupt threshold");
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int dbfifo_drain_delay = 1000; /* usecs to sleep while draining the dbfifo */
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module_param(dbfifo_drain_delay, int, 0644);
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MODULE_PARM_DESC(dbfifo_drain_delay,
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"usecs to sleep while draining the dbfifo");
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/*
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* Set Rx properties of a port, such as promiscruity, address filters, and MTU.
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* If @mtu is -1 it is left unchanged.
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@ -389,6 +389,8 @@ static int set_rxmode(struct net_device *dev, int mtu, bool sleep_ok)
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return ret;
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}
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static struct workqueue_struct *workq;
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/**
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* link_start - enable a port
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* @dev: the port to enable
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@ -2196,7 +2198,7 @@ static void cxgb4_queue_tid_release(struct tid_info *t, unsigned int chan,
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adap->tid_release_head = (void **)((uintptr_t)p | chan);
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if (!adap->tid_release_task_busy) {
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adap->tid_release_task_busy = true;
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schedule_work(&adap->tid_release_task);
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queue_work(workq, &adap->tid_release_task);
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}
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spin_unlock_bh(&adap->tid_release_lock);
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}
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@ -2423,6 +2425,59 @@ void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask,
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}
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EXPORT_SYMBOL(cxgb4_iscsi_init);
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int cxgb4_flush_eq_cache(struct net_device *dev)
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{
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struct adapter *adap = netdev2adap(dev);
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int ret;
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ret = t4_fwaddrspace_write(adap, adap->mbox,
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0xe1000000 + A_SGE_CTXT_CMD, 0x20000000);
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return ret;
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}
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EXPORT_SYMBOL(cxgb4_flush_eq_cache);
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static int read_eq_indices(struct adapter *adap, u16 qid, u16 *pidx, u16 *cidx)
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{
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u32 addr = t4_read_reg(adap, A_SGE_DBQ_CTXT_BADDR) + 24 * qid + 8;
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__be64 indices;
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int ret;
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ret = t4_mem_win_read_len(adap, addr, (__be32 *)&indices, 8);
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if (!ret) {
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indices = be64_to_cpu(indices);
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*cidx = (indices >> 25) & 0xffff;
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*pidx = (indices >> 9) & 0xffff;
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}
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return ret;
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}
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int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx,
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u16 size)
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{
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struct adapter *adap = netdev2adap(dev);
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u16 hw_pidx, hw_cidx;
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int ret;
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ret = read_eq_indices(adap, qid, &hw_pidx, &hw_cidx);
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if (ret)
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goto out;
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if (pidx != hw_pidx) {
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u16 delta;
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if (pidx >= hw_pidx)
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delta = pidx - hw_pidx;
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else
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delta = size - hw_pidx + pidx;
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wmb();
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t4_write_reg(adap, MYPF_REG(A_SGE_PF_KDOORBELL),
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V_QID(qid) | V_PIDX(delta));
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}
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out:
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return ret;
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}
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EXPORT_SYMBOL(cxgb4_sync_txq_pidx);
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static struct pci_driver cxgb4_driver;
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static void check_neigh_update(struct neighbour *neigh)
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@ -2456,6 +2511,95 @@ static struct notifier_block cxgb4_netevent_nb = {
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.notifier_call = netevent_cb
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};
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static void drain_db_fifo(struct adapter *adap, int usecs)
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{
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u32 v;
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do {
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set_current_state(TASK_UNINTERRUPTIBLE);
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schedule_timeout(usecs_to_jiffies(usecs));
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v = t4_read_reg(adap, A_SGE_DBFIFO_STATUS);
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if (G_LP_COUNT(v) == 0 && G_HP_COUNT(v) == 0)
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break;
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} while (1);
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}
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static void disable_txq_db(struct sge_txq *q)
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{
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spin_lock_irq(&q->db_lock);
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q->db_disabled = 1;
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spin_unlock_irq(&q->db_lock);
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}
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static void enable_txq_db(struct sge_txq *q)
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{
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spin_lock_irq(&q->db_lock);
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q->db_disabled = 0;
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spin_unlock_irq(&q->db_lock);
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}
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static void disable_dbs(struct adapter *adap)
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{
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int i;
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for_each_ethrxq(&adap->sge, i)
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disable_txq_db(&adap->sge.ethtxq[i].q);
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for_each_ofldrxq(&adap->sge, i)
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disable_txq_db(&adap->sge.ofldtxq[i].q);
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for_each_port(adap, i)
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disable_txq_db(&adap->sge.ctrlq[i].q);
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}
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static void enable_dbs(struct adapter *adap)
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{
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int i;
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for_each_ethrxq(&adap->sge, i)
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enable_txq_db(&adap->sge.ethtxq[i].q);
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for_each_ofldrxq(&adap->sge, i)
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enable_txq_db(&adap->sge.ofldtxq[i].q);
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for_each_port(adap, i)
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enable_txq_db(&adap->sge.ctrlq[i].q);
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}
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static void sync_txq_pidx(struct adapter *adap, struct sge_txq *q)
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{
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u16 hw_pidx, hw_cidx;
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int ret;
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spin_lock_bh(&q->db_lock);
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ret = read_eq_indices(adap, (u16)q->cntxt_id, &hw_pidx, &hw_cidx);
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if (ret)
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goto out;
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if (q->db_pidx != hw_pidx) {
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u16 delta;
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if (q->db_pidx >= hw_pidx)
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delta = q->db_pidx - hw_pidx;
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else
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delta = q->size - hw_pidx + q->db_pidx;
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wmb();
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t4_write_reg(adap, MYPF_REG(A_SGE_PF_KDOORBELL),
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V_QID(q->cntxt_id) | V_PIDX(delta));
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}
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out:
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q->db_disabled = 0;
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spin_unlock_bh(&q->db_lock);
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if (ret)
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CH_WARN(adap, "DB drop recovery failed.\n");
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}
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static void recover_all_queues(struct adapter *adap)
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{
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int i;
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for_each_ethrxq(&adap->sge, i)
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sync_txq_pidx(adap, &adap->sge.ethtxq[i].q);
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for_each_ofldrxq(&adap->sge, i)
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sync_txq_pidx(adap, &adap->sge.ofldtxq[i].q);
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for_each_port(adap, i)
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sync_txq_pidx(adap, &adap->sge.ctrlq[i].q);
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}
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static void notify_rdma_uld(struct adapter *adap, enum cxgb4_control cmd)
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{
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mutex_lock(&uld_mutex);
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@ -2468,55 +2612,41 @@ static void notify_rdma_uld(struct adapter *adap, enum cxgb4_control cmd)
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static void process_db_full(struct work_struct *work)
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{
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struct adapter *adap;
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static int delay = 1000;
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u32 v;
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adap = container_of(work, struct adapter, db_full_task);
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/* stop LLD queues */
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notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
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do {
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set_current_state(TASK_UNINTERRUPTIBLE);
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schedule_timeout(usecs_to_jiffies(delay));
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v = t4_read_reg(adap, A_SGE_DBFIFO_STATUS);
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if (G_LP_COUNT(v) == 0 && G_HP_COUNT(v) == 0)
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break;
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} while (1);
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drain_db_fifo(adap, dbfifo_drain_delay);
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t4_set_reg_field(adap, A_SGE_INT_ENABLE3,
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F_DBFIFO_HP_INT | F_DBFIFO_LP_INT,
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F_DBFIFO_HP_INT | F_DBFIFO_LP_INT);
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notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
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/*
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* The more we get db full interrupts, the more we'll delay
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* in re-enabling db rings on queues, capped off at 200ms.
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*/
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delay = min(delay << 1, 200000);
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/* resume LLD queues */
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}
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static void process_db_drop(struct work_struct *work)
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{
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struct adapter *adap;
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adap = container_of(work, struct adapter, db_drop_task);
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/*
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* sync the PIDX values in HW and SW for LLD queues.
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*/
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t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, F_DROPPED_DB, 0);
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disable_dbs(adap);
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notify_rdma_uld(adap, CXGB4_CONTROL_DB_DROP);
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drain_db_fifo(adap, 1);
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recover_all_queues(adap);
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enable_dbs(adap);
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}
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void t4_db_full(struct adapter *adap)
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{
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schedule_work(&adap->db_full_task);
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t4_set_reg_field(adap, A_SGE_INT_ENABLE3,
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F_DBFIFO_HP_INT | F_DBFIFO_LP_INT, 0);
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queue_work(workq, &adap->db_full_task);
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}
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void t4_db_dropped(struct adapter *adap)
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{
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schedule_work(&adap->db_drop_task);
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queue_work(workq, &adap->db_drop_task);
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}
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static void uld_attach(struct adapter *adap, unsigned int uld)
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@ -2552,6 +2682,7 @@ static void uld_attach(struct adapter *adap, unsigned int uld)
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lli.gts_reg = adap->regs + MYPF_REG(SGE_PF_GTS);
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lli.db_reg = adap->regs + MYPF_REG(SGE_PF_KDOORBELL);
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lli.fw_vers = adap->params.fw_vers;
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lli.dbfifo_int_thresh = dbfifo_int_thresh;
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handle = ulds[uld].add(&lli);
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if (IS_ERR(handle)) {
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@ -3668,6 +3799,7 @@ static int __devinit init_one(struct pci_dev *pdev,
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adapter->pdev = pdev;
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adapter->pdev_dev = &pdev->dev;
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adapter->mbox = func;
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adapter->fn = func;
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adapter->msg_enable = dflt_msg_enable;
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memset(adapter->chan_map, 0xff, sizeof(adapter->chan_map));
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@ -3865,6 +3997,10 @@ static int __init cxgb4_init_module(void)
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{
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int ret;
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workq = create_singlethread_workqueue("cxgb4");
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if (!workq)
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return -ENOMEM;
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/* Debugfs support is optional, just warn if this fails */
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cxgb4_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL);
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if (!cxgb4_debugfs_root)
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@ -3880,6 +4016,8 @@ static void __exit cxgb4_cleanup_module(void)
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{
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pci_unregister_driver(&cxgb4_driver);
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debugfs_remove(cxgb4_debugfs_root); /* NULL ok */
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flush_workqueue(workq);
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destroy_workqueue(workq);
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}
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module_init(cxgb4_init_module);
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@ -218,6 +218,7 @@ struct cxgb4_lld_info {
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unsigned short ucq_density; /* # of user CQs/page */
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void __iomem *gts_reg; /* address of GTS register */
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void __iomem *db_reg; /* address of kernel doorbell */
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int dbfifo_int_thresh; /* doorbell fifo int threshold */
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};
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struct cxgb4_uld_info {
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@ -226,6 +227,7 @@ struct cxgb4_uld_info {
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int (*rx_handler)(void *handle, const __be64 *rsp,
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const struct pkt_gl *gl);
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int (*state_change)(void *handle, enum cxgb4_state new_state);
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int (*control)(void *handle, enum cxgb4_control control, ...);
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};
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int cxgb4_register_uld(enum cxgb4_uld type, const struct cxgb4_uld_info *p);
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@ -243,4 +245,6 @@ void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask,
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const unsigned int *pgsz_order);
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struct sk_buff *cxgb4_pktgl_to_skb(const struct pkt_gl *gl,
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unsigned int skb_len, unsigned int pull_len);
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int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx, u16 size);
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int cxgb4_flush_eq_cache(struct net_device *dev);
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#endif /* !__CXGB4_OFLD_H */
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@ -767,8 +767,13 @@ static void write_sgl(const struct sk_buff *skb, struct sge_txq *q,
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static inline void ring_tx_db(struct adapter *adap, struct sge_txq *q, int n)
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{
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wmb(); /* write descriptors before telling HW */
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t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL),
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QID(q->cntxt_id) | PIDX(n));
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spin_lock(&q->db_lock);
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if (!q->db_disabled) {
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t4_write_reg(adap, MYPF_REG(A_SGE_PF_KDOORBELL),
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V_QID(q->cntxt_id) | V_PIDX(n));
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}
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q->db_pidx = q->pidx;
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spin_unlock(&q->db_lock);
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}
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/**
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@ -2081,6 +2086,7 @@ static void init_txq(struct adapter *adap, struct sge_txq *q, unsigned int id)
|
|||
q->stops = q->restarts = 0;
|
||||
q->stat = (void *)&q->desc[q->size];
|
||||
q->cntxt_id = id;
|
||||
spin_lock_init(&q->db_lock);
|
||||
adap->sge.egr_map[id - adap->sge.egr_start] = q;
|
||||
}
|
||||
|
||||
|
|
@ -2415,9 +2421,15 @@ void t4_sge_init(struct adapter *adap)
|
|||
RXPKTCPLMODE |
|
||||
(STAT_LEN == 128 ? EGRSTATUSPAGESIZE : 0));
|
||||
|
||||
/*
|
||||
* Set up to drop DOORBELL writes when the DOORBELL FIFO overflows
|
||||
* and generate an interrupt when this occurs so we can recover.
|
||||
*/
|
||||
t4_set_reg_field(adap, A_SGE_DBFIFO_STATUS,
|
||||
V_HP_INT_THRESH(5) | V_LP_INT_THRESH(5),
|
||||
V_HP_INT_THRESH(5) | V_LP_INT_THRESH(5));
|
||||
V_HP_INT_THRESH(M_HP_INT_THRESH) |
|
||||
V_LP_INT_THRESH(M_LP_INT_THRESH),
|
||||
V_HP_INT_THRESH(dbfifo_int_thresh) |
|
||||
V_LP_INT_THRESH(dbfifo_int_thresh));
|
||||
t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, F_ENABLE_DROP,
|
||||
F_ENABLE_DROP);
|
||||
|
||||
|
|
|
|||
|
|
@ -190,6 +190,59 @@
|
|||
#define SGE_DEBUG_DATA_LOW 0x10d4
|
||||
#define SGE_INGRESS_QUEUES_PER_PAGE_PF 0x10f4
|
||||
|
||||
#define S_LP_INT_THRESH 12
|
||||
#define V_LP_INT_THRESH(x) ((x) << S_LP_INT_THRESH)
|
||||
#define S_HP_INT_THRESH 28
|
||||
#define V_HP_INT_THRESH(x) ((x) << S_HP_INT_THRESH)
|
||||
#define A_SGE_DBFIFO_STATUS 0x10a4
|
||||
|
||||
#define S_ENABLE_DROP 13
|
||||
#define V_ENABLE_DROP(x) ((x) << S_ENABLE_DROP)
|
||||
#define F_ENABLE_DROP V_ENABLE_DROP(1U)
|
||||
#define A_SGE_DOORBELL_CONTROL 0x10a8
|
||||
|
||||
#define A_SGE_CTXT_CMD 0x11fc
|
||||
#define A_SGE_DBQ_CTXT_BADDR 0x1084
|
||||
|
||||
#define A_SGE_PF_KDOORBELL 0x0
|
||||
|
||||
#define S_QID 15
|
||||
#define V_QID(x) ((x) << S_QID)
|
||||
|
||||
#define S_PIDX 0
|
||||
#define V_PIDX(x) ((x) << S_PIDX)
|
||||
|
||||
#define M_LP_COUNT 0x7ffU
|
||||
#define S_LP_COUNT 0
|
||||
#define G_LP_COUNT(x) (((x) >> S_LP_COUNT) & M_LP_COUNT)
|
||||
|
||||
#define M_HP_COUNT 0x7ffU
|
||||
#define S_HP_COUNT 16
|
||||
#define G_HP_COUNT(x) (((x) >> S_HP_COUNT) & M_HP_COUNT)
|
||||
|
||||
#define A_SGE_INT_ENABLE3 0x1040
|
||||
|
||||
#define S_DBFIFO_HP_INT 8
|
||||
#define V_DBFIFO_HP_INT(x) ((x) << S_DBFIFO_HP_INT)
|
||||
#define F_DBFIFO_HP_INT V_DBFIFO_HP_INT(1U)
|
||||
|
||||
#define S_DBFIFO_LP_INT 7
|
||||
#define V_DBFIFO_LP_INT(x) ((x) << S_DBFIFO_LP_INT)
|
||||
#define F_DBFIFO_LP_INT V_DBFIFO_LP_INT(1U)
|
||||
|
||||
#define S_DROPPED_DB 0
|
||||
#define V_DROPPED_DB(x) ((x) << S_DROPPED_DB)
|
||||
#define F_DROPPED_DB V_DROPPED_DB(1U)
|
||||
|
||||
#define S_ERR_DROPPED_DB 18
|
||||
#define V_ERR_DROPPED_DB(x) ((x) << S_ERR_DROPPED_DB)
|
||||
#define F_ERR_DROPPED_DB V_ERR_DROPPED_DB(1U)
|
||||
|
||||
#define A_PCIE_MEM_ACCESS_OFFSET 0x306c
|
||||
|
||||
#define M_HP_INT_THRESH 0xfU
|
||||
#define M_LP_INT_THRESH 0xfU
|
||||
|
||||
#define PCIE_PF_CLI 0x44
|
||||
#define PCIE_INT_CAUSE 0x3004
|
||||
#define UNXSPLCPLERR 0x20000000U
|
||||
|
|
|
|||
|
|
@ -1620,4 +1620,19 @@ struct fw_hdr {
|
|||
#define FW_HDR_FW_VER_MINOR_GET(x) (((x) >> 16) & 0xff)
|
||||
#define FW_HDR_FW_VER_MICRO_GET(x) (((x) >> 8) & 0xff)
|
||||
#define FW_HDR_FW_VER_BUILD_GET(x) (((x) >> 0) & 0xff)
|
||||
|
||||
#define S_FW_CMD_OP 24
|
||||
#define V_FW_CMD_OP(x) ((x) << S_FW_CMD_OP)
|
||||
|
||||
#define S_FW_CMD_REQUEST 23
|
||||
#define V_FW_CMD_REQUEST(x) ((x) << S_FW_CMD_REQUEST)
|
||||
#define F_FW_CMD_REQUEST V_FW_CMD_REQUEST(1U)
|
||||
|
||||
#define S_FW_CMD_WRITE 21
|
||||
#define V_FW_CMD_WRITE(x) ((x) << S_FW_CMD_WRITE)
|
||||
#define F_FW_CMD_WRITE V_FW_CMD_WRITE(1U)
|
||||
|
||||
#define S_FW_LDST_CMD_ADDRSPACE 0
|
||||
#define V_FW_LDST_CMD_ADDRSPACE(x) ((x) << S_FW_LDST_CMD_ADDRSPACE)
|
||||
|
||||
#endif /* _T4FW_INTERFACE_H_ */
|
||||
|
|
|
|||
Loading…
Reference in a new issue