ARM: mvebu: use the common function for Armada 375 SMP workaround
Use the common function mvebu_setup_boot_addr_wa() introduced in the commit "ARM: mvebu: Add a common function for the boot address work around" instead of the dedicated version for Armada 375. This commit also moves the workaround in the system-controller module. Indeed the workaround on 375 is really related to setting the boot address which is done by the system controller. As a bonus we no longer use an harcoded value to access the register storing the boot address. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1406120453-29291-5-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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3 changed files with 34 additions and 54 deletions
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@ -18,21 +18,6 @@
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#include <asm/assembler.h>
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__CPUINIT
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#define CPU_RESUME_ADDR_REG 0xf10182d4
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.global armada_375_smp_cpu1_enable_code_start
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.global armada_375_smp_cpu1_enable_code_end
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armada_375_smp_cpu1_enable_code_start:
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ARM_BE8(setend be)
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adr r0, 1f
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ldr r0, [r0]
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ldr r1, [r0]
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ARM_BE8(rev r1, r1)
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mov pc, r1
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1:
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.word CPU_RESUME_ADDR_REG
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armada_375_smp_cpu1_enable_code_end:
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ENTRY(mvebu_cortex_a9_secondary_startup)
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ARM_BE8(setend be)
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@ -20,33 +20,8 @@
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#include <asm/smp_scu.h>
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#include <asm/smp_plat.h>
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#include "common.h"
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#include "mvebu-soc-id.h"
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#include "pmsu.h"
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#define CRYPT0_ENG_ID 41
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#define CRYPT0_ENG_ATTR 0x1
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#define SRAM_PHYS_BASE 0xFFFF0000
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#define BOOTROM_BASE 0xFFF00000
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#define BOOTROM_SIZE 0x100000
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extern unsigned char armada_375_smp_cpu1_enable_code_end;
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extern unsigned char armada_375_smp_cpu1_enable_code_start;
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static void armada_375_smp_cpu1_enable_wa(void)
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{
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void __iomem *sram_virt_base;
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mvebu_mbus_del_window(BOOTROM_BASE, BOOTROM_SIZE);
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mvebu_mbus_add_window_by_id(CRYPT0_ENG_ID, CRYPT0_ENG_ATTR,
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SRAM_PHYS_BASE, SZ_64K);
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sram_virt_base = ioremap(SRAM_PHYS_BASE, SZ_64K);
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memcpy(sram_virt_base, &armada_375_smp_cpu1_enable_code_start,
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&armada_375_smp_cpu1_enable_code_end
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- &armada_375_smp_cpu1_enable_code_start);
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}
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extern void mvebu_cortex_a9_secondary_startup(void);
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static int __cpuinit mvebu_cortex_a9_boot_secondary(unsigned int cpu,
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@ -63,21 +38,10 @@ static int __cpuinit mvebu_cortex_a9_boot_secondary(unsigned int cpu,
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* address.
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*/
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hw_cpu = cpu_logical_map(cpu);
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if (of_machine_is_compatible("marvell,armada375")) {
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u32 dev, rev;
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if (mvebu_get_soc_id(&dev, &rev) == 0 &&
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rev == ARMADA_375_Z1_REV)
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armada_375_smp_cpu1_enable_wa();
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if (of_machine_is_compatible("marvell,armada375"))
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mvebu_system_controller_set_cpu_boot_addr(mvebu_cortex_a9_secondary_startup);
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}
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else {
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mvebu_pmsu_set_cpu_boot_addr(hw_cpu,
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mvebu_cortex_a9_secondary_startup);
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}
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else
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mvebu_pmsu_set_cpu_boot_addr(hw_cpu, mvebu_cortex_a9_secondary_startup);
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smp_wmb();
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ret = mvebu_cpu_reset_deassert(hw_cpu);
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if (ret) {
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@ -28,8 +28,14 @@
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#include <linux/io.h>
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#include <linux/reboot.h>
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#include "common.h"
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#include "mvebu-soc-id.h"
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#include "pmsu.h"
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#define ARMADA_375_CRYPT0_ENG_TARGET 41
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#define ARMADA_375_CRYPT0_ENG_ATTR 1
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static void __iomem *system_controller_base;
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static phys_addr_t system_controller_phys_base;
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struct mvebu_system_controller {
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u32 rstoutn_mask_offset;
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@ -121,10 +127,32 @@ int mvebu_system_controller_get_soc_id(u32 *dev, u32 *rev)
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}
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#ifdef CONFIG_SMP
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void mvebu_armada375_smp_wa_init(void)
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{
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u32 dev, rev;
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phys_addr_t resume_addr_reg;
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if (mvebu_get_soc_id(&dev, &rev) != 0)
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return;
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if (rev != ARMADA_375_Z1_REV)
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return;
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resume_addr_reg = system_controller_phys_base +
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mvebu_sc->resume_boot_addr;
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mvebu_setup_boot_addr_wa(ARMADA_375_CRYPT0_ENG_TARGET,
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ARMADA_375_CRYPT0_ENG_ATTR,
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resume_addr_reg);
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}
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void mvebu_system_controller_set_cpu_boot_addr(void *boot_addr)
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{
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BUG_ON(system_controller_base == NULL);
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BUG_ON(mvebu_sc->resume_boot_addr == 0);
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if (of_machine_is_compatible("marvell,armada375"))
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mvebu_armada375_smp_wa_init();
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writel(virt_to_phys(boot_addr), system_controller_base +
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mvebu_sc->resume_boot_addr);
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}
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@ -138,7 +166,10 @@ static int __init mvebu_system_controller_init(void)
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np = of_find_matching_node_and_match(NULL, of_system_controller_table,
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&match);
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if (np) {
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struct resource res;
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system_controller_base = of_iomap(np, 0);
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of_address_to_resource(np, 0, &res);
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system_controller_phys_base = res.start;
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mvebu_sc = (struct mvebu_system_controller *)match->data;
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of_node_put(np);
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}
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